QUICK LOGIC QL5432-33APB456C, QL5432-33APB456I, QL5432-33APQ208C, QL5432-33APQ208I Datasheet

33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM

QL5432 - Enhanced QuickPCI

Device

last updated 2/5/01

Rev A

■ Supports all PCI commands (including configuration

and MWI)

■ Supports fully-customizable byte enables as a master

■ Zero-wait-state write and one-wait-state read target

interface

■ Supports all types of PCI target terminations: disconnect

with data transfer, disconnect without data transfer, and retry

■ Supports target aborts

■ Has 125 more logic cells in FPGA section, but 2 less

RAM blocks

■ Pin Compatible with QL5232

High Performance PCI Controller

■ 32-bit / 33 MHz PCI Master/Target

■ Zero-wait state PCI Master provides 132 MB/s

transfer rates

■ Zero-wait-state PCI Target Write/One-wait-state PCI

Target Read interface

■ Supports all PCI commands, including configuration

and MWI

■ Supports fully-customizable byte enable for master

channels

■ Target interface supports retry, disconnect with/without

data transfer, and target abort

■ Programmable back-end interface to optional local

processor

■ Independent PCI bus (33 MHz) and local bus

(up to 160 MHz) clocks

■ Fully customizable PCI Configuration Space

■ Configurable FIFOs with depths up to 256

■ Reference design with driver code (Win 95/98/

Win 2000/NT4.0) available

■ PCI v2.2 compliant

■ Supports Type 0 Configuration Cycles in Target mode

■ 3.3V, 5V Tolerant PCI signaling supports Universal

PCI Adapter designs

■ 3.3V CMOS in 208-pin PQFP and 456-pin PBGA

■ Supports endian conversions

■ Unlimited/Continuous Burst Transfers supported

FIGURE 1. QL5432 Diagram

Extendable PCI Functionality

■ Support for PCI host-bridge function

■ Support for Configuration Space from 0x40 to 0x3FF

■ Multi-Function, Expanded Capabilities, & Expansion

ROM capable

■ Power management, Compact PCI, hot-swap/

hot-plug compatible

■ PCI v2.2 Power Management Spec compatible

■ PCI v2.2 Vital Product Data (VPD) configuration support

■ Programmable Interrupt Generator

■ I

O support with local processor

■ Mailbox register support

Programmable Logic

■ 1427 Logic Cells

■ 23,040 RAM bits, up to 266 I/O pins

■ 250 MHz 16-bit counters, 275 MHz Datapaths, 160

MHz FIFOs

■ All back-end interface and glue-logic can be implemented

on chip

■ Any combination of FIFOs that require 20 or less

QuickLogic RAM Modules

■ Six 32-bit busses interface between the PCI Controller

and the Programmable Logic

QL5432 - Enhanced QL5232

Device Highlights

Config

Space

160 MHz

FIFOs

MASTER

CONTROLLER

INTERFACE

PROGRAMMABLE LOGIC

PCI Bus – 33 MHz 32 bits (data and address)

266 User I/O

PCI CONTROLLER

DMA

Controller

HIGH

SPEED

DATA PATH

High Speed

Logic Cells

TARGET

CONTROLLER

2 Preliminary

QL5432 - QuickPCI

The QL5432 device in the QuickLogic QuickPCI ESP (Embedded Standard Product) family provides a complete and customizable PCI interface solution combined with programmable logic. This device eliminates any need for the designer to worry about PCI bus compliance, yet allows for the maximum 32bit PCI bus bandwidth (132 MB/s).

The programmable logic portion of the device contains 1427 QuickLogic Logic Cells, and 20 QuickLogic Dual-Port RAM Blocks. These configurable RAM blocks can be configured in many width/depth combinations. They can also be combined with logic cells to form FIFOs, or be initialized via Serial EEPROM on power-up and used as ROMs.

The QL5432 device meets PCI 2.2 electrical and timing specifications and has been fully hardwaretested. This device also supports the Win'98 and PC'98 standards. The QL5432 device features 3.3volt operation with multi-volt compatible I/Os. Thus it can easily operate in 3-volt systems and is fully compatible with 3.3V, 5V or Universal PCI card applications.

The PCI Controller is a 32-bit/33 MHz PCI 2.2 Compliant Master/Target Controller. It is capable of infinite length Master Write and Read transactions at zero wait states (132 MBytes/second). The Master will never insert wait states during transfers, so data should be supplied or received by FIFOs, which can be configured in the programmable region of the device. The Master is capable of initiating any type of PCI command, including configuration cycles and Memory Write and Invalidate (MWI). This enables the QL5432 device to act as a PCI host. The Master Controller will most often be operated by a DMA Controller in the programmable region of the device. A DMA Controller reference design is available.

The Target interface offers full PCI Configuration Space and flexible target addressing. It supports zerowait-state target write and one-wait-state target read operations. It also supports retry, disconnect with/ without data transfer, and target abort requested by the backend. Any number of 32-bit BARs may be configured, as either memory or I/O space. All required and optional PCI 2.2 Configuration Space registers can be implemented within the programmable region of the device. A reference design of a Target Configuration and Addressing module is provided.

The interface ports are divided into a set of ports for master transactions and a set for target transactions. The Master DMA controller and Target Configuration Space and Address Decoding are done in the programmable logic region of the device. Since these functions are not timing critical, leaving these elements in the programmable region allows the greatest degree of flexibility to the designer. Reference DMA controller, Configuration Space, and Address Decoding blocks are included so that the design cycle can be minimized.

The configuration space is completely customizable in the programmable region of the device. PCI address and command decoding is performed by logic in the programmable section of the device. This allows support for any size of memory or I/O space for back-end logic. It also allows the user to implement any subset of the PCI commands supported by the QL5432. QuickLogic provides a reference Address Register/Counter and Command Decode block.

Architecture Overview

PCI Controller

Configuration Space and

Address Decode

QL5432 - QuickPCI

The customizable DMA controller included with the QuickWorks design software contains the following features:

■ Configurable DMA count size for Reads and Writes

(up to 30-bits)

■ Configurable DMA burst size for PCI (including

unlimited/continuous burst)

■ Customizable PCI command to use by core

■ Customizable Byte Enable signal

■ Programmable Arbitration between DMA Read &

Write transactions

■ DMA Registers may be mapped to any area of

Target Memory S p ac e

- Read Address (32-bit register)

- Write Address (32-bit register)

- Read Length (16-bit register) / Write Length (16-bit register)

- Control and Status (32-bit register, includes 8 bit Burst Length)

■ DMA Registers are available to the local design or

the PCI bus

■ Programmable Interrupt Control to signal end of

transfer or other event

FIFOs may be created with the RAM/FIFO wizard in the QuickWorks tools. The figure below shows the graphical interface used to create these FIFOs. FIFOs may be designed up to 256 deep. With 20 RAM cells available in the QL5432, that allows for up to 10 FIFOs at 64 deep (36 wide), 5 FIFOs at 128 deep (36 wide), 2 FIFOs at 256 deep (40 wide),or 1 FIFO at 512 deep (40 wide).

FIGURE 2: Graphical Interface to create FIFO

DMA Master/Target Control Configurable FIFOs

4 Preliminary

QL5432 - QuickPCI

The figure below shows the interface symbol you would use in your schematic design in order to attach the local interface programmable logic design to the PCI core. If you were designing with a top-level Verilog or VHDL file, then you would use a structural instantiation of this PCI32N block, instead of a graphical symbol.

FIGURE 3: PCI Interface Symbol

PCI Interface Symbol

QL5432 - QuickPCI

The internal signals used to interface with the PCI controller in the QL5432 are listed below, along with a description of each signal. The direction of the signal indicates if it is an input provided by the local interface (i) or an output provided by the PCI controller (o). Signals that end with the character ‘N’ should be considered active-low (for example,

Mst_IRDYN

PCI_Cmd[3 :0] I PCI command to b e u se d for the master tran saction. This sig na l must remain unchan ge d throughout the perio d

when Mst_Burst_Req is active. PCI commands considered as reads include Interrupt Acknowledge, I/O Read, Memory Read, Configuration Read, Memory Read Multiple, Memory Read Line. PCI commands considered as writes include Special Cycle, I/O Write, Memory Write, Configuration Write, Memory Write and Invalidate. Users should make sure that only valid PCI commands are supplied.

Mst_Burst_Req I Request use of the PCI bus. When it is active, the core requests the PCI bus and then generates a master trans-

action. This signal should be held active until all requested data are transferred on the PCI bus and deactivated in the 2nd clock cycle following the last data transfer on PCI (to avoid being considered as requesting a new transaction).

Mst_WrAd[31:0] I Address for master DMA writes. This address must be treated as valid from the beginning of a DMA write until

the DMA write operation is complete. It should be incremented (by 4 bytes) each time data is transferred on the PCI bus.

Mst_RdAd[31:0] I Address for master DMA reads. This address must be treated as valid from the beginning of a DMA read until

the DMA read operation is complete. It should be incremented (by 4 bytes) each time data is transferred on the

PCI bus. Mst_WrData[31:0] I Data for master DMA writes (to PCI bus). Mst_BE[3:0] I Byte enables for master DMA reads and writes. Active-low. Mst_WrData_Valid I Data and byte enable valid on Mst_WrData[31:0] (for master write only) and Mst_BE[3:0] (for both master read

and write). Mst_WrData_Rdy O Data receive acknowledge for Mst_WrData[31:0] (for master write only) and Mst_BE[3:0] (for both). This

serves as the PUSH control for the internal FIFO and the POP control for the external FIFO (in FPGA region)

which provides data and byte enables to the PCI32 core. Mst_BE_Sel I Byte enable select for master transactions. When low, Mst_BE[3:0] should remain constant throughout the

entire transfer (when Mst_Burst_Req is active) and it is used for every data phase of the master transaction.

When high, Mst_BE[3:0] pushed into internal FIFO (along with data in case of master write) is used. Should be

held constant throughout the transaction. Mst_WrBurst_Done O Master write transaction is completed. Active for only one clock cycle. Mst_Rd_Term_Sel I Master read termination mode select when Mst_BE_Sel is high. When both Mst_BE_Sel and

Mst_Rd_Term_Sel are high, master read termination happens when the internal FIFO is empty, and

Mst_Two_Reads and Mst_One_Read are ignored. When either signal is low, Mst_Two_Reads and

Mst_One_Read are used to signal end of master read. Should be held constant throughout the transaction. Mst_One_Read I This signals to the PCI32 core that only one data transfer remains to be read in the burst read. Mst_Two_Reads I Two data transfers remain to be read in the burst read. It is not used for single-data-phase master read

transactions. Mst_RdData_Valid O Master read data valid on Usr_Addr_WrData[31:0]. This serves as the PUSH control for the external FIFO (in

FPGA region) that receives data from the PCI32 core. Mst_RdBurst_Done O Master read transaction is completed. Active for only one clock cycle. Flush_FIFO I Internal FIFO flush. FIFO flushed immediately after it is active (synchronized with PCI clock). Mst_LatCntEn I Enable Latency Counter. Set to 0 to ignore the Latency Timer in the PCI configuration space (offset 0Ch).

For full PCI compliance, this port should be always set to 1. Mst_Xfer_D1 O Data was transferred on the previous PCI clock. Useful for updating DMA transfer counts on DMA Read

operations. Mst_Last_Cycle O Active during the last data transfer of a master transaction. Mst_REQN O Copy of the PCI REQN signal generated by QL5x33 as PCI master. Not usually used in the back-end design.

PCI Master Interface

6 Preliminary

QL5432 - QuickPCI

Mst_IRDYN O Copy of the PCI IRDYN signal generated by QL5x33 as PCI master. Valid only when QL5x33 is the PCI mas-

ter. Kept low otherwise. Not usually used in the back-end design.

Mst_Tabort_Det O Target abort detected during master transaction. This is normally an error condition to be handled in the DMA

controller.

Mst_TTO_Det O Target timeout detected (no response from target). This is normally an error condition to be handled in the

DMA controller.

Usr_Addr_WrData[31:0] O Target address, and target write data. During all target accesses, the address is presented on

Usr_Addr_WrData[31:0] at the same time Usr_Adr_Valid is active. During target write transactions, this port also presents valid write data to the PCI configuration space or user logic when Usr_Adr_Inc is active.

Usr_CBE[3:0] O PCI command and byte enables. During target accesses, the PCI command is presented on Usr_CBE[3:0]

at the same time Usr_Adr_Valid is active. This port also presents active-low byte enables to the PCI configuration space or user logic.

Usr_Adr_Valid O Indicates the beginning of a PCI transaction, and that a target address is valid on Usr_Addr_WrData[31:0]

and the PCI command is valid on Usr_CBE[3:0]. When this signal is active, the target address must be latched and decoded to determine if this address belongs to the device's memory or I/O space. Also, the PCI command must be decoded to determine the type of PCI transaction. On subsequent clocks of a target access, this signal is low, indicating that address is NOT present on Usr_Addr_WrData[31:0].

Usr_Adr_Inc O Indicates that the target address should be incremented, because the previous data transfer has com-

pleted. During burst target accesses, the target address is only presented to the back-end logic at the beginning of the transaction (when Usr_Adr_Valid is active), and must therefore be latched and incremented (by 4) for subsequent data transfers. Note that during target write transactions, Usr_Adr_Inc indicates valid data on Usr_Addr_WrData[31:0] that must be accepted by the backend logic (regardless of the state of Usr_Rdy). During read transactions, Usr_Adr_Inc signals to the backend that the PCI core has presented the read data on the PCI bus (TRDYN asserted).

Usr_RdDecode I This signal should be the combinatorial decode of the "user read" command from Usr_CBE[3:0]. This

command may be mapped from any of the PCI "read" commands, such as Memory Read, Memory Read Line, Memory Read Multiple, I/O Read, etc. It is internally gated with Usr_Adr_Valid.

Usr_WrDecode I This signal should be the combinatorial decode of the "user write" command from Usr_CBE[3:0]. This

command may be mapped from any of the PCI "write" commands, such as Memory Write or I/O Write. It is internally gated with Usr_Adr_Valid.

Usr_Select I This signal should be driven active when the address on Usr_Addr_WrData[31:0] has been decoded and

determined to be within the address space of the device. Usr_Addr_WrData[31:0] must be compared to each of the valid Base Address Registers in the PCI configuration space. Also, this signal must be gated by the Memory Access Enable or I/O Access Enable registers in the PCI configuration space (Command Register bits 1 or 0 at offset 04h). Internally gated with Usr_Adr_Valid.

Usr_Write O This signal is active throughout a "user write" transaction, which has been decoded by Usr_WrDecode at

the beginning of the transaction. The write strobe for individual DWORDs of data (on Usr_Addr_WrData[31:0]) during a user write transaction should be generated by logically ANDing this signal with Usr_Adr_Inc.

Cfg_Write O This signal is active throughout a "configuration write" transaction. The write strobe for individual

DWORDs of data (on Usr_Addr_WrData[31:0]) during a configuration write transaction should be generated by logically ANDing this signal with Usr_Adr_Inc.

Usr_Read O This signal is active throughout a "user read" transaction, which has been decoded by Usr_RdDecode at

the beginning of the transaction. Cfg_Read O This signal is active throughout a "configuration read" transaction. Cfg_RdData[31:0] I Data from the PCI configuration registers, required to be presented during PCI configuration reads. Usr_RdData[31:0] I Data from the back-end user logic, required to be presented during PCI user reads.

PCI Target Interface

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