Quantum CR84A101, Fireball CR 8.4AT Product manual

Quantum Fireball CR 4.3/6.4/8.4/13.0 GB AT

Product Manual

Quantum Fireball CR 4.3/6.4/8.4/13.0 GB AT

Product Manual

January, 1999
81-119270-01

Quantum reserves the right to make changes and improvements to its products, without incurring any
obligation to incorporate such changes or improvements into units previously sold or shipped.

You can request Quantum publications from your Quantum Sales Representative or order them directly
from Quantum.

Publication Number: 81-119270-01

UL/CSA/TUV/CE

UL standard 1950 recognition granted under File No. E78016
CSA standard C22.2 No. 950 certification granted under File No. LR49896
TUV Rheinland EN 60 950 granted under File No. R 9677196
Tested to FCC Rules for Radiated and Conducted Emissions, Part 15, Sub Part J, for Class-B Equipment.

SERVICE CENTERS

Quantum Service Center Quantum Asia-Pacific Pte. Ltd. Quantum Customer Service Group
715 Sycamore Avenue 50 Tagore Lane #b1-04 Quantum Ireland Ltd.
Milpitas, California 95035 Singapore, 2678 Finnabair Industrial Park
Phone: [phone] Phone: [phone] Dundalk
Fax: [phone] Fax: [phone] County Louth, Ireland
http://www.quantum.com Tel: [phone]

Fax: [phone]

PATENTS

These products are covered by or licensed under one or more of the following U.S. Patents:
4,419,701; 4, 538,193 4,625,109; 4,639,798; 4,647,769; 4,647,997; 4,661,696; 4,669,004; 4,675,652;
4,703,176; 4,730,321; 4,772,974; 4,783,705; 4,819,153; 4,882,671; 4,920,442; 4,920,434; 4,982,296;
5,005,089; 5,027,241; 5,031,061; 5,084,791; 5,119,254; 5,160,865; 5,170,229; 5,177,771; Other U.S. and
Foreign Patents Pending.

©

1998 Quantum Corporation. All rights reserved. Printed in U.S.A.

Quantum, the Quantum logo, and AIRLOCK are trademarks of Quantum Corporation, registered in the
U.S.A. and other countries. Capacity for the extraordinary, Quantum Fireball CR, AutoTransfer, AutoRead,
AutoWrite, DisCache, DiskWare, Defect Free Interface, and WriteCache are trademarks of Quantum
Corporation. All other brand names or trademarks are the property of their manufacturers.

This product or document is protected by copyright and distributed under licenses restricting its use,
copying, distribution, and decompilation. No part of this product or document may be reproduced in any
form by any means without prior written authorization of Quantum and its licensors, if any.

RESTRICTED RIGHTS LEGEND: Use, duplication, or disclosure by the government is subject to restrictions
as set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at
DFARS 252.227-7013 and FAR 52.227-19.

THIS PUBLICATION IS PROVIDED “AS IS’ WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR
IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.

Table of Contents

Chapter 1
ABOUT THIS MANUAL

AUDIENCE DEFINITION .......................................................................................................................... 1-1

MANUAL ORGANIZATION ....................................................................................................................1-1

TERMINOLOGY AND CONVENTIONS ................................................................................................... 1-1

REFERENCES ............................................................................................................................................ 1-3

Chapter 2
GENERAL DESCRIPTION

PRODUCT OVERVIEW ............................................................................................................................2-1

KEY FEATURES .......................................................................................................................................2-1

STANDARDS AND REGULATIONS ....................................................................................................... 2-3

HARDWARE REQUIREMENTS ............................................................................................................... 2-3

Chapter 3
INSTALLATION

SPACE REQUIREMENTS ......................................................................................................................... 3-1

UNPACKING INSTRUCTIONS ................................................................................................................. 3-2

HARDWARE OPTIONS ............................................................................................................................ 3-4

Cable Select (CS) Jumper ................................................................................................................ 3-5

Drive Select (DS) Jumper ................................................................................................................ 3-6

Jumper Parking (PK) Position ........................................................................................................ 3-6

Master Jumper configuration ......................................................................................................... 3-6

Reserved Position ............................................................................................................................. 3-6

ATA BUS ADAPTER ................................................................................................................................ 3-7

40-Pin ATA Bus Connector ............................................................................................................ 3-7

Adapter Board .................................................................................................................................. 3-7

MOUNTING ............................................................................................................................................... 3-8

Orientation ........................................................................................................................................ 3-8

Clearance .........................................................................................................................................3-11

Ventilation ...................................................................................................................................... 3-11

COMBINATION CONNECTOR (J1) ....................................................................................................... 3-11

DC Power (J1, Section A) ..............................................................................................................3-12

External Drive Activity LED .........................................................................................................3-12

ATA Bus Interface Connector (J1, Section C) .............................................................................3-12

FOR SYSTEMS WITH A MOTHERBOARD ATA ADAPTER ..............................................................3-13

FOR SYSTEMS WITH AN ATA ADAPTER BOARD ...........................................................................3-13

Adapter Board Installation ........................................................................................................... 3-13

TECHNIQUES IN DRIVE CONFIGURATION ........................................................................................3-15

Quantum Fireball CR 4.3/6.4/.8.4/13.0AT iii

Table of Contents

The 528-Megabytes Barrier ...........................................................................................................3-15

The 8.4-Gigabytes Barrier .............................................................................................................3-16

Operating system limitations............................................................................................. 3-16

SYSTEM STARTUP AND OPERATION ................................................................................................3-17

Chapter 4
SPECIFICATIONS

SPECIFICATION SUMMARY ...................................................................................................................4-1

FORMATTED CAPACITY .........................................................................................................................4-3

DATA TRANSFER RATES .......................................................................................................................4-3

TIMING SPECIFICATIONS .......................................................................................................................4-4

POWER ...................................................................................................................................................... 4-5

Power Sequencing ............................................................................................................................4-5

Power Reset Limits ...........................................................................................................................4-5

Power Requirements ........................................................................................................................4-6

ACOUSTICS ............................................................................................................................................... 4-7

MECHANICAL ..........................................................................................................................................4-8

ENVIRONMENTAL CONDITIONS ...........................................................................................................4-8

SHOCK AND VIBRATION ........................................................................................................................4-9

HANDLING the DRIVE ............................................................................................................................4-9

RELIABILITY ........................................................................................................................................... 4-10

ELECTROMAGNETIC SUSCEPTIBILITY ...............................................................................................4-10

EMITTED VIBRATION ............................................................................................................................4-10

DISK ERRORS .........................................................................................................................................4-10

Chapter 5
BASIC PRINCIPLES OF OPERATION

Quantum Fireball CR DRIVE MECHANISM .........................................................................................5-1

Base Casting Assembly ....................................................................................................................5-3

DC Motor Assembly .........................................................................................................................5-3

Disk Stack Assemblies .....................................................................................................................5-3

Headstack Assembly ........................................................................................................................5-4

Rotary Positioner Assembly ............................................................................................................5-4

Automatic Actuator Lock ................................................................................................................5-4

Air Filtration .....................................................................................................................................5-5

DRIVE ELECTRONICS ..............................................................................................................................5-5

Integrated µProcessor, Disk Controller and ATA Interface Electronics .....................................5-6

Read/Write ASIC ...............................................................................................................................5-9

PreAmplifier and Write Driver .....................................................................................................5-10

FIRMWARE FEATURES .........................................................................................................................5-11

Disk Caching ...................................................................................................................................5-11

Head and Cylinder Skewing.......................................................................................................... 5-13

Error Detection and Correction .....................................................................................................5-14

Defect Management .......................................................................................................................5-20

iv Quantum Fireball CR 4.3/6.4/.8.4/13.0AT

Chapter 6
ATA BUS INTERFACE AND ATA COMMANDS

INTRODUCTION ....................................................................................................................................... 6-1

SOFTWARE INTERFACE .........................................................................................................................6-1

MECHANICAL DESCRIPTION ................................................................................................................ 6-1

Drive Cable and Connector ............................................................................................................. 6-1

ELECTRICAL INTERFACE ....................................................................................................................... 6-2

ATA Bus Interface ............................................................................................................................ 6-2

Host Interface Timing ...................................................................................................................... 6-9

REGISTER ADDRESS DECODING ........................................................................................................6-20

REGISTER DESCRIPTIONS ................................................................................................................... 6-22

Control Block Registers .................................................................................................................6-22

Command Block Registers ............................................................................................................6-23

COMMAND DESCRIPTIONS................................................................................................................. 6-28

Recalibrate 1xh .............................................................................................................................. 6-28

Read Sectors 20h ............................................................................................................................6-28

Write Sector 30h ............................................................................................................................ 6-28

Read Verify Sectors 40h ................................................................................................................6-29

Seek 7xh ..........................................................................................................................................6-29

Execute Drive Diagnostic 90h ......................................................................................................6-29

Initialize Drive Parameters 91h .................................................................................................... 6-30

Download Microcode .....................................................................................................................6-31

SMART B0h ....................................................................................................................................6-32

Read Multiple C4h ......................................................................................................................... 6-44

Write Multiple C5h ........................................................................................................................6-44

Set Multiple Mode C6h ..................................................................................................................6-45

Read DMA C8h ...............................................................................................................................6-45

Write DMA CAh ............................................................................................................................. 6-45

Read Buffer E4h .............................................................................................................................6-45

Flush Cache .....................................................................................................................................6-45

Write Buffer E8h ............................................................................................................................ 6-46

Power Management Commands ...................................................................................................6-46

Identify Drive – ECh ......................................................................................................................6-49

Set Features EFh .............................................................................................................................6-55

Set Features (Ultra ATA/66) ..........................................................................................................6-55

Read Defect List ..............................................................................................................................6-56

Configuration ................................................................................................................................. 6-58

Host Protected Mode Feature .......................................................................................................6-62

ERROR REPORTING ...............................................................................................................................6-64

Table of Contents

Quantum Fireball CR 4.3/6.4/.8.4/13.0AT v

List of Figures

Figure 3-1 Mechanical Dimensions of

Quantum Fireball CR Hard Disk Drive ................................................. 3-1

Figure 3-2 Drive Packing Assembly .........................................................................3-2

Figure 3-3 Drive Packing Assembly of a 20-Pack Container ............................... 3-3

Figure 3-4 Jumper Locations for the

Quantum Fireball CR Hard Disk Drive ................................................. 3-4

Figure 3-5 Jumper Locations on the Interface Connector .....................................3-4

Figure 3-6 AT Connector and Jumper Location ..................................................... 3-6

Figure 3-7 Mounting Dimensions for the

Quantum Fireball CR Hard Disk Drives ...............................................3-8

Figure 3-8 Mounting Screw Clearance for the

Quantum Fireball CR Hard Disk Drives ...............................................3-9

Figure 3-9 Breather Filter ........................................................................................3-10

Figure 3-10 J1 DC Power and ATA Bus Combination Connector ......................3-11

Figure 3-11 Drive Power Supply and ATA Bus Interface Cables .......................3-14

Figure 3-12 Completing the Drive Installation .....................................................3-15

Figure 5-1 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

Hard Disk Drive Exploded View ...........................................................5-2

Figure 5-2 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

Hard Disk Drive Block Diagram ...........................................................5-5

Figure 5-3 Block Diagram .........................................................................................5-6

Figure 5-4 Read/Write ASIC Block Diagram ........................................................... 5-9

Figure 5-5 Sector Data Field with ECC Check Bytes ............................................5-15

Figure 5-6 Byte Interleaving ...................................................................................5-16

Figure 5-7 Correctable and Uncorrectable Double-Burst Errors ........................5-17

Figure 5-8 Correctable and Uncorrectable Quadruple-Burst Errors ...................5-18

Figure 5-9 Twelve Correctable Random Burst Errors .........................................5-19

Figure 6-1 PIO Interface Timing .............................................................................6-10

Figure 6-2 Multiword DMA Bus Interface Timing ...............................................6-11

Figure 6-3 Initiating a Data In Burst .....................................................................6-14

Figure 6-4 Sustained Data In Burst ........................................................................6-14

Figure 6-5 Host Pausing a Data In Burst ...............................................................6-15

Figure 6-6 Device Terminating a Data In Burst ...................................................6-15

Figure 6-7 Host Terminating a Data In Burst .......................................................6-16

Figure 6-8 Initiating a Data Out Burst 6-...................................................................16

Figure 6-9 Sustained Data Out Burst .....................................................................6-17

Quantum Fireball CR 4.3/6.4/8.4/13.0AT vi

Table of Contents

Figure 6-10 Device Pausing a Data Out Burst ......................................................6-17

Figure 6-11 Host Terminating a Data Out Burst ..................................................6-18

Figure 6-12 Device Terminating a Data out Burst ...............................................6-19

Figure 6-13 Host Interface RESET Timing ............................................................6-19

Quantum Fireball CR 4.3/6.4/8.4/13.0AT vii

List of Tables

Table 3-1 AT Jumper Options.................................................................................................................... 3-5

Table 3-2 J1 Power Connector, Section A............................................................................................ 3-12

Table 3-3 Logical Addressing Format ................................................................................................... 3-17

Table 4-1 Specifications............................................................................................................................. 4-1

Table 4-2 Formatted Capacity................................................................................................................... 4-3

Table 4-3 Timing Specifications ............................................................................................................... 4-4

Table 4-4 Power Reset Limits.................................................................................................................... 4-5

Table 4-5 Typical Power and Current Consumption.............................................................................. 4-6

Table 4-6 Acoustical Characteristics—Sound Pressure........................................................................... 4-7

Table 4-7 Acoustical Characteristics—Sound Power............................................................................... 4-7

Table 4-8 Environmental Specifications.................................................................................................. 4-8

Table 4-9 Shock and Vibration Specifications........................................................................................ 4-9

Table 4-10 Error Rates............................................................................................................................... 4-10

Table 5-1 Cylinder Contents...................................................................................................................... 5-3

Table 5-2 Skews Offsets.......................................................................................................................... 5-13

Table 6-1 Drive Connector Pin Assignments (J1, Section C) ............................................................... 6-3

Table 6-2 Series Termination for Ultra ATA/66...................................................................................... 6-6

Table 6-3 Signal Line Definitions............................................................................................................. 6-7

Table 6-4 Interface Signal Name Assignments....................................................................................... 6-8

Table 6-5 PIO Host Interface Timing........................................................................................................ 6-9

Table 6-6 Multiword DMA Host Interface Timing............................................................................... 6-10

Table 6-7 Ultra DMA Data Transfer Timing Requirements................................................................ 6-11

Table 6-8 Host Interface RESET Timing................................................................................................ 6-19

Table 6-9 I/O Port Functions and Selection Addresses....................................................................... 6-20

Table 6-10 Command Block Register Initial Values.............................................................................. 6-21

Table 6-11 Device Control Register Bits.................................................................................................. 6-22

Table 6-12 Drive Address Register Bits................................................................................................... 6-23

Table 6-13 Error Register Bits .................................................................................................................. 6-24

Table 6-14 Drive Head Register Bits........................................................................................................ 6-25

Table 6-15 Status Register Bits................................................................................................................. 6-26

Table 6-16 Quantum Fireball CR 4.3/6.4/8.4/13.0AT Command Codes and Parameters.................. 6-27

Table 6-17 Diagnostic Codes.................................................................................................................... 6-30

Table 6-18 Device attribute thresholds data structure ......................................................................... 6-36

Table 6-19 Individual threshold data structure ..................................................................................... 6-37

Table 6-20 Device attributes data structure .......................................................................................... 6-39

Table 6-21 Individual attribute data structure ...................................................................................... 6-39

Table 6-22 Valid Count Range................................................................................................................. 6-48

Table 6-23 Identify Drive Parameters...................................................................................................... 6-50

Table 6-24 Transfer/Mode Values............................................................................................................ 6-55

Table 6-25 READ DEFECT LIST LENGTH Command Bytes.................................................................. 6-56

Table 6-26 AT READ DEFECT LIST Command Bytes............................................................................ 6-57

Table 6-27 DEFECT LIST DATA FORMAT............................................................................................... 6-57

Quantum Fireball CR 4.3/6.4/8.4/13.0AT viii

Table of Contents

Table 6-28 DEFECT ENTRY DATA FORMAT........................................................................................... 6-57

Table 6-29 Accessing the READ CONFIGURATION Command ............................................................ 6-58

Table 6-30 Accessing the SET CONFIGURATION Command................................................................ 6-59

Table 6-31 Accessing the SET CONFIGURATION WITHOUT SAVING TO DISK Command.............. 6-60

Table 6-32 Configuration Command Format.......................................................................................... 6-60

Table 6-33 Command Errors..................................................................................................................... 6-64

ix Quantum Fireball CR 4.3/6.4/8.4/13.0AT

This chapter gives an overview of the contents of this manual, including the intended
audience, how the manual is organized, terminology and conventions, and references.

1.1 AUDIENCE DEFINITION

The Quantum Fireball CR™4.3/6.4/8.4/13.0AT Product Manual is intended for several
audiences. These audiences include: the end user, installer, developer, original equipment
manufacturer (OEM), and distributor. The manual provides information about
installation, principles of operation, interface command implementation, and
maintenance.

Chapter 1

ABOUT THIS MANUAL

1.2 MANUAL ORGANIZATION

This manual is organized into the following chapters:

• Chapter 1 – About This Manual

• Chapter 2 – General Description

• Chapter 3 – Installation

• Chapter 4 – Specifications

• Chapter 5 – Basic Principles of Operation

• Chapter 6 – ATA Bus Interface and ATA Commands

1.3 TERMINOLOGY AND CONVENTIONS

In the Glossary at the back of this manual, you can find definitions for many of the terms
used in this manual. In addition, the following abbreviations are used in this manual:

• ASIC application-specific integrated circuit

• ATA advanced technology attachment

• bpi bits per inch

• dB decibels

• dBA decibels, A weighted

• ECC error correcting code

• fci flux changes per inch

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 1-1

About This Manual

• Hz hertz

• KB kilobytes

• LSB least significant bit

• mA milliamperes

• MB megabytes (1 MB = 1,000,000 bytes when referring to disk
storage and 1,048,576 bytes in all other cases)

• Mbit/s megabits per second

• MB/s megabytes per second

• MHz megahertz

• ms milliseconds

• MSB most significant bit

• mV millivolts

• ns nanoseconds

• tpi tracks per inch

• µs microseconds

• V volts

The typographical and naming conventions used in this manual are listed below.
Conventions that are unique to a specific table appear in the notes that follow that table.

Typographical Conventions:

• Names of Bits: Bit names are presented in initial capitals. An example is

the Host Software Reset bit.

• Commands: Interface commands are listed in all capitals. An example is

WRITE LONG.

• Register Names: Registers are given in this manual with initial capitals. An

example is the Alternate Status Register.

• Parameters: Parameters are given as initial capitals when spelled out, and

are given as all capitals when abbreviated. Examples are Prefetch Enable
(PE), and Cache Enable (CE).

• Hexadecimal Notation: The hexadecimal notation is given in 9-point

subscript form. An example is 30

.

H

• Signal Negation: A signal name that is defined as active low is listed with

a minus sign following the signal. An example is RD–.

• Messages: A message that is sent from the drive to the host is listed in all

capitals. An example is ILLEGAL COMMAND.

1-2 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

Naming Conventions:

• Host: In general, the system in which the drive resides is referred to as the
host.

• Computer Voice: This refers to items you type at the computer keyboard.
These items are listed in 10-point, all capitals, Courier font. An example is

FORMAT C:/S.

1.4 REFERENCES

For additional information about the AT interface, refer to:

• IBM Technical Reference Manual #6183355, March 1986.

• ATA Common Access Method Specification, Revision 4.0.

About This Manual

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 1-3

About This Manual

1-4 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

This chapter summarizes the general functions and key features of the Quantum Fireball
CR 4.3/6.4/8.4/13.0AT hard disk drives, as well as the applicable standards and
regulations.

2.1 PRODUCT OVERVIEW

Quantum’s Fireball CR hard disk drives are part of a family of high performance, 1-inch­high hard disk drives manufactured to meet the highest product quality standards.

Chapter 2

GENERAL DESCRIPTION

These hard disk drives use nonremovable, 3 1/2-inch hard disks and are available
with the ATA interface.

The Quantum Fireball CR 4.3/6.4/8.4/13.0AT hard disk drives feature an embedded hard
disk drive controller, and use ATA commands to optimize system performance. Because
the drive manages media defects and error recovery internally, these operations are fully
transparent to the user.

The innovative design of the Quantum Fireball CR hard disk drives incorporate leading
edge technologies such as UltraATA/66, Advanced Cache Management, and Shock
Protection System™ (SPS). These enhanced technologies enable Quantum to produce a
family of high-performance, high-reliability drives.

2.2 KEY FEATURES

The Quantum Fireball CR 4.3/6.4/8.4/13.0AT hard disk drives include the following key
features:

General

• Formatted storage capacity of 4.3 GB (1 disk, 2 heads), 6.4 GB (2 disks, 3 heads),

8.4 GB (2 disks, 4 heads), and 13.0 GB (3 disks, 6 heads)

• Low profile, 1-inch height

• Industry standard 3 1/2-inch form factor

• Emulation of IBM
commands

Performance

®

PC AT

®

task file register, and all AT fixed disk

• Average seek time of 9.5 ms

• Average rotational latency of 5.59 ms

• New Ultra ATA interface with Quantum-patented UltraATA/66 protocol
supporting burst data transfer rates of 66 MB/s.

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 2-1

General Description

• 512 K buffer with 418 K (approximate) Advance Cache Management
(ACM). Look-ahead DisCache feature with continuous prefetch and
WriteCache write-buffering capabilities

• AutoTask Register update, Multi-block AutoRead, and Multi-block
AutoWrite features in a custom ASIC

• Read-on-arrival firmware

• Quadruple-burst ECC, and double burst ECC on-the-fly

• 1:1 interleave on read/write operations

• Support of all standard ATA data transfer modes with PIO mode 4 and
multiword DMA mode 2, and Ultra DMA modes 0, 1, 2, 3, and 4

Reliability

• 625,000 hours mean time between failure (MTBF) in the field

• Automatic retry on read errors

• 288-bit, interleaved Reed-Solomon Error Correcting Code (ECC), with cross
checking correction up to four separate bursts of 32 bits each totalling up
to 128 bits in length

• S.M.A.R.T. 4 system (Self-Monitoring, Analysis and Reporting Technology)

• Patented Airlock

®

automatic shipping lock, magnetic actuator retract, and

dedicated landing zone

• Transparent media defect mapping

• High performance, in-line defective sector skipping

• Adaptive cache segmentation

• Reassignment of defective sectors discovered in the field, without
reformatting

• Shock Protection System

Versatility

• Power saving modes

• Downloadable firmware

• Cable select feature

• Ability to daisy-chain two drives on the interface

2-2 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

2.3 STANDARDS AND REGULATIONS

The Quantum Fireball CR family of hard disk drives satisfy the following standards and
regulations:

• Underwriters Laboratory (U.L.): Standard 1950. Information technology
equipment including business equipment.

• Canadian Standards Association (CSA): Standard C22.2 No. 950-M93.
Information technology equipment including business equipment.

• European Standards (TUV): Standard EN 60 950 and IEC 950. Information
technology equipment including business equipment.

• Federal Communications Commission (FCC): FCC Rules for Radiated and
Conducted Emissions, Part 15, Sub Part J, For Class B Equipment.

• CISPR: CISPR 22 Rules for Radiated and Conducted Emissions, for Class B
Equipment.

• Drives comply with European Union (EU) for application of CE mark.

General Description

2.4 HARDWARE REQUIREMENTS

The Quantum Fireball CR hard disk drives are compatible with the IBM PC AT, and other
computers that are compatible with the IBM PC AT. It connects to the PC either by means
of a third-party IDE-compatible adapter board, or by plugging a cable from the drive
directly into a PC motherboard that supplies an ATA interface.

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 2-3

General Description

2-4 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

This chapter explains how to unpack, configure, mount, and connect the Quantum
Fireball CR 4.3/6.4/8.4/13.0AT hard disk drive prior to operation. It also explains how to
start up and operate the drive.

3.1 SPACE REQUIREMENTS

The Quantum Fireball CR hard disk drives are shipped without a faceplate. Figure 3-1
shows the external dimensions of the Quantum Fireball CR 4.3/6.4/8.4/13.0AT drives.

Chapter 3

INSTALLATION

146.1 mm
(5.75 inches)

Figure 3-1

Mechanical Dimensions of Quantum Fireball CR Hard Disk Drive

25.4 mm
(1.00 inches)

101.6 mm
(4.00 inches)

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 3-1

Installation

3.2 UNPACKING INSTRUCTIONS

CAUTION: The maximum limits for physical shock can be exceeded if the

drive is not handled properly. Special care should be
taken not to bump or drop the drive. It is highly recommended
that Quantum Fireball CR drives are not stacked or placed on any
hard surface after they are unpacked. Such handling could cause
media damage.

1. Open the shipping container and remove the packing assembly that contains
the drive.

2. Remove the drive from the packing assembly.

CAUTION: During shipment and handling, the antistatic electrostatic dis-

charge (ESD) bag prevents electronic component
damage due to electrostatic discharge. To avoid accidental damage
to the drive, do not use a sharp instrument to open the ESD bag
and do not touch PCB components. Save the packing materials for
possible future use.

3. When you are ready to install the drive, remove it from the ESD bag.

Figure 3-2 shows the packing assembly for a single Quantum Fireball CR hard disk
drive. A 20-pack shipping container is available for multiple drive shipments.

Upper Pad

Hard Disk

Drive

Lower Pad

Container

Figure 3-2

3-2 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

Drive Packing Assembly

Polypropylene
Molded Lid

Bottom Tray
Cushioned
Foam Set

Installation

Side Pads

Container

Figure 3-3

Drive Packing Assembly of a Polypropylene 20-Pack Container

Note: The 20-pack container should be shipped in the same way it was

received from Quantum. When individual drives are shipped from
the 20-pack container then it should be appropriately packaged
(not supplied with the 20-pack) to prevent damage.

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 3-3

Installation

3.3 HARDWARE OPTIONS

The configuration of a Quantum Fireball CR 4.3/6.4/8.4/13.0AT hard disk drive depends
on the host system in which it is to be installed. This section describes the hardware
options that you must take into account prior to installation. Figure 3-4 shows the
printed circuit board (PCB) assembly, indicating the jumpers that control some of these
options.

DC Power
Connector

Jumpers

IDE Bus

Interface Header

Figure 3-4

Master

CS

GND

Default
Setting

Back
of
Drive

Front
of
Drive

Jumper Locations for the Quantum Fireball CR Hard Disk Drive

Back of Drive

CS

DS

PK

AT Interface Connector

Jumper Configurations

Slave Cable Select

CS

GNDDSGND

Jumper
shown in
Parking
Position

Reserved
Position

DS

GND

DS with CS
for Slaves
not supporting
DASP

Figure 3-5

Jumper Locations on the Interface Connector

3-4 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

Installation

The configuration of the following four jumpers controls the drive’s mode of operation:

• CS – Cable Select

• DS – Drive Select

• PK– Jumper Parking Position (Slave mode)

The AT PCB has two jumper locations provided for configuration options in a system.
These jumpers are used to configure the drive for master/slave operation in a system.
The default configuration for the drive as shipped from the factory is with a jumper
across the DS location, and open positions in the CS and PK positions.

Table 3-1 defines the operation of the jumpers and their function relative to pin 28 on
the interface. 1 indicates that the specified jumper is installed; 0 indicates that the
jumper is not installed.

Table 3-1

CS DS PK PIN 28 DESCRIPTION

0 0 X X Drive is configured as a slave
0 1 X X Drive is configured as a Master
1 0 X Open Drive is configured as a slave
1 0 X Gnd Drive is configured as a Master
1 0 X Gnd Drive is configured as a Master with slave present
1 1 X X Drive is configured as a Master with an attached slave that

Note: In Table 3-1, a 0 indicates that the jumper is removed, a 1 indicates

that the jumper is installed, and an X indicates that the jumper set­ting does not matter.

AT Jumper Options

does not support DASP

3.3.1 Cable Select (CS) Jumper

When two Quantum Fireball CR 4.3/6.4/8.4/13.0AT hard disk drives are daisy-chained
together, they can be configured as Master or Slave either by the CS or DS jumpers. To
configure the drive as a Master or Slave with the CS feature, the CS jumper is installed
(1).

Once you install the CS jumper, the drive is configured as a Master or Slave by the state
of the Cable Select signal: pin 28 of the ATA bus connector. Please note that pin 28 is
a vendor-specific pin that Quantum is using for a specific purpose. More than one
function is allocated to CS, according to the ATA CAM specification (see reference to
this specification in Chapter 1). If pin 28 is a 0 (grounded), the drive is configured as a
Master. If it is a 1 (high), the drive is configured as a Slave. In order to configure two
drives in a Master/Slave relationship using the CS jumper, you need to use a cable that
provides the proper signal level at pin 28 of the ATA bus connector. This allows two
drives to operate in a Master/Slave relationship according to the drive cable placement.

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 3-5

Installation

3.3.2 Drive Select (DS) Jumper

You can also daisy-chain two drives on the ATA bus interface by using their Drive
Select (DS) jumpers. To use the DS feature, the CS jumper must be removed.

To configure a drive as the Master (Drive 0), a jumper must be installed on the DS pins.
The Quantum Fireball CR 4.3/6.4/8.4/13.0AT hard disk drives are shipped from the

factory as a Master (Drive 0 - DS jumper installed). To configure a drive as a Slave
(Drive 1), the DS jumper must be removed. In this configuration, the spare jumper
removed from the DS position may be stored on the PK jumper pins.

Note: The order in which drives are connected in a daisy chain has no sig-

nificance.

3.3.3 Jumper Parking (PK) Position

The PK position is used as a holding place for the jumper for a slave drive in systems
that do not support Cable Select. The pins used for the parking position are vendor
unique. The drive will bias the parking position pins to detect the presence of this
jumper. When doing so it will maintain a minimum impedance of 4.7 K Ω to the +5 volt
supply and 2.4K Ω to ground.

3.3.4 Master Jumper configuration

In combination with the current DS or CS jumper settings, the Slave Present (SP) jumper
can be implemented if necessary as follows:

• When the drive is configured as a Master
installed, and the Cable Select signal is set to (0), adding an additional
jumper (both jumpers DS and CS now installed) will indicate to the drive
that a Slave drive is present. This Master with Slave Present jumper
configuration should be installed on the Master drive only if the Slave drive
does not use the Drive Active/Slave Present (DASP–) signal to indicate its
presence.

3.3.5 Reserved Position

Do not put a jumper at the reserved position (RSVD).

Pin 1 Pin 1

7.22±0.50
(to pin center)

45.02±0.50

(to pin center)

Pin 1 of AT Connector

29.78±0.50
(to pin center)

(

DS jumper installed or CS jumper

4.55±0.50

Connector Side

C

L

Figure 3-6 AT Connector and Jumper Location

3-6 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

3.4 ATA BUS ADAPTER

There are two ways you can configure a system to allow the Quantum Fireball CR hard
disk drives to communicate over the ATA bus of an IBM or IBM-compatible PC:

1. Connect the drive to a 40-pin ATA bus connector (if available) on the motherboard
of the PC.

2. Install an IDE-compatible adapter board in the PC, and connect the drive to the
adapter board.

3.4.1 40-Pin ATA Bus Connector

Most PC motherboards have a built-in 40-pin ATA bus connector that is compatible
with the 40-pin ATA interface of the Quantum Fireball CR 4.3/6.4/8.4/13.0AT hard disk
drives. If the motherboard has an ATA connector, simply connect a 40-pin ribbon cable
between the drive and the motherboard.

You should also refer to the motherboard instruction manual, and refer to Chapter 6 of
this manual to ensure signal compatibility.

3.4.2 Adapter Board

Installation

If your PC motherboard does not contain a built-in 40-pin ATA bus interface connector,
you must install an ATA bus adapter board and connecting cable to allow the drive to
interface with the motherboard. Quantum does not supply such an adapter board, but
they are available from several third-party vendors.

Please carefully read the instruction manual that comes with your adapter board, as
well as Chapter 6 of this manual to ensure signal compatibility between the adapter
board and the drive. Also, make sure that the adapter board jumper settings are
appropriate.

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 3-7

Installation

3.5 MOUNTING

Drive mounting orientation, clearance, and ventilation requirements are described in
the following subsections.

3.5.1 Orientation

The mounting holes on the Quantum Fireball CR 4.3/6.4/8.4/13.0AT hard disk drives
allow the drive to be mounted in any orientation. Figure 3-6 and Figure 3-7 show the
location of the three mounting holes on each side of the drive. The drive can also be
mounted using the four mounting hole locations on the PCB side of the drive.

Note: It is highly recommended that the drive is hard mounted on to the

chassis of the system being used for general operation, as well as
for test purposes. Failure to hard mount the drive can result in er­roneous errors during testing.

Drives can be mounted in any orientation. Normal position is with
the PCB facing down.

All dimensions are in millimeters. For mounting, #6-32 UNC screws are recommended.

101.60
± 0.25

147.00
Max

± 0.50

6.35 ± 0.25

25.4

± 0.5

28.50

44.45

± 0.25

41.28

± 0.50

3.18 ± 0.25

95.25

± 0.25

101.6

± 0.25

Figure 3-7 Mounting Dimensions for the Quantum Fireball CR Hard Disk Drives

3-8 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

Installation

5.08 mm Maximum
(0.20 Inches)

Drive

Mounting

Screw

Printed­Circuit
Board

Head/Disk

Assembly

6.35 mm Maximum (0.25 Inches)

Printed­Circuit
Board

Figure 3-8 Mounting Screw Clearance for the Quantum Fireball CR Hard Disk Drives

CAUTION: The PCB is very close to the mounting holes. Do not exceed the

specified length for the mounting screws. The specified screw
length allows full use of the mounting hole threads, while avoiding
damaging or placing unwanted stress on the PCB. Figure 3-8
specifies the minimum clearance between the PCB and the screws
in the mounting holes. To avoid stripping the mounting hole
threads, the maximum torque applied to the screws must not
exceed 8 inch-pounds. A maximum screw length of 0.25 inches may
be used.

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 3-9

Installation

Breather Filter Inlet

Figure 3-9 Breather Filter

CAUTION: The Quantum Fireball CR 4.3/6.4/8.4/13.0AT hard disk drives use

a breather filter to eliminate pressure differences that may develop
between the inside and outside of the Head Disk Assembly (HDA).
Blockage of this air inlet could result in pressure building up inside
the HDA and could cause damage to the gasket sealing the HDA
(see Section 5.1.7 for more details).

3-10 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

3.5.2 Clearance

Clearance from the drive to any other surface (except mounting surfaces) must be a
minimum of 1.25 mm (0.05 inches).

3.5.3 Ventilation

The Quantum Fireball CR 4.3/6.4/8.4/13.0AT hard disk drives operate without a cooling
fan, provided the ambient air temperature does not exceed 131°F (55°C) at any point
along the drive form factor envelope.

3.6 COMBINATION CONNECTOR (J1)

J1 is a three-in-one combination connector. The drive’s DC power can be applied to
section A. The ATA bus interface (40-pin) uses section C. The connector is mounted on
the back edge of the printed-circuit board (PCB), as shown in Figure 3-10.

Center

Key Slot

Installation

Pin 1

J1 IDE (40-Pin)/DC (4-Pin)

Combination Connector

4-Pin DC Power

(J1 Section A)

4321

Pin 40

40-Pin IDE

(J1 Section C)

Pin 1

Figure 3-10 J1 DC Power and ATA Bus Combination Connector

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 3-11

Installation

3.6.1 DC Power (J1, Section A)

The recommended mating connectors for the +5 VDC and +12 VDC input power are
listed in Table 3-2.

Table 3-2 J1 Power Connector, Section A

PIN

NUMBER

J1 Section A (4-Pin):

1 +12 VDC 4-Pin Connector:
2 Ground

3 Ground

4 +5 VDC

VOLTAGE

LEVEL

Return for
+12 VDC

Return for +5
VDC

Note: Labels indicate the pin numbers on the connector. Pins 2 and 3 of

section A are the +5 and +12 volt returns and are connected togeth­er on the drive.

MATING CONNECTOR TYPE AND PART NUMBER

(OR EQUIVALENT)

AMP P/N 1-480424-0

Loose piece contacts:

AMP P/N VS 60619-4

Strip contacts:

AMP P/N VS 61117-4

3.6.2 External Drive Activity LED

An external drive activity LED may be connected to the DASP-I/O pin 39 on J1. For
more details, see the pin description in Table 6-1.

3.6.3 ATA Bus Interface Connector (J1, Section C)

On the Quantum Fireball CR 4.3/6.4/8.4/13.0AT hard disk drives, the ATA bus interface
cable connector (J1, section C) is a 40-pin Universal Header, as shown in Figure 3-10.

To prevent the possibility of incorrect installation, the connector has been keyed by
removing Pin 20. This ensures that a connector cannot be installed upside down.

See Chapter 6, “ATA Bus Interface and ATA Commands,” for more detailed information
about the required signals. Refer to Table 6-1 for the pin assignments of the ATA bus
connector (J1, section C).

3-12 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

3.7 FOR SYSTEMS WITH A MOTHERBOARD ATA ADAPTER

You can install the Quantum Fireball CR 4.3/6.4/8.4/13.0AT hard disk drives in an AT­compatible system that contains a 40-pin ATA bus connector on the motherboard.

To connect the drive to the motherboard, use a 40 conductor ribbon cable (80 conductor
ribbon cable if using UltraATA/66 drive) 18 inches in length or shorter. Ensure that pin
1 of the drive is connected to pin 1 of the motherboard connector.

3.8 FOR SYSTEMS WITH AN ATA ADAPTER BOARD

To install the Quantum Fireball CR 4.3/6.4/8.4/13.0AT hard disk drive in an AT­compatible system without a 40-pin ATA bus connector on its motherboard, you need
a third-party IDE-compatible adapter board.

3.8.1 Adapter Board Installation

Carefully read the manual that accompanies your adapter board before installing it.
Make sure that all the jumpers are set properly and that there are no address or signal
conflicts. You must also investigate to see if your AT-compatible system contains a
combination floppy and hard disk controller board. If it does, you must disable the hard
disk drive controller functions on that controller board before proceeding.

Installation

Once you have disabled the hard disk drive controller functions on the floppy/hard
drive controller, install the adapter board. Again, make sure that you have set all jumper
straps on the adapter board to avoid addressing and signal conflicts.

Note: For Sections 3.7 and 3.8, power should be turned off on the com-

puter before installing the drive.

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 3-13

Installation

3.8.1.1 Connecting the Adapter Board and the Drive

Use a 40-pin ribbon cable to connect the drive to the board. See Figure 3-11. To connect
the drive to the board:

1. Insert the 40-pin cable connector into the mating connector of the adapter board.
Make sure that pin 1 of the connector matches with pin 1 on the cable.

2. Insert the other end of the cable into the header on the drive. When inserting
this end of the cable, make sure that pin 1 of the cable connects to pin 1 of the
drive connector.

3. Secure the drive to the system chassis by using the mounting screws, as shown
in Figure 3-12.

Pin 1

ATA-Bus
Interface Cable

Power Supply Cable

ATA-Bus
Interface
Connector

40-Pin Header

(3-Pin or 4-Pin)

Key Slot

DC Power
Connector

Bevel

Figure 3-11 Drive Power Supply and ATA Bus Interface Cables

3-14 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

Installation

Mounting Screws

ATA-Bus Interface Cable

Mounting Bracket

Figure 3-12 Completing the Drive Installation

3.9 TECHNIQUES IN DRIVE CONFIGURATION

3.9.1 The 528-Megabytes Barrier

Older BIOS that only support Int 13 commands for accessing ATA drives through DOS
based operating systems will be limited to use only 1024 cylinders. This will reduce the
effective capacity of the drive to 528 Mbytes.

Whenever possible the Quantum Fireball CR 4.3/6.4/8.4/13.0AT drive should be used
on systems that support LBA translation to ensure the use of the entire capacity of the
disk drive. If that is not possible the following are some techniques that can be used to
overcome this barrier.

• Use a third party software program that translates the hard drive
parameters to an acceptable configuration for MS-DOS.

• Use a hard disk controller that translates the hard drive parameters to an
appropriate setup for both MS-DOS and the computer system’s ROM-BIOS.

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 3-15

Installation

3.9.2 The 8.4-Gigabytes Barrier

Newer BIOS’s allow users to configure disk drives to go beyond the 528 MB barrier by
using several BIOS translation schemes. However, while using these translations the
BIOS using Int 13 functions are limited to 24 bits of addressing which results in another
barrier at the 8.4 GB capacity.

To overcome this barrier a new set of Int 13 extensions are being implemented by most
BIOS manufacturers. The new Int 13 extension allows for four words of addressing
space (64 bits) resulting on 9.4 Terrabytes of accessible space.

Whenever possible the Quantum Fireball CR 4.3/6.4/8.4/13.0AT drive should be used
on systems with BIOS that support Int 13 extensions. If that is not possible the following
are some techniques that can be used to overcome this barrier:

• Use a third party software that supplements the BIOS and adds Int 13
extension support.

• Obtain a BIOS upgrade from the system board manufacturer. Many system
board manufacturers allow their BIOS to be upgraded in the field using
special download utilities. Information on BIOS upgrades can be obtained
on the System Board Customer Service respective web sites on the Internet.

3.9.3 Operating system limitations

Most popular operating systems available today have additional limitations which
affect the use of large capacity drives. However, these limitations can not be corrected
on the BIOS and it is up to the operating system manufacturers to release improved
versions to address these problems.

The most popular operating systems available today, DOS and Win 95, use a File
Allocation Table (FAT) size of 16 bits which will only support partitions up to 2.1 GB.
A newer release of Win 95 called OSR2 with a 32 bit FAT has been released to system
manufacturers only. This new FAT size table will support partitions of up to 2.2
Terrabytes.

3-16 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

3.10 SYSTEM STARTUP AND OPERATION

Once you have installed the Quantum Fireball CR 4.3/6.4/8.4/13.0AT hard disk drive,
and adapter board (if required) in the host system, you are ready to partition and format
the drive for operation. To set up the drive correctly, follow these steps:

1. Power on the system.

2. Run the SETUP program. This is generally on a Diagnostics or Utilities disk, or
within the system’s BIOS. Some system BIOS have an auto-detecting feature
making SETUP unnecessary.

3. Enter the appropriate parameters.

The SETUP program allows you to enter the types of optional hardware installed—such
as the hard disk drive type, the floppy disk drive capacity, and the display adapter type.
The system’s BIOS uses this information to initialize the system when the power is
switched on. For instructions on how to use the SETUP program, refer to the system
manual for your PC.

During the AT system CMOS setup, you must enter the drive type for the Quantum
Fireball CR hard disk drives. The drive supports the translation of its physical drive
geometry parameters such as cylinders, heads, and sectors per track to a logical
addressing mode. The drive can work with different BIOS drive-type tables of the
various host systems.

Installation

You can choose any drive type that does not exceed the capacity of the drive. Table 3-3
gives the logical parameters that provide the maximum capacity on the Quantum
Fireball CR family of hard disk drives.

Table 3-3

LBA Capacity 4.3 GB 6.4 GB 8.6 GB 13.0 GB
CHS Capacity 4,320 MB 6,480 MB 8,640 MB 13,020 MB
Logical Cylinders 14,848 13,328 16,383* 25,228*
Logical Heads 9 15 16 16
Logical Sectors/Track 63 63 63 63
Total Number Logical Sectors 8,418,816 12,594,960 16,514,064 25,429,824

Note: *Capacity may be restricted to 8.4 GB (or less) due to system BIOS lim-

itations. Check with your system manufacturer to determine if your
BIOS supports LBA Mode for hard drives greater than 8.4 GB. Default
logical cylinders is limited to 16,383 as per the ATA-4 specifications.

Logical Addressing Format

QUANTUM FIREBALL CR

4.3 6.4 8.4 13.0

To match the logical specifications of the drive to the drive type of a particular BIOS,
consult the system’s drive-type table. This table specifies the number of cylinders,
heads, and sectors for a particular drive type.

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 3-17

Installation

You must choose a drive type that meets the following requirements:

For the 4.3 AT:

Logical Cylinders x Logical Heads x Logical Sectors/Track x 512 = 4,310,433,792

For the 6.4 AT:

Logical Cylinders x Logical Heads x Logical Sectors/Track x 512 = 6,448,619,520

For the 8.4 AT:

Logical Cylinders x Logical Heads x Logical Sectors/Track x 512 = 8,455,200,768

For the 13.0 AT:

Logical Cylinders x Logical Heads x Logical Sectors/Track x 512 = 13,020,069,888

4. Boot the system using the operating system installation disk—for example,
MS-DOS—then follow the installation instructions in the operating system
manual.

3-18 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

This chapter gives a detailed description of the physical, electrical, and environmental
characteristics of the Quantum Fireball CR hard disk drives.

4.1 SPECIFICATION SUMMARY

Table 4-1 gives a summary of the Quantum Fireball CR hard disk drives.

Table 4-1 Specifications

Chapter 4

SPECIFICATIONS

DESCRIPTION

Formatted Capacity 4,320 MB 6,480 MB 8,640 MB 13,020 MB
Nominal rotational speed (rpm) 5,400 5,400 5,400 5,400
Number of Disks 1223
Number of R/W heads 2346
Data Organization:

Zones per surface 15 15 15 15
Tracks per surface 12,515 12,515 12,515 12,515
Total tracks 25,030 37,545 50,060 75,090

Sectors per track:

Inside zone 250 250 250 250
Outside zone 403 403 403 403
Total User Sectors 8,418,816 12,594,960 16,514,064 25,429,824
Bytes per sector 512 512 512 512
Number of tracks per cylinder 2346

Recording:

Recording technology Multiple

Maximum linear density 267,000 fci 267,000 fci 267,000 fci 267,000 fci

Encoding method 24/25 PRML 24/25 PRML 24/25 PRML 24/25 PRML

Interleave 1:1 1:1 1:1 1:1
Track density 13,000 tpi 13,000 tpi 13,000 tpi 13,000 tpi
Maximum effective areal den-

sity

4.3 A T 6.4 A T 8.4 A T 13.0 AT

Zone

3,465

Mbits/in

QUANTUM FIREBALL CR

Multiple

Zone

2

3,465

Mbits/in

2

Mbits/in

Multiple

Zone

3,465

Multiple

Zone

2

3,465

Mbits/in

2

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 4-1

Specifications

DESCRIPTION

QUANTUM FIREBALL CR

4.3 A T 6.4 A T 8.4 A T 13.0 AT

Performance:

Seek times:

Read-on-arrival 9.5 ms typ.

11.5 ms max.

Track-to-track 1.5 ms

typical

Average write 11.0 ms typ.

13.0 ms max.

Full stroke 18.0 ms typ.

22.0 ms max.

9.5 ms typ.

11.5 ms max.

1.5 ms
typical

11.0 ms typ.

13.0 ms max.

18.0 ms typ.

22.0 ms max.

9.5 ms typ.

11.5 ms max.

1.5 ms
typical

11.0 ms typ.

13.0 ms max.

18.0 ms typ.

22.0 ms max.

9.5 ms typ.

11.5 ms max.

1.5 ms
typical

11.0 ms typ.

13.0 ms max.

18.0 ms typ.

22.0 ms max.

Data transfer Rates:

Disk to Read Once a Revolution

Disk to Read

Instantaneously

1

Read Buffer to ATA Bus
(PIO Mode with IORDY)

Read Buffer to ATA Bus
(Ultra A T A Mode)

1, 2

92.2 Mb/sec
min.

148.6 Mb/sec
max.

121.9 Mb/sec

min.

194.9 Mb/sec
max.

16.7 MB/sec.
max.

66 MB/sec.

max.

92.2 Mb/sec
min.

148.6 Mb/sec
max.

121.9 Mb/sec

min.

194.9 Mb/sec
max.

16.7 MB/sec.
max.

66 MB/sec.

max.

92.2 Mb/sec
min.

148.6 Mb/sec
max.

121.9 Mb/sec

min.

194.9 Mb/sec
max.

16.7 MB/sec.
max.

66 MB/sec.

max.

92.2 Mb/sec
min.

148.6 Mb/sec
max.

121.9 Mb/sec

min.

194.9 Mb/sec
max.

16.7 MB/sec.
max.

66 MB/sec.

max.

Buffer Size 512 KB 512 KB 512 KB 512 KB
Reliability:

Seek error rate

2

Unrecoverable error rate

Error correction method
(with cross check)

Projected MTBF

3

Contact Start/Stop Cycles

2

625,000 hrs 625,000 hrs 625,000 hrs 625,000 hrs

4

50,000 min. 50,000 min. 50,000 min. 50,000 min.

1 in 10

14

1 in 10

288-bit

Reed

Solomon

6

1 in 10

14

1 in 10

288-bit

Reed

Solomon

6

1 in 10

14

1 in 10

288-bit

Reed

Solomon

6

1 in 10

1 in 10

288-bit

Reed

Solomon

(Ambient temperature)

Auto head-park method AirLock® with Magnetic Actuator Bias

6

14

1. Disk to read buffer transfer rate is zone-dependent, instantaneous

2. Refer to Section 4.12, “DISK ERRORS” for details on error rate definitions.

3. CSS specifications assumes a duty cycle of one power off operation for every one
idle spin down.

4-2 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

Specifications

4.2 FORMATTED CAPACITY

At the factory, the Quantum Fireball CR 4.3/6.4/8.4/13.0AT hard disk drives receive a
low-level format that creates the actual tracks and sectors on the drive. Table 4-2 shows
the capacity resulting from this process. Formatting done at the user level, for operation
with DOS, UNIX, or other operating systems, may result in less capacity than the physical
capacity shown in Table 4-2.

Table 4-2 Formatted Capacity

QUANTUM FIREBALL CR

4.3 A T 6.4 A T 8.4 A T 13.0 A T

Formatted Capacity 4,320 MB 6,480 MB 8,640 MB 13,020 MB
Number of 512-byte sectors available 8,418,816 12,594,960 16,514,064 25,429,824

Note: * The AT capacity is artificially limited to a 2.1 GB partition boundary.

4.3 DATA TRANSFER RATES

Data is transferred from the disk to the read buffer at a rate of up to 171 Mb/s in bursts.
Data is transferred from the read buffer to the ATA bus at a rate of up to 16.7 MB/s
using programmed I/O with IORDY, or at a rate of up to 66 MB/s using UltraATA/66.
For more detailed information on interface timing, refer to Chapter 6.

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 4-3

Specifications

4.4 TIMING SPECIFICATIONS

Table 4-3 illustrates the timing specifications of the Quantum Fireball CR hard disk
drives.

Table 4-3 Timing Specifications

PARAMETER

Sequential Cylinder Switch Time
Sequential Head Switch Time

4

Random Average (Read or Seek)
Random Average (Write)

9

TYPICAL

NOMINAL

3

3.0 ms 4.0 ms

1

2.5 ms 3.0 ms

9

9.5 ms 11.5 ms

11.0 ms 13.0 ms

WORST

CASE

2

Full-Stroke Seek 18.0 ms 22.0 ms
Average Rotational Latency 5.59 ms —
Power On

5

to Drive Ready

6

9.0 seconds 12.0 seconds
Standby7 to Interface Ready 9.0 seconds 12.0 seconds
Spindown Time, Standby Command 20.0 seconds 15 seconds
Spindown Time, Power loss 18.0 seconds 30 seconds

1. Nominal conditions are as follows:

•Nominal temperature 77˚F (25˚C)

•Nominal supply voltages (12.0V, 5.0V)

•No applied shock or vibration

2. Worst case conditions are as follows:

•Worst case temperature extremes 32 to 131˚F (5˚C to 55˚C)

•Worst case supply voltages (12.0V ±10%, 5.0 V ±5%)

3. Sequential Cylinder Switch Time is the time from the conclusion of the last sector of
a cylinder to the first logical sector on the next cylinder (no more than 6% of cylinder
switches exceed this time).

4. Sequential Head Switch Time is the time from the last sector of a track to the
beginning of the first logical sector of the next track of the same cylinder (no more
than 6% of head switches exceed this time).

5. Power On is the time from when the supply voltages reach operating range to when
the drive is ready to accept any command.

6. Drive Ready is the condition in which the disks are rotating at the rated speed, and
the drive is able to accept and execute commands requiring disk access without
further delay at power or start up. Error recovery routines may extend the time to as
long as 45 seconds for drive ready.

7. Standby is the condition at which the microprocessor is powered, but not the HDA.
When the host sends the drive a shutdown command, the drive parks the heads away
from the data zone, and spins down to a complete stop.

8. After this time it is safe to move the disk drive

9. Average random seek is defined as the average seek time between random logical
block addresses (LBAs).

8
8

4-4 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

4.5 POWER

The Quantum Fireball CR 4.3/6.4/8.4/13.0AT hard disk drives operate from two supply
voltages:

• +12V ±10%

• +5V ±5%

The allowable ripple and noise is 250 mV peak-to-peak for the +12 Volt supply and 100
mV peak-to-peak for the +5 Volt supply.

4.5.1 Power Sequencing

You may apply the power in any order, or open either the power or power return line
with no loss of data or damage to the disk drive. However, data may be lost in the sector
being written at the time of power loss. The drive can withstand transient voltages of
+10% to –100% from nominal while powering up or down.

4.5.2 Power Reset Limits

When powering up, the drive remains reset until both VHT reset limits in Table 4-4 are
exceeded. When powering down, the drive becomes reset when either supply voltage
drops below the V

LT

Specifications

threshold.

Table 4-4 Power Reset Limits

DC VOL T AGE THRESHOLD HYSTERESIS

VLT = 4.65V maximum,

+5 V

+12 V

4.15V minimum

VHT = 4.72V maximum,

4.25V minimum

VLT = 9.70V maximum,

8.25V minimum

VHT = 10.70V maximum,

8.40V minimum

55 mV (typical)

200 mV (typical)

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 4-5

Specifications

4.5.3 Power Requirements

Table 4-5 lists the voltages and typical average corresponding currents for the various
modes of operation of the Quantum Fireball CR hard disk drives.

Table 4-5 Typical Power and Current Consumption

2

MODE OF

TYPICAL A VERAGE CURRENT

(MA RMS UNLESS OTHERWISE NOTED)

OPERATION

+12 V +5V

MODEL NUMBER 4.3 6.4 8.4 13.0 4.3 6.4 8.4 13.0

1

Startup

(peak) 1703 1670 1670 1682 627 624 624 652

3

Idle
Operating
Maximum Seeking
Standby
Sleep

4

5

6

7

Read/Write On Track

MODE OF

OPERATION

8

192 224 224 280 436 434 434 450
381 407 407 462 442 440 440 456
664 687 687 742 441 439 439 455

38 38 38 38 110 110 110 110
38 38 38 38 110 110 110 110

192 220 220 273 449 444 444 460

TYPICAL A VERAGE PO WER2 (W A TTS)

MODEL NUMBER 4.3 6.4 8.4 13.0

1

Startup
Idle
Operating
Maximum Seeking
Standby
Sleep
Read/Write On Track

(peak) 23.6 23.2 23.2 23.4

3

4

5

6

7

8

4.5 4.9 4.9 5.6

6.8 7.1 7.1 7.8

10.2 10.4 10.4 11.2

1.0 1.0 1.0 1.0

1.0 1.0 1.0 1.0

4.5 4.9 4.9 5.6

1. Current is rms except for startup. Startup current is the typical peak current of the
peaks greater than 10 ms in duration.

2. Power requirements reflect nominal for +12V and +5V power.

4-6 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

Specifications

3. Idle mode is in effect when the drive is not reading, writing, seeking, or executing

any commands. A portion of the R/W circuitry is powered down, the motor is up to
speed and the Drive Ready condition exists.

4. Operating mode is defined as when data is being read from or written to the disk. It

is computed based on 40% seeking, 30% on-track read, 20% idle, and 10% on-track
write.

5. Maximum seeking is defined as continuous random seek operations with minimum

controller delay.

6. Standby mode is defined as when the motor is stopped, the actuator is parked, and

all electronics except the interface control are in low power state. Standby occurs
after a programmable time-out after the last host access. Drive ready and seek
complete status exist. The drive leaves standby upon receipt of a command that
requires disk access or upon receiving a spinup command.

7. Sleep is defined as when the spindle and actuator motors are off and the heads are

latched in the landing zone. Receipt of a reset causes the drive to transition from the
sleep to the standby mode.

8. Read/Write On Track is defined as 50% read operations and 50% write operations on

a single physical track.

4.6 ACOUSTICS

Table 4-6 and Table 4-7 specify the acoustical characteristics of the Quantum Fireball CR

4.3/6.4/8.4/13.0AT hard disk drives.

OPERATING MODE

Idle On Track

Table 4-7 Acoustical Characteristics—Sound Power

OPERATING MODE

Idle On Track 1-3 Disk 3.4 Bels 3.8 Bels

Table 4-6 Acoustical Characteristics—Sound Pressure

MEASURED NOISE

(SOUND PRESSURE)

32 dBA (typical)

35 dBA (maximum)

MEASURED NOISE

(SOUND POWER PER ISO 7779)

TYPICAL MAXIMUM

DISTANCE

39.3 in (1 m)

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 4-7

Specifications

4.7 MECHANICAL

Height: 1.0 in. (25.4 mm)
Width: 4.0 in. (101.6 mm)
Depth: 5.75 in. (146.1 mm)
Weight (Typ): Quantum Fireball CR 4.3AT 1.01 lb (.960 kg)

Quantum Firebal CR 6.4/8.4AT 1.05 lb (.475 kg)
Quantum Fireball CR 13.0AT 1.08 lb (.490 kg)

4.8 ENVIRONMENTAL CONDITIONS

Table 4-8 summarizes the environmental specifications of the Quantum Fireball CR hard
disk drives.

Table 4-8 Environmental Specifications

PARAMETER OPERATING NON-OPERATING

Temperature
(Non-condensing)

Temperature Gradient
(Non-condensing)

Humidity2 (Non-condensing)
Maximum W et Bulb
T emperature

1

5˚ to 55˚C

(41˚ to 131˚F)

24˚C/hr maximum

(75.2˚F/hr)

10% to 85% RH

29˚C (86˚F)

-40˚ to 65˚C

(-40˚ to 149˚F)

48˚C/hr maximum

(118.4˚F/hr)

5% to 95% RH

40˚C (104˚F)

Humidity Gradient 30% / hour 30% / hour
Altitude

3, 4

–200 m to 3,000 m

(–650 to 10,000 ft.)

–200 m to 12, 000 m

(–650 to 40,000 ft.)

Altitude Gradient 1.5 kPa/min 8 kPa/min

1. Maximum operating temperature must not exceed the drive at any point along the
drive form factor envelope. Airflow or other means must be used as needed to meet
this requirement.

2. The humidity range shown is applicable for temperatures whose combination does
not result in condensation in violation of the wet bulb specifications.

3. Altitude is relative to sea level.

4. The specified drive uncorrectable error rate will not be exceeded over these
conditions.

4-8 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

4.9 SHOCK AND VIBRATION

The Quantum Fireball CR 4.3/6.4/8.4/13.0AT hard disk drives can withstand levels of
shock and vibration applied to any of its three mutually perpendicular axes, or principal
base axis, as specified in Table 4-9. A functioning drive can be subjected to specified
operating levels of shock and vibration. When a drive has been subjected to specified
nonoperating levels of shock and vibration, with power to the drive off, there will be no
loss of user data at power on.

When packed in its 1-pack shipping container, the Quantum Fireball CR drives can
withstand a drop from 30 inches onto a concrete surface on any of its surfaces, six edges,
or three corners. The 12-pack shipping container can withstand a drop from 30 inches
onto a concrete surface on any of its surfaces, six edges, or three corners.

Table 4-9 Shock and Vibration Specifications

1

Shock

Translational
1/2 sine wave

11 ms duration
2 ms duration

OPERATING NONOPERATING

20.0 Gs

20.0 Gs

Specifications

70 Gs

200 Gs

Trapezoidal
Rotational

2 ms applied at
actuator pivot point

Vibration

Random Vibration (G2/Hz)

1

0.004 (10 – 300Hz)

0.0006 (300 – 450 Hz)

Sine wave (peak to peak)

1 GP-P 5-400 Hz

1/2 octave per minute sweep

1. The specified drive unrecovered error rate will not be exceeded over these conditions.

4.10 HANDLING the DRIVE

Before handling the Quantum hard disk drive some precautions must to be taken to
ensure that the drive is not damaged. Use both hands while handling the drive and hold
the drive by its edges. Quantum drives are designed to withstand normal handling,
however, hard drives can be damaged by electrostatic discharge (ESD), dropping the
drive, rough handling, and mishandling. Use of a properly grounded wrist strap to the
earth is strongly recommended. Always keep the drive inside its special antistatic bag
until ready to install.

—

80 Gs, 18 in/sec velocity change

— 15,000 rad/sec2

0.05 (10 – 300 Hz)

0.012 (300 – 500 Hz)
2 Gs P-P 5–500 Hz

Note: To avoid causing any damage to the drive do not touch the Printed

Circuit Board (PCB) or any of its components when handling the
drive.

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 4-9

Specifications

4.11 RELIABILITY

Mean Time Between Failures (MTBF): The projected field MTBF is 625,000 hours.

Component Life: 5 years
Preventive Maintenance (PM): Not required
Start/Stop: 50,000 cycles at ambient temperature

The Quantum MTBF numbers represent Bell­Core TR-332 Issue #6, December 1997 MTBF

predictions and represent the minimum MTBF
that Quantum or a customer would expect from
the drive.

(minimum)

Note: CSS specification assumes a duty cycle of one power off operation

for every one idle mode spin downs.

4.12 ELECTROMAGNETIC SUSCEPTIBILITY

.4 Volts/meter over a range of 20Hz to 20 MHz.

4.13 EMITTED VIBRATION

.07 Gs peak.

4-10 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

4.14 DISK ERRORS

ERROR TYPE MAXIMUM NUMBER OF ERRORS

Specifications

Table 4-10 Error Rates

Retry recovered read errors
Multi read recovered errors
Unrecovered data errors
Seek errors

4

3

1. Retry recovered read errors are errors which require retries for data correction. Errors
corrected by ECC on-the-fly are not considered recovered read errors. Read on arrival
is disabled to meet this specification. Errors corrected by the thermal asperity
correction are not considered recovered read errors.

2. Multi read recovered errors are those errors which require the quadruple-burst error
correction algorithm to be applied for data correction. This correction is typically
applied only after the programmed retry count is exhausted.

3. Unrecovered read errors are errors that are not correctable using ECC or retries. The
drive terminates retry reads either when a repeating error pattern occurs, or after the
programmed limit for unsuccessful retries and the application of quadruple-burst
error correction.

4. Seek errors occur when the actuator fails to reach (or remain) over the requested
cylinder and the drive requires the execution of a full recalibration routine to locate
the requested cylinder.

1

2

1 event per 109 bits read
1 event per 1012 bits read
1 event per 1014 bits read
1 error per 106 seeks

Note: Error rates are for worst case temperature and voltage.

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 4-11

Specifications

4-12 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

BASIC PRINCIPLES OF OPERATION

This chapter describes the operation of Quantum Fireball CR 4.3/6.4/8.4/13.0AT hard disk
drives’ functional subsystems. It is intended as a guide to the operation of the drive,
rather than a detailed theory of operation.

5.1 QUANTUM FIREBALL CR DRIVE MECHANISM

This section describes the drive mechanism. Section 5.2 describes the drive electronics.
The Quantum Fireball CR hard disk drives consist of a mechanical assembly and a PCB
as shown in Figure 5-1.

The head/disk assembly (HDA) contains the mechanical subassemblies of the drive, which
are sealed under a metal cover. The HDA consists of the following components:

• Base casting

• DC motor assembly

• Disk stack assembly

• Headstack assembly

• Rotary positioner assembly

• Automatic actuator lock

• Air filter

Chapter 5

The drive is assembled in a Class-100 clean room.

CAUTION:To ensure that the air in the HDA remains free of

contamination, never remove or adjust its cover and
seals. Tampering with the HDA will void your warranty.

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 5-1

Basic Principles of Operation

EMS
Grounding
Washer

Cover

Gasket

Diskstack
Assembly

Lower
Mag Plate
Assembly

Upper
Mag Plate
Assembly

Rotary
Positioner
Assembly

Automatic
Actuator
Lock

Spacer
(placed between
each disk)

DC
Spindle
Motor

Base Casting
Assembly

Printed
Circuit
Board

Figure 5-1 Quantum Fireball CR 4.3/6.4/8.4/13.0AT Hard Disk Drive Exploded View

5-2 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

5.1.1 Base Casting Assembly

A single-piece, e-coated, aluminum-alloy base casting provides a mounting surface for
the drive mechanism and PCB. The base casting also acts as the flange for the DC motor
assembly. To provide a contamination-free environment for the HDA, a gasket provides
a seal between the base casting, and the metal cover that encloses the drive mechanism.

5.1.2 DC Motor Assembly

Integral with the base casting, the DC motor assembly is a fixed-shaft, brushless DC
spindle motor that drives the counter-clockwise rotation of the disks.

5.1.3 Disk Stack Assemblies

The disk stack assembly in the Quantum Fireball CR hard disk drives consist of disks
secured by a disk clamp. The aluminum-alloy disks have a sputtered thin-film magnetic
coating.

A carbon overcoat lubricates the disk surface. This prevents head and media wear due to
head contact with the disk surface during head takeoff and landing. Head contact with
the disk surface occurs only in the landing zone outside of the data area, when the disk
is not rotating at full speed. The landing zone is located at the inner diameter of the disk,
beyond the last cylinder of the data area.

Basic Principles of Operation

Table 5-1 Cylinder Contents

CYLINDER

CONTENTS

System Data 0 20 325 157.4

1

ZONE

15 830 250 121.9
14 830 260 126.7
13 830 285 136.3
12 830 293 142.1
11 830 313 150.7
10 830 325 157.4

9 830 342 162.2
8 830 348 169.0
7 830 358 173.8
6 830 370 179.5
5 830 380 183.4
4 830 389 188.2
3 830 390 189.1
2 830 399 192.0

NUMBER

OF TRACKS

SECTORS

PER TRACK

DATA RATE

1 895 403 194.9

1. For user data, zone 15 is the innermost zone and zone 1 is the outermost zone.

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 5-3

Basic Principles of Operation

5.1.4 Headstack Assembly

The headstack assembly consists of read/write heads, head arms, and a coil joined
together by insertion molding to form a rotor subassembly, bearings, and a flex circuit.
Read/write heads mounted to spring-steel flexures are swage mounted onto the rotary
positioner assembly arms.

The flex circuit exits the HDA between the base casting and the cover. A cover gasket
seals the gap. The flex circuit connects the headstack assembly to the PCB. The flex
circuit contains a read preamplifier/write driver IC.

5.1.5 Rotary Positioner Assembly

The rotary positioner, or rotary voice-coil actuator, is a Quantum-proprietary design that
consists of upper and lower permanent magnet plates, a rotary single-phase coil molded
around the headstack mounting hub, and a bearing shaft. The single bi-polar magnet
consists of two alternating poles and is bonded to the magnet plate. A resilient crash stop
prevents the heads from being driven into the spindle or off the disk surface.

Current from the power amplifier induces a magnetic field in the voice coil. Fluctuations
in the field around the permanent magnet cause the voice coil to move. The movement
of the voice coil positions the heads over the requested cylinder.

5.1.6 Automatic Actuator Lock

To ensure data integrity and prevent damage during shipment, the drive uses a dedicated
landing zone, an actuator magnetic retract, and Quantum’s patented Airlock®. The
Airlock holds the headstack in the landing zone whenever the disks are not rotating. It
consists of an air vane mounted near the perimeter of the disk stack, and a locking arm
that restrains the actuator arm assembly.

When DC power is applied to the motor and the disk stack rotates, the rotation generates
an airflow on the surface of the disk. As the flow of air across the air vane increases with
disk rotation, the locking arm pivots away from the actuator arm, enabling the headstack
to move out of the landing zone. When DC power is removed from the motor, an
electronic return mechanism automatically pulls the actuator into the landing zone,
where the magnetic actuator retract force holds it until the Airlock closes and latches it
in place.

5-4 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

5.1.7 Air Filtration

The Quantum Fireball CR 4.3/6.4/8.4/13.0AT hard disk drives are Winchester-type drives.
The heads fly very close to the media surface. Therefore, it is essential that the air
circulating within the drive be kept free of particles. Quantum assembles the drive in a
Class-100 purified air environment, then seals the drive with a metal cover. When the
drive is in use, the rotation of the disks forces the air inside of the drive through an
internal 0.3 micron filter. The internal HDA cavity pressure equalizes to the external
pressure change by passing air through a 0.3 micron, carbon impregnated breather filter.

5.2 DRIVE ELECTRONICS

Advanced circuit (Very Large Scale Integration) design and the use of miniature surface­mounted devices and proprietary VLSI components enable the drive electronics,
including the ATA bus interface, to reside on a single printed circuit board assembly
(PCBA).

Figure 5-2 contains a simplified block diagram of the Quantum Fireball CR hard disk
drive electronics.

The only electrical component not on the PCBA is the PreAmplifier and Write Driver IC.
It is on the flex circuit (inside of the sealed HDA). Mounting the preamplifier as close as
possible to the read/write heads improves the signal-to-noise ratio. The flex circuit
(including the PreAmplifier and Write Driver IC) provides the electrical connection
between the PCB, the rotary positioner assembly, and read/write heads.

Basic Principles of Operation

HARD DISK

PCB

ASSEMBLY

PREAMP &
WRITE
DRIVER

SERIAL BUS

VOICE

COIL

MOTOR

SPINDLE

MOTOR

RDX RDY

WR DATA

SERIAL BUS

SPINDLE/VCM

POWER ASIC

RD DATA

WR DATA

–RESET

µ CONTROLLER/DISK CONTROLLER

VCM/SPINDLE CONTROL

READ/WRITE

ASIC

SERIAL

RD/WR DATA

BUS

SERIAL BUS

ATA INTERFACE ASIC

–POR

REF
CLK

B ADDR B DATA
(0-7) (0-15)

DRAM

(256K X 16)

–WE

ATA I/O

CONTROL BUS

Figure 5-2 Quantum Fireball CR 4.3/6.4/8.4/13.0AT Hard Disk Drive Block Diagram

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 5-5

Basic Principles of Operation

5.2.1 Integrated µProcessor, Disk Controller and ATA Interface Electronics

The µProcessor, Disk Controller, and ATA Interface electronics are contained in a
proprietary ASIC developed by Quantum, as shown below in Figure 5-3.

ATA Interface

+3.3V

+5V

UATA-66

Interface

Digital Controller

ASIC

+3.3V

SDRAM

Buffer

+8V +5V

Preamp

+3.3V

Read Channel

User

Defined

Logic

Micro Controller

Core

+12V

Regulator

+8V

VCM Motor

Driver

HDA

+5V+3.3V

Regulator

+12V

Figure 5-3 Block Diagram

5-6 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

Actuator

Spindle Motor

The integrated µProcessor, Disk Controller, and ATA Interface Electronics have nine
functional modules (described below):

• µProcessor

• Digital Synchronous Spoke (DSS)

• Error Correction Code (ECC) Control

• Formatter

• Buffer Controller

• Servo Controller, including PWM

• Serial Interface

• ATA Interface Controller

• Motor Controller

5.2.1.1 µProcessor

The µProcessor core provides local processor services to the drive electronics under
program control. The µProcessor manages the resources of the Disk Controller, and ATA
Interface internally. It also manages the Read/Write ASIC (Application Specific Integrated
Circuit), and the Spindle/VCM driver externally.

5.2.1.2 Digital Synchronous Spoke

The DSS decodes servo information written on the drive at the factory to determine the
position of the read/write head. It interfaces with the read/write channel, process timing
and position information, and stores it in registers that are read by the servo firmware.

Basic Principles of Operation

5.2.1.3 Error Correction Code (ECC) Control

The Error Correction Code (ECC) Control block utilizes a Reed-Solomon encoder/decoder
circuit that is used for disk read/write operations. It uses a total of 36 redundancy bytes
organized as 32 ECC (Error Correction Code) bytes with four interleaves, and four cross­check bytes. The ECC uses eight bits per symbol and four interleaves. This allows
quadruple-burst error correction of at least 96, and as many as 128 bits in error.

5.2.1.4 Formatter

The Formatter controls the operation of the read and write channel portions of the ASIC.
To initiate a disk operation, the µProcessor loads a set of commands into the WCS
(writable control store) register. Loading and manipulating the WCS is done through the
µProcessor Interface registers.

The Formatter also directly drives the read and write gates (RG, WG) and Command Mode
Interface of the Read/Write ASIC and the R/W Preamplifier, as well as passing write data
to the Precompensator circuit in the Read/Write ASIC.

5.2.1.5 Buffer Controller

The Buffer Controller supports a 512 Kbyte buffer, which is organized as 256 K x 16 bits.
The 16-bit width implementation provides a 60 MB/s maximum buffer bandwidth. This
increased bandwidth allows the µProcessor to have direct access to the buffer,
eliminating the need for a separate µProcessor RAM IC.

The Buffer Controller supports both drive and host address rollover and reloading, to
allow for buffer segmentation. Drive and host addresses may be separately loaded for
automated read/write functions.

The Buffer Controller operates under the direction of the µProcessor.

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 5-7

Basic Principles of Operation

5.2.1.6 Servo Processor

The Servo Processor in the Read Write Channel ASIC provides servo data recovery and
burst demodulation to extract the actuator position information. This information is
processed in the controller ASIC/microprocessor, and a control signal is output to the
VCM in the Power ASIC. This controls the current in the actuator coil which controls the
position of the actuator.

5.2.1.7 Read/Write Interface

The Read/Write interface allows the integrated µprocessor, disk controller to
communicate with the Read/Write chip.

5.2.1.8 ATA Interface Controller

The ATA Interface Controller portion of the ASIC provides data handling, bus control,
and transfer management services for the ATA interface. Configuration and control of
the interface is accomplished by the µController across the MAD bus. Data transfer
operations are controlled by the Buffer Controller module.

5.2.1.9 Motor Controller

The Motor Controller controls the spindle and voice coil motor (VCM) mechanism on the
drive.

5.2.2 Read/Write ASIC

The Read/Write ASIC integrates an Advanced Partial Response Maximum Likelihood
(PRML) processor, a selectable code rate Encoder-Decoder (ENDEC), and a Servo
Processor with data rates up to 270 MHz (259 Mb/s). Programming is done through a fast
40 MHz serial interface. The controller and data interface through an 8-bit wide data
interface. The Read/Write ASIC is a low power 3.3 Volts, single supply, with selective
power down capabilities.

The Read/Write ASIC comprises 12 main functional modules (described below):

• Pre-Compensator

• Variable Gain Amplifier (VGA)

• Butterworth Filter

• FIR Filter

• Flash A/D Converter

• Viterbi Detector

• ENDEC

• Servo Processor

• Clock Synthesizer

• PLL

• Serial Interface

• TA Detection and Correction

5.2.2.1 Pre-Compensator

The pre-compensator introduces pre-compensation to the write data received from the
sequencer module in the DCIIA. The pre-compensated data is then passed to the R/W Pre­Amplifier and written to the disk. Pre-compensation reduces the write interference from
adjacent write bit.

5-8 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

5.2.2.2 Variable Gain Amplifier (VGA)

Digital and analog controlled AGC function with input attenuator for extended range.

5.2.2.3 Butterworth Filter

Continuous time data filter which can be programmed for each zone rate.

5.2.2.4 FIR (Finite Impulse Response) Filter

Digitally controlled and programmable filter for partial response signal conditioning.

5.2.2.5 Flash A/D Converter

Provides very high speed digitization of the processed read signal.

5.2.2.6 Viterbi Detector

Decodes ADC result into binary bit stream.

5.2.2.7 ENDEC

Provides 16/17 or 24/25 code conversion to NRZ. Includes preamble and sync mark
generation and detection.

5.2.2.8 Servo Processor

Servo processor with servo data recovery and burst demodulation.

Basic Principles of Operation

5.2.2.9 Clock Synthesizer

Provides programmable frequencies for each zone data rate.

5.2.2.10 PLL

Provides digital read clock recovery.

5.2.2.11 Serial Interface

High speed interface for digital control of all internal blocks.

5.2.2.12 TA Detection and Correction

Detects thermal asperities’ defective sectors and enables thermal asperity recoveries.

5.2.3 PreAmplifier and Write Driver

The PreAmplifier and Write Driver provides write driver and read pre-amplifier functions,
and R/W head selection. The write driver receives precompensated write data from the
PreCompensator module in the Read/Write ASIC. The write driver then sends this data to
the heads in the form of a corresponding alternating current. The read pre-amplifier
amplifies the low-amplitude voltages generated by the R/W heads, and transmits them to
the VGA module in the Read/Write ASIC. Head select is determined by the controller. The
preamp also contains internal compensation for thermal asperity induced amplitude
variation.

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 5-9

Basic Principles of Operation

5.3 FIRMWARE FEATURES

This section describes the following firmware features:

• Disk caching

• Head and cylinder skewing

• Error detection and correction

• Defect management

5.3.1 Disk Caching

The Quantum Fireball CR 4.3/6.4/8.4/13.0AT hard disk drives incorporate DisCache, a
418 K (approximate) disk cache, to enhance drive performance. This integrated feature
is user-programmable and can significantly improve system throughput. Read and
write caching can be enabled or disabled by using the Set Configuration command.

5.3.1.1 Adaptive Caching

The cache buffer for the Quantum Fireball CR drives features adaptive segmentation for
more efficient use of the buffer’s RAM. With this feature, the buffer space used for read
and write operations is dynamically allocated. The cache can be flexibly divided into
several segments under program control. Each segment contains one cache entry.

A cache entry consists of the requested read data plus its corresponding prefetch data.
Adaptive segmentation allows the drive to make optimum use of the buffer. The amount
of stored data can be increased.

5.3.1.2 Read Cache

DisCache anticipates host-system requests for data and stores that data for faster access.
When the host requests a particular segment of data, the caching feature uses a prefetch
strategy to “look ahead”, and automatically store the subsequent data from the disk into
high-speed RAM. If the host requests this subsequent data, the RAM is accessed rather
than the disk.

Since typically 50 percent or more of all disk requests are sequential, there is a high
probability that subsequent data requested will be in the cache. This cached data can be
retrieved in microseconds rather than milliseconds. As a result, DisCache can provide
substantial time savings during at least half of all disk requests. In these instances,
DisCache could save most of the disk transaction time by eliminating the seek and
rotational latency delays that dominate the typical disk transaction. For example, in a 1K
data transfer, these delays make up to 90 percent of the elapsed time.

DisCache works by continuing to fill its cache memory with adjacent data after
transferring data requested by the host. Unlike a noncaching controller, Quantum’s disk
controller continues a read operation after the requested data has been transferred to the
host system. This read operation terminates after a programmed amount of subsequent
data has been read into the cache segment.

The cache memory consists of a 418 K (approximate) DRAM buffer allocated to hold the
data, which can be directly accessed by the host by means of the READ and WRITE
commands. The memory functions as a group of segments with rollover points at the end
of cache memory. The unit of data stored is the logical block (that is, a multiple of the
512 byte sector). Therefore, all accesses to the cache memory must be in multiples of the
sector size. All non-read/write commands force emptying of the cache:

5-10 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

5.3.1.3 Write Cache

When a write command is executed with write caching enabled, the drive stores the data
to be written in a DRAM cache buffer, and immediately sends a GOOD STATUS message
to the host before the data is actually written to the disk. The host is then free to move
on to other tasks, such as preparing data for the next data transfer, without having to
wait for the drive to seek to the appropriate track, or rotate to the specified sector.

While the host is preparing data for the next transfer, the drive immediately writes the
cached data to the disk, usually completing the operation in less than 20 ms after issuing
GOOD STATUS. With WriteCache, a single-block random write, for example, requires
only about 3 ms of host time. Without WriteCache, the same operation would occupy the
host for about 20 ms.

WriteCache allows data to be transferred in a continuous flow to the drive, rather than
as individual blocks of data separated by disk access delays. This is achieved by taking
advantage of the ability to write blocks of data sequentially on a disk that is formatted
with a 1:1 interleave. This means that as the last byte of data is transferred out of the
write cache and the head passes over the next sector of the disk, the first byte of the of
the next block of data is ready to be transferred, thus there is no interruption or delay in
the data transfer process.

The WriteCache algorithm fills the cache buffer with new data from the host while
simultaneously transferring data to the disk that the host previously stored in the cache.

Basic Principles of Operation

5.3.1.4 Performance Benefits

In a drive without DisCache, there is a delay during sequential reads because of the
rotational latency, even if the disk actuator already is positioned at the desired cylinder.
DisCache eliminates this rotational latency time (5.59 ms on average) when requested
data resides in the cache.

Moreover, the disk must often service requests from multiple processes in a multitasking
or multiuser environment. In these instances, while each process might request data
sequentially, the disk drive must share time among all these processes. In most disk
drives, the heads must move from one location to another. With DisCache, even if
another process interrupts, the drive continues to access the data sequentially from its
high-speed memory. In handling multiple processes, DisCache achieves its most
impressive performance gains, saving both seek and latency time when desired data
resides in the cache.

The cache can be flexibly divided into several segments under program control. Each
segment contains one cache entry. A cache entry consists of the requested read data plus
its corresponding prefetch data.

The requested read data takes up a certain amount of space in the cache segment. Hence,
the corresponding prefetch data can essentially occupy the rest of the space within the
segment. The other factors determining prefetch size are the maximum and minimum
prefetch. The drive’s prefetch algorithm dynamically controls the actual prefetch value
based on the current demand, with the consideration of overhead to subsequent
commands.

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 5-11

Basic Principles of Operation

5.3.2 Head and Cylinder Skewing

Head and cylinder skewing in the Quantum Fireball CR 4.3/6.4/8.4/13.0AT hard disk
drives minimize latency time and thus increases data throughput.

5.3.2.1 Head Skewing

Head skewing reduces the latency time that results when the drive must switch read/write
heads to access sequential data. A head skew is employed such that the next logical sector
of data to be accessed will be under the read/write head once the head switch is made,
and the data is ready to be accessed. Thus, when sequential data is on the same cylinder
but on a different disk surface, a head switch is needed but not a seek. Since the
sequential head-switch time is well defined on the Quantum Fireball CR drives, the sector
addresses can be optimally positioned across track boundaries to minimize the latency
time during a head switch. See Table 5-2.

5.3.2.2 Cylinder Skewing

Cylinder skewing is also used to minimize the latency time associated with a single­cylinder seek. The next logical sector of data that crosses a cylinder boundary is
positioned on the drive such that after a single-cylinder seek is performed, and when the
drive is ready to continue accessing data, the sector to be accessed is positioned directly
under the read/write head. Therefore, the cylinder skew takes place between the last
sector of data on the last head of a cylinder, and the first sector of data on the first head
of the next cylinder. Since single-cylinder seeks are well defined on the Quantum Fireball
CR drives, the sector addresses can be optimally positioned across cylinder boundaries
to minimize the latency time associated with a single-cylinder seek. See Table 5-2.

5.3.2.3 Skewing with ID-less

In the ID-less environment, the drive’s track and cylinder skewing will be based in unit
of wedges instead of the traditional sectors. The integrated µprocessor, disk controller and
ATA interface contains a “Wedge Skew Register” to assist in the task of skewing, where
the skew offset must now be calculated with every read/write operation. The firmware
will program the skew offset into this register every time the drive goes to a new track.
The integrated µprocessor, disk controller and ATA interface will then add this value to
the wedge number in the ID calculator, effectively relocating the “first” sector of the track
away from the index. For example, if without skew, sector 0 is to be found following
wedge 0, then if the skew register is set to 10, sector 0 will be found following wedge 10.

Since the wedge-to-wedge time is constant over the entire disk, a single set of head and
cylinder skew off-sets will fulfill the requirement for all recording zones.

5.3.2.4 Skew Offsets

Head Skew 2.16 ms 21

Cylinder Skew 2.88 ms 28

Note: Nominal wedge-to-wedge time of 102.88 µs is used. Worst case in-

stantaneous spindle variation (±0.25%) is used while calculating to
provide a safety margin.

Table 5-2 Skews Offsets

SWITCH TIME WEDGE OFFSET

Wedge offsets are rounded to the closest whole number.

5-12 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

5.3.2.5 Runtime Calculation

Since the wedge-to-wedge time is constant over the entire disk, a single set of head and
cylinder skew offsets will fulfill the requirement for all recording zones. The formula used
to compute the wedge skew for a given cylinder and head is:

Wedge skew = [C* ((# of heads – 1) * TS + CS) + H * TS] MOD 108
Where: C = Cylinder number

H = Head number
TS = Head Skew Offset
CS Cylinder Skew Offset
(wedges/track = 108)

5.3.3 Error Detection and Correction

As disk drive areal densities increase, obtaining extremely low error rates requires a new
generation of sophisticated error correction codes. Quantum Fireball CR hard disk drive
series implement 288-bit quadruple-burst Reed-Solomon error correction techniques to
reduce the uncorrectable read block error rate to less than one bit in 1 x 10

When errors occur, an automatic retry, a double-burst, and a more rigorous quadruple­burst correction algorithm enable the correction of any sector with four bursts of four
incorrect bytes each, or up to sixteen multiple random one-byte burst errors. In addition
to these advanced error correction capabilities, the drive uses an additional cross­checking code and algorithm to double check the main ECC correction. This greatly
reduces the probability of a miscorrection.

Basic Principles of Operation

14

bits read.

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 5-13

Basic Principles of Operation

5.3.3.1 Background Information on Error Correction Code and ECC On-the-Fly

A sector on the Quantum Fireball CR 4.3/6.4/8.4/13.0AT drive is comprised of 512 bytes
of user data, followed by four cross-checking (XC) bytes (32 bits), followed by 32 ECC
check bytes (288 bits). The four cross-checking bytes are used to double check the main
ECC correction and reduce the probability of miscorrection. Errors of up to 64 bits within
one sector can be corrected “on-the-fly,” in real time as they occur, allowing a high
degree of data integrity with no impact on the drive’s performance.

The drive does not need to re-read a sector on the next disk revolution or apply ECC for
those errors that are corrected on-the-fly. Errors corrected in this manner are invisible to
the host system.

When errors cannot be corrected on-the-fly, an automatic retry, and a more rigorous
quadruple-burst error correction algorithm enables the correction of any sector with four
bursts of four incorrect bytes each (up to 16 contiguous bytes), or up to 16 multiple
random one-byte burst errors. In addition to this error correction capability, the drive’s
implementation of an additional cross-checking code and algorithm double checks the
main ECC correction, and greatly decreases the likelihood of miscorrection.

The 32 ECC check bytes shown in Figure 5-4 are used to detect and correct errors. The
cross-checking and ECC data is computed and appended to the user data when the sector
is first written.

12345

d 1d 2d 3d 4d 5

512 data bytes 32 ECC bytes

Figure 5-4 Sector Data Field with ECC Check Bytes

512 513 516

d 512 xc 1

xc 2 • • • •• • • • • •

4

cross-check

bytes

518517

ecc 2ecc 1

548

ecc 32

5-14 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

Interleave 1
Interleave 2
Interleave 3

Interleave 4

Basic Principles of Operation

To obtain the ECC check byte values, each byte (including cross-checking and ECC bytes)
within the sector is interleaved into one of four groups, where the first byte is in
interleave 1, the second byte is in interleave 2, the third byte is in interleave 3, the fourth
byte is in interleave 4, the fifth byte is in interleave 1, and so on, as shown in Figure 5-5.

d1

d5

• • • •

d2

d6

d3

d7

d4 d8 d512 xc4 ecc4 ecc8 ecc12 ecc16• • • • ecc20 ecc24

• • • •

• • • •

d509

d510

xc1

d511

xc2

ecc1

xc3

ecc2

ecc5

ecc3

ecc6

ecc9

ecc7

ecc10

ecc11

ecc13

ecc14

ecc17

ecc15

ecc18

ecc19

ecc21

ecc22

ecc23

Figure 5-5 Byte Interleaving

Note: ECC interleaving is not the same as the sector interleaving that is

done on the disk.

Each of the four interleaves is encoded with 8 ECC bytes, resulting in the 32 ECC bytes
at the end of the sector. The four cross checking bytes are derived from all 512 data bytes.
The combination of the interleaving, and the nature of the ECC formulas enable the drive
to know where the error occurs.

Because the ECC check bytes follow the cross checking bytes, errors found within the
cross-checking bytes can be corrected. Due to the power and sophistication of the code,
errors found within the ECC check bytes can also be corrected.

Each time a sector of data is read, the Quantum Fireball CR drives will generate a new
set of ECC check bytes and cross-checking bytes from the user data. These new check
bytes are compared to the ones originally written to the disk. The difference between the
newly computed and original check bytes is reflected in a set of 32 syndromes and three
cross checking syndromes, which correspond to the number of check bytes. If all the ECC
syndrome values equal zero, and cx syndrome value equals 0 or 0FF, the data was read
with no errors, and the sector is transferred to the host system. If any of the syndromes
do not equal zero, an error has occurred. The type of correction the drive applies depends
on the nature and the extent of the error.

High speed on-the-fly error correction saves several milliseconds on each single-, or
double- burst error, because there is no need to wait for a disk revolution to bring the
sector under the head for re-reading.

Correction of Single-, or Double-Burst Errors On-the-Fly

Single-burst errors may have up to four erroneous bytes (32 bits) within a sector,
provided that each of the four bytes occur in a different interleave.

The Quantum Fireball CR drives have the capability to correct double-burst errors on­the-fly as well. Double-burst errors can be simply viewed as two spans of errors within
one sector. More specifically, correctable double-burst errors must have two or fewer
erroneous bytes per interleave.

The drive’s Reed-Solomon ECC corrects double-burst errors up to 64 bits long, (provided
that the error consists of two or fewer bytes residing in each of the interleaves).

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 5-15

Basic Principles of Operation

Double-Burst Error Examples

In the example shown in Figure 5-6 C, the 58-bit error is uncorrectable since it occupies
more than two erroneous bytes per interleave.

The other two 64-bit errors, shown in Figure 5-6 A and B, are correctable because no
more than two error bytes of the entire error reside in any one of the interleaves.

Note: Any 57-bit error burst can be corrected on-the-fly using double-

burst error correction because no more than two bytes can occupy
each interleave.

Byte 1

A

Byte 1

B

Byte 1

C

• • •

• • •

Interleave

3

• • •

CORRECTABLE

Interleave

Interleave1Interleave

4

Interleave1Interleave2Interleave

2

• • •
3

32 bits 32 bits

CORRECTABLE (On-the-Fly)

Interleave2Interleave

• • •

Interleave2Interleave

3

4

Interleave1Interleave2Interleave3Interleave

4

64 bits

UNCORRECTABLE

Interleave2Interleave

3

Interleave

Interleave1Interleave2Interleave3Interleave

4

4

56 bits

1 bit

Figure 5-6 Correctable and Uncorrectable Double-Burst Errors

Byte 526

Interleave

4

Interleave

1

Interleave1Interleave

• • •

Byte 526

• • •

2

1 bit

Byte 526

• • •

5-16 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

Basic Principles of Operation

Correction of Quadruple-Burst Errors

Through sophisticated algorithms, Quantum Fireball CR 4.3/6.4/8.4/13.0AT drives have
the capability to correct quadruple-burst errors, even though the probability of their
occurrence is low. Quadruple-burst errors can be simply viewed as four spans of errors
within one sector. More specifically, correctable quadruple-burst errors must have four
or fewer erroneous bytes per interleave, and will not be corrected on-the-fly.

The drive’s Reed-Solomon ECC corrects quadruple-burst errors up to 128 bits long,
(provided that the error consists of four or fewer bytes residing in each of the interleaves).

If the quadruple-burst correction is successful, the data from the sector can be written to
a spare sector, and the logical address will be mapped to the new physical location.

Quadruple-Burst Error Examples

In the example shown in Figure 5-7 C, the 120-bit error is uncorrectable since it occupies
more than four erroneous bytes per interleave.

The other two 128-bit errors, shown in Figure 5-7 A and B, are correctable because no
more than four error bytes of the entire error reside in any one of the interleaves.

Note: Any 121-bit error burst can be corrected using quadruple-burst er-

ror correction because no more than four bytes can occupy each in­terleave.

Interleave1Interleave2Interleave

A

Interleave1Interleave2Interleave

B

32 bits

Interleave1Interleave2Interleave

C

1 bit

Interleave

4

3

Interleave

4

Interleave

• • •

Interleave

4

3

3

Interleave2Interleave3Interleave

1

CORRECTABLE

Interleave1Interleave2Interleave

32 bits

UNCORRECTABLE

Interleave2Interleave

1

3

3

Interleave

Interleave1Interleave2Interleave3Interleave4Interleave1Interleave2Interleave3Interleave

4

128 bits

Interleave

4

120 bits

4

Interleave

Interleave2Interleave3Interleave4Interleave1Interleave2Interleave3Interleave4Interleave

1

32 bits

Interleave1Interleave2Interleave

• • • • • •

Interleave

3

4

CORRECTABLE

Interleave

Figure 5-7 Correctable and Uncorrectable Quadruple-Burst Errors

4

Interleave1Interleave2Interleave

1 bit

3

32 bits

1

Interleave

4

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 5-17

Basic Principles of Operation

Multiple Random Burst Errors

The drive’s ECC can correct up to 128 bits of multiple random errors, provided that the
incorrect bytes follow the guidelines for correctable quadruple-burst errors. Up to 64 bits
of multiple random errors can be corrected on-the-fly, provided that the incorrect bytes
follow the guidelines for correctable double-burst errors. Up to 64 bits of multiple
random errors can be corrected on-the-fly if two bytes per interleave contains an error.
If more than four bytes in any one interleave are in error, the sector cannot be corrected.
Figure 5-8 shows an example of a correctable random burst error consisting of 16 bytes
(128 bits). This random burst error is correctable because no more than four bytes within
each interleave are in error.

INTERLEAVE 1

1
5
9

•

•

•

85
89
93

•

•

•

INTERLEAVE 2

2
6

10

•

•

•

86
90
94

•

•

•

INTERLEAVE 3

3
7

11

•

•

•

87
91
95

•

•

•

INTERLEAVE 4

4
8

12

•

•

•

88
92
96

•

•

•

505

506
510 511509 512

513 XC 515 XC

•

•

•

BYTE CONTAINING AN ERROR

Figure 5-8 Twelve Correctable Random Burst Errors

5-18 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

514 XC

•

•

•

507

•

•

•

508

516 XC

•

•

•

5.3.3.2 ECC Error Handling

When a data error occurs, the Quantum Fireball CR hard disk drives check to see if the
error is correctable on-the-fly. This process takes about 200 µs. If the error is correctable
on-the-fly, the error is corrected and the data is transferred to the host system.

If the data is not correctable on-the-fly, the sector is re-read in an attempt to read the
data correctly without applying the triple-, or quadruple-burst ECC correction. Before
invoking the complex triple-, or quadruple-burst ECC algorithm, the drive will always try
to recover from an error by attempting to re-read the data correctly. This strategy
prevents invoking correction on non-repeatable errors. Each time a sector in error is re­read a set of ECC syndromes is computed. If all of the ECC syndrome values equal zero,
and xc syndrome value equals to 0 or 0FF, the data was read with no errors, and the
sector is transferred to the host system. If any of the syndrome values do not equal zero,
an error has occurred, the syndrome values are retained, and another re-read is invoked.

Note: Non-repeatable errors are usually related to the signal to noise ratio

of the system. They are not due to media defects.

When the sets of syndromes from two consecutive re-reads are the same, a stable
syndrome has been achieved. This event may be significant depending on whether the
automatic read reallocation or early correction features have been enabled. If the early
correction feature has been enabled and a stable syndrome has been achieved, triple-, or
quadruple-burst ECC correction is applied, and the appropriate message is transferred to
the host system (e.g., corrected data, etc.).

Basic Principles of Operation

Note: These features can be enabled or disabled through the ATA Set

Configuration command. The EEC bit enables early ECC triple-, or
quadruple-burst correction if a stable syndrome has been achieved
before all of the re-reads have been exhausted. The ARR bit enables
the automatic reallocation of defective sectors.

If the automatic read reallocation feature is enabled, the drive, when encountering
triple-, or quadruple-burst errors, will attempt to re-read up to 8 times the retry count
set in the AT Configuration bytes.

Note: The Quantum Fireball CR 4.3/6.4/8.4/13.0AT drives are shipped from the

factory with the automatic read reallocation feature enabled so that any
new defective sectors can be easily and automatically reallocated for the
average AT end user.

5.3.4 Defect Management

The Quantum Fireball CR drives allocate 32 sectors per 65,504 sectors. In the factory, the
media is scanned for defects. If a sector on a cylinder is found to be defective, the address
of the sector is added to the drive’s defect list. Sectors located physically subsequent to
the defective sector are assigned logical block addresses such that a sequential ordering
of logical blocks is maintained. This inline sparing technique is employed in an attempt
to eliminate slow data transfer that would result from a single defective sector on a
cylinder.

If more than 32 sectors are found defective within 65,504 sectors, the above inline
sparing technique is applied to the 32 sectors only. The remaining defective sectors are
replaced with the nearest available pool of spares.

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 5-19

Basic Principles of Operation

Defects that occur in the field are known as grown defects. If such a defective sector is
found in the field, the sector is reallocated according to the same algorithm used at the
factory for those sectors that are found defective after the first 32 spares per pool of
spares; that is, inline sparing is not performed on these grown defects. Instead, the sector
is reallocated to an available spare sector on a nearby available pool of spares.

Sectors are considered to contain grown defects if the quadruple-burst ECC algorithm
must be applied to recover the data. If this algorithm is successful, the corrected data is
stored in the newly allocated sector. If the algorithm is not successful, a pending defect
will be added to the defect list. Any subsequent read to the original logical block will
return an error if the read is not successful. A host command to over-write the location
will result in 4 write/read/verifies of the suspect location. If any of the 4 write/read/
verifies fail, the new data will be written to a spare sector, and the original location will
be added to the permanent defect list. If all 4 write/read/verifies pass, data will be written
to the location, and the pending defect will be removed from the list.

5-20 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

Chapter 6

ATA BUS INTERFACE AND ATA COMMANDS

This chapter describes the interface between Quantum Fireball CR 4.3/6.4/8.4/13.0AT
hard disk drives and the ATA bus. The commands that are issued from the host to control
the drive are listed, as well as the electrical and mechanical characteristics of the
interface.

6.1 INTRODUCTION

Quantum Fireball CR 4.3/6.4/8.4/13.0AT hard disk drives use the standard IBM PC ATA
bus interface, and are compatible with systems that provide an ATA interface connector
on the motherboard. It may also be used with a third-party adapter board in systems that
do not have a built-in ATA adapter. The adapter board plugs into a standard 16-bit
expansion slot in an AT-compatible computer. A cable connects the drive to the adapter
board.

6.2 SOFTWARE INTERFACE

The Quantum Fireball CR drives are controlled by the Basic Input/Output System (BIOS)
program residing in an IBM PC AT, or IBM compatible PC. The BIOS communicates
directly with the drive’s built-in controller. It issues commands to the drive and receives
status information from the drive.

6.3 MECHANICAL DESCRIPTION

6.3.1 Drive Cable and Connector

The hard disk drive connects to the host computer by means of a cable. This cable has a
40-pin connector that plugs into the drive, and a 40-pin connector that plugs into the
host computer. At the host end, the cable plugs into either an adapter board residing in
a host expansion slot, or an on-board ATA adapter.

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 6-1

ATA Bus Interface and ATA Commands

6.4 ELECTRICAL INTERFACE

6.4.1 ATA Bus Interface

A 40-pin ATA interface connector on the motherboard or an adapter board provides an
interface between the drive and a host that uses an IBM PC AT bus. The ATA interface
contains bus drivers and receivers compatible with the standard AT bus. The AT-bus
interface signals D8–D15, INTRQ, and IOCS16– require the ATA adapter board to have an
extended I/O-bus connector.

The ATA interface buffers data and controls signals between the drive and the AT bus of
the host system, and decodes addresses on the host address bus. The Command Block
Registers on the drive accept commands from the host system BIOS.

Note: Some host systems do not read the Status Register after the drive

issues an interrupt. In such cases, the interrupt may not be
acknowledged. To overcome this problem, you may have to
configure a jumper on the motherboard or adapter board to allow
interrupts to be controlled by the drive’s interrupt logic. Read your
motherboard or adapter board manual carefully to find out how to
do this.

6.4.1.1 Electrical Characteristics

All signals are transistor-transistor logic (TTL) compatible—with logic 1 greater than 2.0
volts and less than 5.25 volts; and logic 0 greater than 0.0 volts and less than 0.8 volts.

6.4.1.2 Drive Signals

The drive connector (J1, section C) connects the drive to an adapter board or onboard
ATA adapter in the host computer. J1, section C is a 40-pin shrouded connector with two
rows of 20 pins on 100-mil centers. J1 has been keyed by removing pin 20. The
connecting cable is a 40-conductor (80-conductor for UDMA modes 3 and 4 operation)
flat ribbon cable with a maximum length of 18 inches.

describes the signals on the drive connector (J1, section C). The drive does not use all of
the signals provided by the ATA bus. Table 6-4 shows the relationship between the drive
connector (J1, section C) and the ATA bus.

Note: In , the following conventions apply:

A minus sign follows the name of any signal that is asserted as
active low.
Direction (DIR) is in reference to the drive.
IN indicates input to the drive.
OUT indicates output from the drive.
I/O indicates that the signal is bidirectional.

6-2 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

ATA Bus Interface and ATA Commands

Table 6-1 Drive Connector Pin Assignments (J1, Section C)

SIGNAL NAME DIR PIN DESCRIPTION

Reset RESET– IN 1 Drive reset signal from the host system, inverted on

the adapter board or motherboard.
This signal from the host system will be asserted
beginning with the application of power, and held
asserted until at least 25 µs after voltage levels have
stabilized within tolerance during power on. It will be
negated thereafter unless some event requires that the
device(s) be reset following power on.
ATA devices will not recognize a signal assertion
shorter than 20 ns as a valid reset signal. Devices may
respond to any signal assertion greater than 20 ns,
and will recognize a signal equal to or greater than 25
µs.
The drive has a 10kΩ pull-up resistor on this signal.

Ground Ground — 2 Ground between the host system and the drive.

Data Bus I/O 3–18 An 8/16-bit, bidirectional data bus between the host

and the drive. D0–D7 are used for 8-bit transfers, such

as registers and ECC bytes.
DD0 17 Bit 0
DD1 15 Bit 1
DD2 13 Bit 2
DD3 11 Bit 3
DD4 9 Bit 4
DD5 7 Bit 5
DD6 5 Bit 6
DD7 3 Bit 7
DD8 4 Bit 8
DD9 6 Bit 9

DD10 8 Bit 10
DD11 10 Bit 11
DD12 12 Bit 12
DD13 14 Bit 13
DD14 16 Bit 14
DD15 18 Bit 15

Ground Ground — 19 Ground between the host system and the drive.

Keypin KEYPIN — 20 Pin removed to key the interface connector.

DMA Request DMARQ OUT 21 Asserted by the drive when it is ready to exchange

data with the host. The direction of the data transfer is

determined by DIOW– and DIOR–. DMARQ is used in

conjunction with DMACK–. The drive has a 10kΩ

pull-down resistor on this signal.

Ground Ground — 22 Ground between the host system and the drive.

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 6-3

ATA Bus Interface and ATA Commands

Table 6-1 Drive Connector Pin Assignments (J1, Section C) (Continued)

SIGNAL NAME DIR PIN DESCRIPTION

I/O Write DIOW– IN 23 The rising edge of this write strobe provides a clock

for data transfers from the host data bus (DD0–DD7 or
DD0–DD15) to a register or to the drive’s data port.

Ground Ground — 24 Ground between the host system and the drive.

I/O Read DIOR– IN 25 The rising edge of this read strobe provides a clock for

data transfers from a register or the drive’s data port
to the host data bus (DD0–DD7 or DD0–DD15). The
rising edge of DIOR– latches data at the host.

Ground Ground — 26 Ground between the host system and the drive.

I/O Channel Ready IORDY OUT 27 When the drive is not ready to respond to a data

transfer request, the IORDY signal is asserted active
low to extend the host transfer cycle of any host
register read or write access. When IORDY is
deasserted, it is in a high-impedance state and it is the
host’s responsibility to pull this signal up to a high
level (if necessary).

Cable Select — 28 This is a signal from the host that allows the drive to

be configured as drive 0 when the signal is 0
(grounded), and as drive 1 when the signal is 1 (high).
The drive has a 10kΩ pull-up resistor on this signal.

DMA Acknowledge DACK1– IN 29 Used by the host to respond to the drive’s DMARQ

signal. DMARQ signals that there is more data
available for the host.

Ground Ground — 30 Ground between the host system and the drive.

Interrupt Request INTRQ OUT 31 An interrupt to the host system. Asserted only when

the drive microprocessor has a pending interrupt, the
drive is selected, and the host clears nIEN in the
Device Control Register. When nIEN is a 1 or the drive
is not selected, this output signal is in a high­impedance state, regardless of the presence or absence
of a pending interrupt.

INTRQ is deasserted by an assertion of RESET–, the
setting of SRST in the Device Control Register, or
when the host writes to the Command Register or
reads the Status Register.

When data is being transferred in programmed I/O
(PIO) mode, INTRQ is asserted at the beginning of each
data block transfer. Exception: INTRQ is not asserted
at the beginning of the first data block transfer that
occurs when any of the following commands
executes: FORMAT TRACK, Write Sector, WRITE
BUFFER, or WRITE LONG.

16-Bit I/O IOCS16– OUT 32 An open-collector output signal. Indicates to the host

system that the 16-bit data port has been addressed,
and that the drive is ready to send or receive a 16-bit
word. When transferring data in PIO mode, if IOCS16–
is not asserted, D0–D7 are used for 8-bit transfers; if
IOCS16– is asserted, D0–D15 are used for 16-bit data
transfers.

Drive Address Bus A 3-bit, binary-coded address supplied by the host

when accessing a register or the drive’s data port.

6-4 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

ATA Bus Interface and ATA Commands

Table 6-1 Drive Connector Pin Assignments (J1, Section C) (Continued)

SIGNAL NAME DIR PIN DESCRIPTION

Bit 1 DA1 IN 33
Bit 0 DA0 IN 35
Bit 2 DA2 IN 36

Passed Diagnostics PDIAG– I/O 34 Drive 0 (Master) monitors this Drive 1 (Slave) open-

collector output signal, which indicates the result of a

diagnostics command or reset. The drive has a 10K

pull-up resistor on this signal.

Following the receipt of a power-on reset, software

reset, or RESET– drive 1 negates PDIAG– within 1 ms.

PDIAG– indicates to drive 0 that drive 1 is busy

(BSY=1). Then, drive 1 asserts PDIAG– within 30

seconds, indicating that drive 1 is no longer busy

(BSY=0) and can provide status information.

Following the assertion of PDIAG–, drive 1 is unable

to accept commands until drive 1 is ready (DRDY=1)—

that is, until the reset procedure for drive 1 is

complete.

Following the receipt of a valid EXECUTE DRIVE

DIAGNOSTIC command, drive 1 negates PDIAG–

within 1 ms, indicating to drive 0 that it is busy and

has not yet passed its internal diagnostics. If drive 1 is

present, drive 0 waits for drive 1 to assert PDIAG– for

up to 5 seconds after the receipt of a valid EXECUTE

DRIVE DIAGNOSTIC command. Since PDIAG–

indicates that drive 1 has passed its internal

diagnostics and is ready to provide status, drive 1

clears BSY prior to asserting PDIAG–.

If drive 1 fails to respond during reset initialization,

drive 0 reports its own status after completing its

internal diagnostics. Drive 0 is unable to accept

commands until drive 0 is ready (DRDY=1)—that is,

until the reset procedure for drive 0 is complete.

Chip Select 0 CS1FX– IN 37 Chip-select signal decoded from the host address bus.

Used to select the host-accessible Command Block

Registers.

Chip Select 1 CS3FX– IN 38 Chip select signal decoded from the host address bus.

Used to select the host-accessible Control Block

Registers.

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 6-5

ATA Bus Interface and ATA Commands

Table 6-1

SIGNAL NAME DIR PIN DESCRIPTION

Drive Active/Slave

Present

Ground Ground — 40 Ground between the host system and the drive.

Series termination resistors are required at both the host and the device for operation in
any of the Ultra ATA/66 modes. Table 6-2 describes recommended values for series
termination at the host and the device.

Drive Connector Pin Assignments (J1, Section C) (Continued)

DASP– I/O 39 A time-multiplexed signal that indicates either drive

activity or that drive 1 is present. During power-on
initialization, DASP– is asserted by drive 1 within 400
ms to indicate that drive 1 is present. If drive 1 is not
present, drive 0 asserts DASP– after 450 ms to light
the drive-activity LED.

An open-collector output signal, DASP– is deasserted
following the receipt of a valid command by drive 1
or after the drive is ready, whichever occurs first. Once
DASP– is deasserted, either hard drive can assert
DASP– to light the drive-activity LED. Each drive has
a 10K pull-up resistor on this signal.

If an external drive-activity LED is used to monitor
this signal, an external resistor must be connected in
series between the signal and a +5 volt supply in order
to limit the current to 24 mA maximum.

Table 6-2 Series Termination for Ultra ATA/66

SIGNAL HOST TERMINA TION DEVICE TERMINA TION

DIOR–/HDMARDY–/HSTROBE 33 Ω 82 Ω

DIOW–/STOP 33 Ω 82 Ω

CS0–, CS1– 33 Ω 82 Ω

DA0, DA1, DA2 33 Ω 82 Ω

DMACK– 33 Ω 82 Ω

DD 15 through DD0 33 Ω 33 Ω

DMARQ 82 Ω 33 Ω

INTRQ 82 Ω 33 Ω

IORDY/DDMARDY–/DSTROBE 82 Ω 33 Ω

Note: Only those signals requiring termination are listed in this table. If

a signal is not listed, series termination is not required for operation
in an Ultra ATA/66 mode.

6-6 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

6.4.1.3 Ultra ATA/66 80 Conductor Cable

The use of a 80 conductor cable is suggested in order to successfully meet the new Ultra
ATA/66 mode 3 and 4 faster timing requirements. The 80 conductor cable is used with
the same connector configuration as the standard 40 conductor cable. There is no new
signal and the 40 additional lines are ground paths tied together to all 7 original ground
conductors. Both, the host and the device (drive) may detect the type of cable being used.

Host Based Cable detection (preferred method)

This detection scheme is already defined in the ATA/ATAPI-4 document. To detect the
type of cable being used the host must sample the PDIAG-/CBLID- signal. After device
0/1 handshaking and a command has been sent to device 1 to cause it to release the
PDIAG- signal, the host detects the state of CBLID-.

Host detects CBLID- below Vil = 80 Conductor
Host detects CBLID- above Vih = 40 Conductor

Device Based Cable detection

Following the issuing of an ID command by the host the device will respond by:

• Asserts PDIAG-/CBLID- (drives it low) for 30 ms minimum.

• Releases PDIAG-/CBLID-

• Measures level of PDIAG-/CBLID- 2 to 13 ms after releasing it.

ATA Bus Interface and ATA Commands

The detected electrical level of PDIAG-/CBLID- will be stored in ID word 93 bit 13 (refer
to Table 6-23).

• PDIAG-/CBLID- less than Vil = 0

• PDIAG-/CBLID- greater than Vih = 1

The host can then read ID data and use information in word 93 only if the device supports
Ultra DMA modes higher than 2, otherwise, it shall be ignored.

• 0 = 40 Conductor if both device and host support method

• 1 = 80 Conductor if both device and host support method.

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 6-7

ATA Bus Interface and ATA Commands

6.4.1.4 ATA Bus Signals

See Table 6-4 for the relationship between the drive signals and the ATA bus.

Signal Line Definitions (Ultra ATA/66)

Several existing ATA signal lines are redefined during the Ultra ATA/66 protocol to
provide new functions. These lines change from old to new definitions the moment the
host decides to allow a DMA burst, if the Ultra ATA/66 transfer mode was previously
chosen via Set Features. The drive becomes aware of this change upon assertion of the
–DMACK line. These lines revert back to their original definitions upon the deassertion
of –DMACK at the termination of the DMA burst.

NEW DEFINITION OLD DEFINITION

DMARQ = DMARQ

–DMACK = –DMACK

(These two signals remain unchanged to ensure backward compatibility with

–DMARDY

STROBE

STOP = –DIOW

–CBLID –PDIAG

Table 6-3 Signal Line Definitions

PIO modes)

= IORDY on WRITE commands

= –DIOR on READ commands

= –DIOR on WRITE commands

= IORDY on READ commands

6-8 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

ATA Bus Interface and ATA Commands

Table 6-4 Interface Signal Name Assignments

J1 PIN

NUMBER

DESCRIPTION HOST DIR DEV ACRONYM

28 CABLE SELECT —> CSEL
37 CHIP SELECT 0 —> CS0–
38 CHIP SELECT 1 <—> CS1–
17 DATA BUS BIT 0 <—> DD0
15 DATA BUS BIT 1 <—> DD1
13 DATA BUS BIT 2 <—> DD2
11 DATA BUS BIT 3 <—> DD3

9 DATA BUS BIT 4 <—> DD4
7 DATA BUS BIT 5 <—> DD5
5 DATA BUS BIT 6 <—> DD6
3 DATA BUS BIT 7 <—> DD7
4 DATA BUS BIT 8 <—> DD8
6 DATA BUS BIT 9 <—> DD9

8 DATA BUS BIT 10 <—> DD10
10 DATA BUS BIT 11 <—> DD11
12 DATA BUS BIT 12 <—> DD12
14 DATA BUS BIT 13 <—> DD13
16 DATA BUS BIT 14 <—> DD14
18 DATA BUS BIT 15 <—> DD15
39 DEVICE ACTIVE OR SLAVE

(DEVICE 1) PRESENT

(See Note 1) DASP–

35 DEVICE ADDRESS BIT 0 —> DA0
33 DEVICE ADDRESS BIT 1 —> DA1
36 DEVICE ADDRESS BIT 2 —> DA2
29 DMA ACKNOWLEDGE —> DMACK–
21 DMA REQUEST <— DMARQ
31 INTERRUPT REQUEST <— INTRQ
25 I/O READ

DMA ready on data in bursts (see note 2)

Data strobe on data out bursts (see note 2)

27 I/O READY

DMA ready on data out bursts (see note 2)

Data strobe on data in bursts (see note 2)

—>
—>
—>

<—
<—
<—

HDMARDY–

DDMARDY–

DIOR–

HSTROBE

IORDY

DSTROBE

23 I/O WRITE

STOP (see note 2)

34 PASSED DIAGNOSTCS/CABLE

DETECTION

(See Notes 1 & 5) PDIAG–/

—>
—>

DIOW–

STOP

CBLID–

1 RESET —> RESET
32 I/O CS16 <— IOCS16

Note: 1.See signal descriptions for information on source of these signals.

2.Used during Ultra DMA protocol only.

3.Pins numbered 2, 19, 22, 24, 26, 30, and 40 are ground.

4.Pin number 20 is the Key Pin.

5. CBLID– during device based cable detection on devices supporting
Ultra DMA modes higher than 2.

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 6-9

ATA Bus Interface and ATA Commands

6.4.2 Host Interface Timing

6.4.2.1 Programmed I/O (PIO) Transfer Mode

The PIO host interface timing shown in Table 6-5 is in reference to signals at 0.8 volts
and 2.0 volts. All times are in nanoseconds, unless otherwise noted. Figure 6-1 provides
a timing diagram.

Table 6-5 PIO Host Interface Timing

SYMBOL DESCRIPTION MIN/MAX

t0 Cycle Time min 120 120

t1 Address Valid to DIOW–/DIOR–Setup min 25 25
t2 DIOW–/DIOR– Pulsewidth (8- or 16-bit) min 70 70

t2i DIOW–/DIOR– Negated Pulsewidth min 25 25

t3 DIOW–Data Setup min 20 20
t4 DIOW– Data Hold min 10 10
t5 DIOR– Data Setup min 20 20

t5a DIOR– to Data Valid max — —

t6 DIOR– Data Hold min 5 5

t6z DIOR– Data Tristate max 30 30

t7 Address Valid to IOCS16– Assertion max N/A N/A
t8 Address Valid to IOSC16– Deassertion max N/A N/A
t9 DIOW–/DIOR– to Address Valid Hold min 10 10

tA IORDY Setup Time min 35 35

tB IORDY Pulse Width max 1250 1250
tR

1. ATA Mode 4 timing is listed for reference only.

Read Data Valid to IORDY active

(if IORDY is initially low after tA)

QUANTUM

MODE 4

(local bus)

1

QUANTUM

FIREBALL CR

AT

min 0 0

6-10 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

ATA Bus Interface and ATA Commands

Address

t 7

IOCS16

DIOW­DIOR-

IORDY

Read Data

Write Data

t 1

t A

t 5a

t 2

t B

t R

t 5

t 3

Figure 6-1 PIO Interface Timing

6.4.2.2 Multiword DMA Transfer Mode

The multiword DMA host interface timing shown in Table 6-6 is in reference to signals
at 0.8 volts and 2.0 volts. All times are in nanoseconds, unless otherwise noted. Figure 6­2 provides a timing diagram.

t 0

t 8

t 9

t 2i

t 6z

t 6

t 4

Table 6-6

SYMBOL DESCRIPTION MIN/MAX

Multiword DMA Host Interface Timing

MODE 2

(local bus)

QUANTUM

1

FIREBALL CR

t0 Cycle Time min 120 120

tD DIOR–/DIOW– Pulsewidth min 70 70

tE DIOR– to Data Valid max – –
tF DIOR– Data Hold min 5 5

tFz DIOR– Data Tristate

2

max 20 20
tG DIOW– Data Setup min 20 20
tH DIOW– Data Hold min 10 10

tI DMACK to DIOR–/DIOW– Setup min 0 0

tJ DIOR–/DIOW– to DMACK– Hold min 5 5

tK DIOR–/DIOW– Negated Pulsewidth min 25 25

tL DIOR–/DIOW– to DMARQ Delay max 35 35
tz DMACK– Data Tristate

3

max 25 25

1. ATA Mode 2 timing is listed for reference only.

2. The Quantum Fireball CR 4.3/6.4/8.4/13.0AT drive tristates after each word transferred.

3. Symbol tz only applies on the last tristate at the end of a multiword DMA transfer cycle.

AT

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 6-11

ATA Bus Interface and ATA Commands

DMARQ
DMACK-

t 0

t L

DIOW­DIOR-

Read DD0-15

Write DD0-15

t I

t E t F

t G t H

t Fz

t Kt D

t J

t Z

Figure 6-2 Multiword DMA Bus Interface Timing

Table 6-7 Ultra DMA Data Transfer Timing Requirements

NAME

MODE 0

(ns)

Min Max Min Max Min Max Min Max Min Max

MODE 1

(ns)

MODE 2

(ns)

MODE 3

(ns)

MODE 4

(ns)

COMMENTS

Tcyc 114 75 55 39 25 Cycle time (from STROBE

edge to STROBE edge)

T2cyc 235 156 117 86 57 Two cycle time (from rising

edge to next rising edge or
from falling edge to next
falling edge of STROBE)

Tds 15 10 7 7 5 Data setup time (at receiver)

Tdh55555Data hold time (at receiver)

Tdvs 70 48 34 20 6 Data valid setup time (at

sender) - time from data
bus being valid until
STROBE edge

Tdvh 66666Data valid hold time (at

sender) - time from STROBE
edge until data may go
invalid

Tfs 0 230 0 200 0 170 0 130 0 120 First STROBE - time for

device to send first
STROBE.

Tli 0 150 0 150 0 150 0 100 0 100 Limited interlock time -

time allowed between an
action by one agent (either
host or device) and the
following action by the
other agent

6-12 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

ATA Bus Interface and ATA Commands

NAME

MODE 0

(ns)

Min Max Min Max Min Max Min Max Min Max

MODE 1

(ns)

MODE 2

(ns)

MODE 3

(ns)

MODE 4

(ns)

COMMENTS

Tmli 20 20 20 20 20 Interlock time with

minimum
Tui00000Unlimited interlock time
Taz 10 10 10 10 10 Maximum time allowed for

outputs to release

Tzah 20 20 20 20 20 Minimum delay time
Tzad 00000

required for output drivers

turning on (from released

state)

Tenv 20 70 20 70 20 70 55 55 Envelope time (all control

signal transitions are within

the DMACK envelope by

this much time)

Tsr 50 30 20 NA NA NA NA STROBE to DMARDY-

response time to ensure the

synchronous pause case

(when the receiver is

pausing)

Trfs 75 60 50 60 60 Ready-to-final-STROBE

time (this long after

receiving DMARDY-

negation, no more STROBE

edges may be sent)
Trp 160 125 100 100 100 Ready-to-pause time—time

until a receiver may assume

that the sender has paused

after negation of DMARDY-

Tiordyz 20 20 20 20 20 Pull-up time before

allowing IORDY to be

released

Tziordy 00000Minimum time device shall

wait before driving IORDY

Tack 20 20 20 20 20 Setup and hold times before

assertion and negation of

DMACK-

Tss 50 50 50 50 50 Time from STROBE edge to

STOP assertion (when the

sender is stopping)

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 6-13

ATA Bus Interface and ATA Commands

Notes:

1. The timing parameters Tui and Tli indicate device-to-host or host-to-device
interlocks, that is, one agent (either host or device) is waiting for the other agent to
respond with a signal on the bus before proceeding. Tui is an unlimited interlock,
or one which has no maximum time value. Tli is a limited time-out, or one which
has a defined maximum.

2. All timing parameters are measured at the connector of the device to which the
parameter applies. For example, the sender shall stop toggling STROBE Trfs ns
after the negation of DMARDY-. Both STROBE and DMARDY- timing
measurements are taken at the connector of the sender.

3. All timing measurement switching points (low to high and high to low) are to
be taken at 1.5V.

6-14 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

ATA Bus Interface and ATA Commands

Figures 6-3 through 6-12 define the timings associated with all phases of Ultra DMA
transfers.

Table 6-7 contains the values for the timings for each of the Ultra DMA transfer modes.

DMARQ
(device)

Tui

DMACK-

(host)

Tack

STOP

(host)

Tack

HDMARDY-

(host)

Tziordy

DSTROBE

(device)

DD(15:0)

Taz

Tenv

Tenv

Tzad

Tzad

Tfs

Tfs

Tdvs

Tdvh

Tack

DA0, DA1, DA2,

CS0-, CS1-

Figure 6-3 Initiating a Data In Burst

T2cyc

Tcyc Tcyc

T2cyc

DSTROBE

at device

DD(15:0)

at device

DSTROBE

at host

DD(15:0)

at host

Tdvh

Tdh

Tdvs Tdvs

Tdvh

Tds Tdh Tds

Tdvh

Tdh

Figure 6-4 Sustained Data In Burst

Note: DD(15:0) and DSTROBE signals are shown at both the host and the device

to emphasize that cable settling time as well as cable propagation delay
shall not allow the data signals to be considered stable at the host until well
after they are driven by the device.

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 6-15

ATA Bus Interface and ATA Commands

DMARQ
(device)

DMACK-

(host)

STOP

(host)

HDMARDY

(host)

DSTROBE

(device)

DD(15:0)

(device)

Note: The host knows the burst is fully paused Trp ns after HDMARDY- is negated and

DMARQ
(device)

DMACK-

(host)

STOP

(host)

HDMARDY-

(host)

DSTROBE

(device)

Trp

Tsr

Trfs

Figure 6-5 Host Pausing a Data In Burst

may then assert STOP to terminate the burst. Tsr timing need not be met for an
asynchronous pause.

Tdvs

Tmli

Tack

Tack

Tiordyz

Tdvh

Tss

Tli

Tli

Tli

Tzah

Taz

DD(15:0)

DA0, DA1, DA2,

CS0-, CS1-

Figure 6-6 Device Terminating a Data In Burst

6-16 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

CRC

Tack

DMARQ
(device)

DMACK-

(host)

STOP

(host)

HDMARDY-

(host)

DSTROBE

(device)

DD(15:0)

Trfs

Trp

Tli

Tli

Taz

Tzah

Tmli

Tmli

ATA Bus Interface and ATA Commands

Tdvs

Tack

Tack

Tiordyz

Tdvh

CRC

DA0, DA1, DA2,

CS0-, CS1-

DMARQ
(device)

DMACK-

(host)

STOP
(host)

DDMARDY-

(device)

HSTROBE

(host)

DD(15:0)

(host)

DA0, DA1, DA2,

CS0-, CS1-

Figure 6-7 Host Terminating a Data In Burst

Tui

Tack Tenv

Tziordy Tli

Tack

Tack

Tui

Tdvs

Figure 6-8 Initiating a Data Out Burst

Tack

Tdvh

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 6-17

ATA Bus Interface and ATA Commands

HSTROBE

at host

Tdvh

DD(15:0)

at host

T2cyc

Tcyc Tcyc

Tdvs Tdvs

Tdvh

T2cyc

Tdvh

HSTROBE

at device

DD(15:0)
at device

Note: DD(15:0) and HSTROBE signals are shown at both the device and the host to

DMARQ
(device)

DMACK-

(host)

STOP

(host)

DDMARDY-

(device)

Tdh

Tds T dh

Tds

Tdh

Figure 6-9 Sustained Data Out Burst

emphasize that cable settling time as well as cable propagation delay shall not
allow the data signals to be considered stable at the device until well after they
are driven by the host.

Trp

Tsr

HSTROBE

(host)

DD(15:0)

(host)

Figure 6-10 Device Pausing a Data Out Burst

Note: The device knows the burst is fully paused Trp ns after DDMARDY- is negated

and may then negate DMARQ to terminate the burst. Tsr timing need not be met
for an asynchronous pause.

6-18 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

Trfs

ATA Bus Interface and ATA Commands

,

DMARQ

(device)

DMACK-

(host)

STOP

(host)

DDMARDY-

(device)

HSTROBE

(host)

DD(15:0)

(host)

DA0, DA1, DA2,

CS0-

CS1-

Tss

Tli

Tli

Tli

Tmli

Tack

Tiordyz

Tack

Tdvs

Tdvh

CRC

Tack

Figure 6-11 Host Terminating a Data Out Burst

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 6-19

ATA Bus Interface and ATA Commands

DMARQ

(device)

DMACK-

(host)

TmliTrp

Tmli

STOP
(host)

DDMARDY-

(device)

Trfs

HSTROBE

(host)

DD(15:0)

(host)

DA0, DA1, DA2,

CS0-, CS1-

Figure 6-12 Device Terminating a Data out Burst

6.4.2.3 Host Interface RESET Timing

The host interface RESET timing shown in Table 6-8 is in reference to signals at 0.8 volts
and 2.0 volts. All times are in nanoseconds, unless otherwise noted. Figure 6-13 provides
a timing diagram.

Tli

Tli

Tack

Tiordyz

Tack

Tdvs

Tdvh

CRC

Tack

Table 6-8 Host Interface RESET Timing

SYMBOL DESCRIPTION MINIMUM MAXIMUM

tM

RESET– Pulse width

t MRESET-

300 —

Figure 6-13 Host Interface RESET Timing

6-20 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

6.5 REGISTER ADDRESS DECODING

The host addresses the drive by using programmed I/O. Host address lines A0–A2, chip­select CS1FX– and CS3FX–, and IOR– and IOW– address the disk registers. Host address
lines A3–A9 generate the two chip-select signals, CS1FX– and CS3FX–.

• Chip Select CS1FX– accesses the eight Command Block Registers.

• Chip Select CS3FX– is valid during 8-bit transfers to or from the Alternate
Status Register.

The drive selects the primary or secondary command block addresses by setting Address
bit A7.

Data bus lines 8–15 are valid only when IOCS16– is active and the drive is transferring
data. The drive transfers ECC information only on data bus lines 0–7. Data bus lines 8–
15 are invalid during transfers of ECC information.

I/O to or from the drive occurs over an I/O port that routes input or output data to or
from selected registers, by using the following encoded signals from the host: CS1FX–,
CS3FX–, DA2, DA1, DA0, DIOR–, and DIOW–. The host writes to the Command Block
Registers when transmitting commands to the drive, and to the Control Block Registers
when transmitting control, like a software reset. Table 6-9 lists the selection addresses
for these registers.

ATA Bus Interface and ATA Commands

Table 6-9 I/O Port Functions and Selection Addresses

FUNCTION HOST SIGNALS

CONTROL BLOCK REGISTERS CS1FX– CS3FX– DA2 DA1 DA0

READ (DIOR–) WRITE (DIOW–)

Data Bus High Impedance Not Used N

Data Bus High Impedance Not Used N A

1

NX2XX

3

0XX

Data Bus High Impedance Not Used N A 1 0 X

Alternate Status Device Control N A 1 1 0

Drive Address Not Used N A 1 1 1

COMMAND BLOCK REGISTERS

READ (DIOR–) WRITE (DIOW–)

Data Port Data Port A N 0 0 0

Error Register Features A N 0 0 1

Sector Count Sector Count A N 0 1 0

Sector Number

LBA Bits 0–7
Cylinder Low

LBA Bits 8–15

Cylinder High

LBA Bits 16–23

Drive/Head

4

5

4

5

4

5

4

Sector Number A N 0 1 1

LBA Bits 0–7 A N 0 1 1

Cylinder Low A N 1 0 0

LBA Bits 8–15 A N 1 0 0

Cylinder High A N 1 0 1

LBA Bits 16–23 A N 1 0 1

Drive/Head A N 1 1 0

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 6-21

ATA Bus Interface and ATA Commands

FUNCTION HOST SIGNALS

LBA Bits 24–27

5

LBA Bits 24–27 A N 1 1 0

Status Command A N 1 1 1

Invalid Address Invalid Address A A X X X

1. N = signal deasserted

2. X = signal either asserted or deasserted

3. A = signal asserted

4. Mapping of registers in CHS mode

5. Mapping of registers in LBA mode
After power on or following a reset, the drive initializes the Command Block Registers to

the values shown in Table 6-10.

Table 6-10 Command Block Register Initial Values

REGISTER VALUE

Error Register 01

Sector Count Register 01

Sector Number Register 01

Cylinder Low Register 00

Cylinder High Register 00

Drive/Head Register 00

6-22 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

6.6 REGISTER DESCRIPTIONS

The Quantum Fireball CR 4.3/6.4/8.4/13.0AT hard disk drives emulate the ATA Command
and Control Block Registers. Functional descriptions of these registers are given in the
next two sections.

6.6.1 Control Block Registers

6.6.1.1 Alternate Status Register

The Alternate Status Register contains the same information as the Status Register in the
command block. Reading the Alternate Status Register does not imply the
acknowledgment of an interrupt by the host or clear a pending interrupt. See the
description of the Status Register in section 6.6.2.8 for definitions of bits in this register.

6.6.1.2 Device Control Register

This write-only register contains two control bits, as shown in Table 6-11.

Table 6-11 Device Control Register Bits

BIT MNEMONIC DESCRIPTION

7 Reserved –
6 Reserved –
5 Reserved –
4 Reserved –
3 1 Always 1
2 SRST
1 nIEN
0 0 Always 0

1

2

ATA Bus Interface and ATA Commands

Host software reset bit

Drive interrupt enable bit

1. SRST = Host Software Reset bit. When the host sets this bit,
the drive is reset. When two drives are daisy-chained on the
interface, this bit resets both drives simultaneously.

2. nIEN = Drive Interrupt Enable bit. When nIEN equals 0 or
the host has selected the drive, the drive enables the host
interrupt signal INTRQ through a tristate buffer to the host.
When nIEN equals 1 or the drive is not selected, the host
interrupt signal INTRQ is in a high-impedance state,
regardless of the presence or absence of a pending
interrupt.

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 6-23

ATA Bus Interface and ATA Commands

6.6.1.3 Drive Address Register

The Drive Address Register returns the head-select addresses for the drive currently
selected. Table 6-12 shows the Drive Address bits.

Table 6-12 Drive Address Register Bits

BIT MNEMONIC DESCRIPTION

7 HiZ
6 nWTG
5 nHS3
4 nHS2 –
3 nHS1 –
2 nHS0 Head Address lsb
1 nDS1
0 nDS0 Drive 0 Select bit

1. HiZ = High Impedance bit. When the host
reads the register, this bit will be in a high
impedance state.

2. nWTG = Write Gate bit. When a write
operation to the drive is in progress, nWTG
equals 0.

3. nHS0–nHS3 = Head Address bits. These bits
are equivalent to the one’s complement of the
binary-coded address of the head currently
selected.

4. nDS0–nDS1 = Drive Select bits. When drive 1
is selected, nDS1 equals 0. When drive 0 is
selected, nDS0 equals 0.

1

2

3

4

High Impedance bit

Write Gate bit

Head Address msb

Drive 1 Select bit

6.6.2 Command Block Registers

6.6.2.1 Data Port Register

All data transferred between the device data buffer and the host passes through the Data
Port Register. The host transfers the sector table to this register during execution of the
FORMAT TRACK command.

6.6.2.2 Error Register

The Error Register contains status information about the last command executed by the
drive. The contents of this register are valid only when the Error bit (ERR) in the Status
Register is set to 1. The contents of the Error Register are also valid at power on, and at
the completion of the drive’s internal diagnostics, when the register contains a status
code. When the error bit in the Status Register is set to 1, the host interprets the Error
Register bits as shown in Table 6-13.

6-24 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

ATA Bus Interface and ATA Commands

Table 6-13 Error Register Bits

MNEMONIC BIT DESCRIPTION

#7
#6
#5
#4
#3

ABRT 2 Requested command aborted due to a drive status error, such as Not

Ready or Write Fault, or because the command code is invalid.
#1
#0

6.6.2.3 Sector Count Register

The Sector Count Register defines the number of sectors of data to be transferred across
the host bus for a subsequent command. If the value in this register is 0, the sector count
is 256 sectors. If the Sector Count Register command executes successfully, the value in
this register at command completion is 0. As the drive transfers each sector, it decrements
the Sector Count Register to reflect the number of sectors remaining to be transferred. If
the command’s execution is unsuccessful, this register contains the number of sectors
that must be transferred to complete the original request.

When the drive executes an INITIALIZE DRIVE PARAMETERS or Format Track command,
the value in this register defines the number of sectors per track.

6.6.2.4 Sector Number Register

The Sector Number Register contains the ID number of the first sector to be accessed by
a subsequent command. The sector number is a value between one and the maximum
number of sectors per track. As the drive transfers each sector, it increments the Sector
Number Register. See the command descriptions in section 6.7 for information about the
contents of the Sector Number Register after successful or unsuccessful command
completion.

In LBA mode, this register contains bits 0 to 7. At command completion, the host updates
this register to reflect the current LBA bits 0 to 7.

6.6.2.5 Cylinder Low Register

The Cylinder Low Register contains the eight low-order bits of the starting cylinder
address for any disk access. On multiple sector transfers that cross cylinder boundaries,
the drive updates this register when command execution is complete, to reflect the
current cylinder number. The host loads the least significant bits of the cylinder address
into the Cylinder Low Register.

In LBA mode, this register contains bits 8 to 15. At command completion, the drive
updates this register to reflect the current LBA bits 8 to 15.

6.6.2.6 Cylinder High Register

The Cylinder High Register contains the eight high-order bits of the starting cylinder
address for any disk access. On multiple sector transfers that cross cylinder boundaries,
the drive updates this register at the completion of command execution, to reflect the
current cylinder number. The host loads the most significant bits of the cylinder address
into the Cylinder High Register.

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 6-25

ATA Bus Interface and ATA Commands

In LBA mode, this register contains bits 16 to 23. At command completion, the host
updates this register to reflect the current LBA bits 16 to 23.

6.6.2.7 Drive/Head Register

The Drive/Head Register contains the drive ID number and its head numbers. At command
completion this register is updated by the drive to reflect the current head.

In LBA mode, this register contains bits 24 to 27. At command completion, the drive
updates this register to reflect the current LBA bits 24 to 27.

Table 6-14 shows the Drive/Head Register bits.

MNEMONIC BIT DESCRIPTION

Reserved 7

L6

Reserved 5 Always 1

DRV 4

HS3 3

HS2 2

HS1 1

HS0 0

1. Bits 5–7 define the sector size set in hardware (512 bytes).

2. Bit 6 is the binary encoded Address Mode Select. When bit 6 is set to 0,
addressing is by CHS mode. When bit 6 is set to 1, addressing is by LBA mode.

3. Bit 4 (DRV) contains the binary encoded drive select number. The Master is the
primary drive; the Slave is the secondary drive

4. In CHS mode, bits 3–0 (HS0–HS3) contain the binary encoded address of the
selected head. At command completion, the host updates these bits to reflect
the address of the head currently selected. In LBA mode, bits 3–0 (HS0–HS3)
contain bits 24–27 of the LBA Address. At command completion, the host
updates this register to reflect the current LBA bits 24 to 27.

Table 6-14 Drive Head Register Bits

1

2

Always 1

0 for CHS mode
1 for LBA mode

3

0 indicates the Master drive is selected

1 indicates the Slave drive is selected

4

Most significant Head Address bit in CHS mode

Bit 24 of the LBA Address in LBA mode

Head Address bit for CHS mode

Bit 25 of the LBA Address in LBA mode

Head Address bit for CHS mode

Bit 26 of the LBA Address in LBA mode

Least significant Head Address bit in CHS mode

Bit 27 of the LBA Address in LBA mode

6.6.2.8 Status Register

The Status Register contains information about the status of the drive and the controller.
The drive updates the contents of this register at the completion of each command. When
the Busy bit is set (BSY=1), no other bits in the Command Block Registers are valid. When
the Busy bit is not set (BSY=0), the information in the Status Register and Command
Block Registers is valid.

When an interrupt is pending, the drive considers that the host has acknowledged the
interrupt when it reads the Status Register. Therefore, whenever the host reads this
register, the drive clears any pending interrupt. Table 6-15 defines the Status Register
bits.

6-26 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

ATA Bus Interface and ATA Commands

Table 6-15 Status Register Bits

MNEMONIC BIT DESCRIPTION

BSY 7 Busy bit. Set by the controller logic of the drive whenever the

drive has access to and the host is locked out of the Command
Block Registers.
BSY is set under the following conditions:

• Within 400 ns after the deassertion of RESET- or after SRST is set in
the Device Control Register. Following a reset, BSY will be set for no
longer than 30 seconds.

• Within 400 ns of a host write to the Command Block Registers with a
Read, READ LONG, READ BUFFER, SEEK, RECALIBRATE, INITIALIZE
DRIVE PARAMETERS, Read Verify, Identify Drive, or EXECUTE DRIVE
DIAGNOSTIC command.

• Within 5 µsec after the transfer of 512 bytes of data during the execu­tion of a Write, Format Track, or WRITE BUFFER command, or 512
bytes of data and the appropriate number of ECC bytes during the ex­ecution of a WRITE LONG command.

When BSY=1, the host cannot write to a Command Block Register and
reading any Command Block Register returns the contents of the Status
Register.

DRDY 6 Drive Ready bit. Indicates that the drive is ready to accept a command.

When an error occurs, this bit remains unchanged until the host reads the
Status Register, then again indicates that the drive is ready. At power on, this
bit should be cleared, and should remain cleared until the drive is up to speed

and ready to accept a command.
#5
#4

DRQ 3 Data Request bit. When set, this bit indicates that the drive is ready to trans-

fer a word or byte of data from the host to the data port.

Obsolete 2
Obsolete 1

ERR 0 Error bit. When set, this bit indicates that the previous command resulted in

an error. The other bits in the Status Register and the bits in the Error Register

contain additional information about the cause of the error.

Note: The content of # bit is command dependent.

Bits 2 and 1 are obsolete according to the ATA-4 specification.

6.6.2.9 Command Register

The host sends a command to the drive by means of an 8-bit code written to the
Command Register. As soon as the drive receives the command in its Command Register,
it begins execution of the command. Table 6-16 lists the hexadecimal command codes
and parameters for each executable command. The code F0h is common to all of the
extended commands. Each of these commands is distinguished by a unique subcode. For
a detailed description of each command, see Section 6.7, "COMMAND DESCRIPTIONS,"
found later in this chapter.

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 6-27

ATA Bus Interface and ATA Commands

Table 6-16 Quantum Fireball CR 4.3/6.4/8.4/13.0AT Command Codes and Parameters

COMMAND PARAMETER

NAME CODE

SC

Ex. Sub

Code

SN CY DS HD FR

RECALIBRATE 1Xh V
READ SECTORS 20h VVVVV
WRITE SECTORS 30h VVVVV
READ VERIFY SECTORS 40h VVVVV
SEEK 7Xh VVVV
EXECUTE DRIVE DIAGNOSTIC 90h
INITIALIZE DRIVE PARAMETERS 91h V V V
DOWNLOAD MICROCODE 92h VVVVV
SMART B0h V V
READ MULTIPLE C4h VVVVV
WRITE MULTIPLE C5h VVVVV
SET MULTIPLE MODE C6h V V
READ DMA C8h VVVVV
WRITE DMA CAh VVVVV
STANDBY IMMEDIATE E0h V
IDLE IMMEDIATE E1h V
STANDBY MODE (AUTO POWER-DOWN) E2h V V
IDLE MODE (AUTO POWER-DOWN) E3h V V
READ BUFFER E4h V
CHECK POWER MODE E5h V V
SLEEP MODE E6h V
FLUSH CACHE—optional cmnd. E7h V
WRITE BUFFER E8h V
IDENTIFY DRIVE ECh V
READ DEFECT LIST—extended cmnd. F0h O0h V V V
READ CONFIGURATION—extended cmnd. F0h O1h V V V
SET CONFIGURATION—extended cmnd. F0h FEh/

VVV

FFh
SCAN VERIFY—extended cmnd. F0h FCh V V V
GET SCAN VERIFY STATUS—extended cmnd. F0h FDh V V V
READ NATIVE MAX ADDRESS F8
SET MAX ADDRESS F9 VVVV

Note: The following information applies to Table 6-16:

SC = Sector Count Register
SN = Sector Number Register
CY = Cylinder Low and High Registers
DS = Drive Select bit (Bit 4 of Drive/Head Register)
HD = 4 Head Select Bits (Bits 0–3 of Drive Head Register)
V = Must contain valid information for this command

FR = Features Register

6-28 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

6.7 COMMAND DESCRIPTIONS

The Quantum Fireball CR hard disk drives support all standard ATA drive commands. The
drive decodes, then executes, commands loaded into the Command Block Register. In
applications involving two hard drives, both drives receive all commands. However, only
the selected drive executes commands—with the exception of the EXECUTE DRIVE
DIAGNOSTIC command, as explained below. The procedure for executing a command on
the selected drive is as follows:

1. Wait for the drive to indicate that it is no longer busy (BSY=0).

2. Activate the Interrupt Enable (–IEN) bit.

3. Wait for the drive to set RDY (RDY=1).

4. Load the required parameters into the Command Block Register.

5. Write the command code to the Command Register.

Execution of the command begins as soon as the drive loads the Command Block
Register. The remainder of this section describes the function of each command. The
commands are listed in the same order they appear in Table 6-16.

ATA Bus Interface and ATA Commands

6.7.1 Recalibrate 1xh

The RECALIBRATE command moves the read/write heads from any location on the disk
to cylinder 0. On receiving this command, the drive sets the BSY bit and issues a seek
command to cylinder 0. The drive then waits for the seek operation to complete, updates
status, negates BSY, and generates an interrupt. If the drive cannot seek to cylinder 0, it
posts the message TRACK 0 NOT FOUND.

6.7.2 Read Sectors 20h

The Read Sectors command reads from 1 to 256 sectors, beginning at the specified sector.
As specified in the Command Block Register, a sector count equal to 0 requests 256
sectors. When the drive accepts this command, it sets BSY and begins execution of the
command.

6.7.2.1 Multiple Sector Reads

Multiple sector reads set DRQ. After reading each sector, the drive generates an interrupt
when the sector buffer is full, and the drive is ready for the host to read the data. Once
the host empties the sector buffer, the drive immediately clears DRQ and sets BSY.

If an error occurs during a multiple sector read, the read terminates at the sector in which
the error occurred. The Command Block Register contains the cylinder, head, and sector
numbers of the sector in which the error occurred. The host can then read the Command
Block Register to determine what kind of error has occurred, and in which sector. Whether
the data error is correctable or uncorrectable, the drive loads the data into the sector
buffer.

6.7.3 Write Sector 30h

The WRITE SECTOR command writes from 1 to 256 sectors, beginning at the specified
sector. As specified in the Command Block Register, a sector count equal to 0 requests
256 sectors. When the drive accepts this command, it sets DRQ and waits for the host to
fill the sector buffer with the data to be written to the drive. The drive does not generate
an interrupt to start the first buffer-fill operation. Once the buffer is full, the drive clears
DRQ, sets BSY, and begins execution of the command.

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 6-29

ATA Bus Interface and ATA Commands

6.7.3.1 Multiple Sector Writes

The MULTIPLE SECTOR WRITES command sets DRQ. The drive generates an interrupt
whenever the sector buffer is ready to be filled. When the host fills the sector buffer, the
drive immediately clears DRQ and sets BSY.

If an error occurs during a multiple sector write operation, the write operation terminates
at the sector in which the error occurred. The Command Block Register contains the
cylinder, head, and sector numbers of the sector in which the error occurred. The host can
then read the Command Block Register to determine what kind of error has occurred, and
in which sector.

6.7.4 Read Verify Sectors 40h

The execution of the READ VERIFY SECTORS command is identical to that of the READ
SECTORS command. However, the Read Verify command does not cause the drive to set
DRQ, the drive transfers no data to the host, and the Long bit is invalid. On receiving the
READ VERIFY command, the drive sets BSY. When the drive has verified the requested
sectors, it clears BSY and generates an interrupt. On command completion, the Command
Block Registers contain the cylinder, head, and sector numbers of the last sector verified.

If an error occurs during a multiple sector verify operation, the read operation terminates
at the sector in which the error occurred. The Command Block Registers contain the
cylinder, head, and sector numbers in which the error occurred.

6.7.5 Seek 7xh

The SEEK command causes the actuator to seek the track to which the Cylinder and Drive/
Head registers point. When the drive receives this command in its Command Block
Registers, it performs the following functions:

1. Sets BSY

2. Initiates the seek operation

3. Resets BSY

4. Sets the Drive Seek Complete (DSC) bit in the Status Register

The drive does not wait for the seek to complete before it sends an interrupt. If the BSY
bit is not set in the Status Register, the drive can accept and queue subsequent commands
while performing the seek. If the Cylinder registers contain an illegal cylinder, the drive
sets the ERR bit in the Status Register and the IDNF bit in the Error Register.

6.7.6 Execute Drive Diagnostic 90h

The EXECUTE DRIVE DIAGNOSTIC command performs the internal diagnostic tests
implemented on the drive. Drive 0 sets BSY within 400 ns of receiving of the command.

If Drive 1 is present:

• Both drives execute diagnostics.

• Drive 0 waits up to six seconds for drive 1 to assert PDIAG–.

6-30 Quantum Fireball CR 4.3/6.4/8.4/13.0AT

ATA Bus Interface and ATA Commands

• If drive 1 does not assert PDIAG– to indicate a failure, drive 0 appends 80h
with its own diagnostic status.

• If the host detects a drive 1 diagnostic failure when reading drive 0 status,
it sets the DRV bit, then reads the drive 1 status.

If Drive 1 is not present:

• Drive 0 reports only its own diagnostic results.

• Drive 0 clears BSY and generates an interrupt.

If drive 1 fails diagnostics, drive 0 appends 80h with its own diagnostic status and loads
that code into the Error Register. If drive 1 passes its diagnostics or no drive 1 is present,
drive 0 appends 00h with its own diagnostic status and loads that code into the Error
Register.

The diagnostic code written to the Error Register is a unique 8-bit code. Table 6-17 lists
the diagnostic codes.

Table 6-17 Diagnostic Codes

DIAGNOSTIC

CODE

01h No Error Detected
02h Formatter Device Error
03h Sector Buffer Error
04h ECC Circuitry Error
05h Controlling Microprocessor Error

8Xh Drive 1 Failed

6.7.7 Initialize Drive Parameters 91h

The INITIALIZE DRIVE PARAMETERS command enables the host to set the logical
number of heads and the logical number of sectors per track. On receiving the command,
the drive sets the BSY bit, saves the parameters, clears BSY, and generates an interrupt.

The only two register values used by this command are the Sector Count Register, which
specifies the number of sectors; and the Drive/Head Register, which specifies the number
of heads, minus 1. The DRV bit assigns these values to drive 0 or drive 1, as appropriate.

This command does not check the sector count and head values for validity. If these
values are invalid, the drive will not report an error until another command causes an
illegal access.

DESCRIPTION

Quantum Fireball CR 4.3/6.4/8.4/13.0AT 6-31

ATA Bus Interface and ATA Commands

6.7.8 Download Microcode

COMMAND CODE - 92h
TYPE - Optional
PROTOCOL - PIO data out
INPUTS - The head bits of the device/head register will always be set to zero. The cylinder

high and low registers will be set to zero. The sector number and the sector count are used
together as a 16-bit sector count value. The feature register specifies the subcommand
code.

Register 76543210

Features Subcommand code

Sector Count Sector count (low order)

Sector Number Sector count (high order)

Cylinder Low 00h

Cylinder High 00h

Device/Head 1 1 D 0000

Command 92h

NORMAL OUTPUTS- None. required.
ERROR OUTPUTS- Aborted command if the device does not support this command or did

not accept the microcode data. Aborted error if subcommand code is not a supported
value.

Status Register Error Register

DRDY DF CORR ERR BBK UNC IDNF ABRT TK0NF AMNF

VV V V

PREREQUISITES - DRDY set equal to one.
DESCRIPTION - This command enables the host to alter the device’s microcode. The data

transferred using the DOWNLOAD MICROCODE command is vendor specific.
All transfers will be an integer multiple of the sector size. The size of the data transfer is

determined by the contents of the Sector Number register and the Sector Count register.
The Sector Number register will be used to extend the Sector Count register, to create a
sixteen bit sector count value. The Sector Number register will be the most significant
eight bits and the Sector Count register will be the least significant eight bits. A value of
zero in both the Sector Number register and the Sector Count register will indicate no
data is to transferred. This allows transfer sizes from 0 bytes to 33, 553, 920 bytes in 512
byte increments.

The Features register will be used to determine the effect of the DOWNLOAD MICROCODE
sub command. The values for the Feature Register are:

01h — download is for immediate, temporary use
07h — save downloaded code for immediate and future use.

Either or both values may be supported. All other values are reserved.

6-32 Quantum Fireball CR 4.3/6.4/8.4/13.0AT