Quantum CR43A013, Fireball CR 4.3AT Manual

Quantum.

Quantum

Fireball

CR

4.3/6.4/8.4/12.7 Product

GB

AT

Manual

Preliminary

Quantum~

Quantum

Fireball CR 4.3/6.4/8.4/12.7 GB

Product

Manual

Preliminary

AT

November, 1998

81-119270-01

Quantum reserves

the

right to make changes and improvements to its products, without incurring

obligation to incorporate such changes

or

improvements into units previously sold

or

shipped.

any

You can request Quantum publications from your Quantum Sales Representative

or

order them directly

from Quantum. Publication Number: 81-119270-01

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TUV

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950 certification granted under File No. LR49896

EN

60

950 granted

Rules for Radiated

under

File

under

File

No.

and

Conducted Emissions,

No.

E78016

R 9677196

Part

15, Sub Part J, for Class-B Equipment.

SERVICE CENTERS

Quantum Service Center 715 Sycamore Avenue Milpitas,

California 95035 Phone: (408) 894-4000 Fax: (408) 894-3218 http://www.quantum.com

Quantum Asia-Pacific Pte. Ltd. 50 Tagore Lane #b 1-04 Singapore,

2678

Phone: (65) 450-9333

(65)

Fax:

452-2544

Quantum

Customer Service Group Quantum Ireland Ltd. Finnabair Industrial Park Dundalk County Louth, Ireland

(353)

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PATENTS

These products are covered 4,419,701;

4,538,1934,625,109; 4,639,798; 4,647,769; 4,647,997; 4,661,696; 4,669,004; 4,675,652;

4,703,176; 4,730,321; 4,772,974; 4,783,705; 4,819,153; 4,882,671; 4,920,442; 4,920,434; 4,982,296;

5,005,089; 5,027,241; 5,031,061; 5,084,791; 5,119,254; 5,160,865; 5,170,229; 5,177,771; Other

Foreign

Patents Pending.

by

or

licensed

under

one or more

of

the following

U.S.

Patents:

U.S.

and

<I>

Quantum, the QUantum logo,

U.S.A

and

AutoWrite,

other countries. Capacity for

DisCache, DiskWare, Defect Free Interface, and WriteCache are trademarks

Corporation. All other

This

product

or

document is protected copying, distribution, and decompilation. form by

RESTRICTED

as set forth DFARS

TIUS

IMPLIED, FITNESS

any

means without prior written authorization RIGHTS

in

LEGEND:

subparagraph (c)(I)(ii)

252.227-7013

PUBLICATION

IS

INCLUDING,

FOR A PARTICULAR

and

AIRLOCK

brand

names

of

by

Use, duplication,

of

and

FAR

52.227-19.

PROVIDED" AS IS' BUT

NOT

LIMITED

PURPOSE,

are trademarks

the

extraordinary, Quantum Fireball

trademarks are the property

copyright and distributed under licenses restricting its use,

No

part

of

or

Rights

disclosure

in

the

WITHOUT

TO,

THE

OR

IMPLIED

NON-INFRINGEMENT.

in

U.S.A.

of

Quantum Corporation, registered

of

their manufacturers.

this product

of

Technical Data

WARRANTY

or

document

Quantum and its licensors,

by

the

government is subj ect to restrictions

and

OF

ANY

WARRANTIES

in

CR,

AutoTransfer, AutoRead,

of

Quantum

may

be

reproduced if

any.

the

in

any

Computer Software clause at

KIND,

EITHER

OF

MERCHANTABILITY,

EXPRESS

OR

Table

of

Contents

Chapter 1 ABOUT

THIS

AUDIENCE DEFINITION .......................................................................................................................... 1-1

MANUAL

TERMINOLOGY AND CONVENTIONS ................................................................................................... 1-1

REFERENCES ............................................................................................................................................

MANUAL

ORGANIZATION .................................................................................................................... 1-1

Chapter 2 GENERAL DESCRIPTION

PRODUCT OVERVIEW ............................................................................................................................ 2-1

KEY

FEATURES .......................................................................................................................................

STANDARDS AND REGULATIONS .......................................................................................................

HARDWARE REQillREMENTS ...............................................................................................................

Chapter 3 INSTALLATION

SPACE REQillREMENTS .........................................................................................................................

UNPACKING INSTRUCTIONS .................................................................................................................

HARDWARE OPTIONS ............................................................................................................................

Cable

Select

(CS)

Jumper

Drive

Select

(DS)

Jumper Jumper Master Reserved

ATA BUS ADAPTER ................................................................................................................................

40-Pin Adapter

MOUNTING ...............................................................................................................................................

Orientation

Clearance .........................................................................................................................................

Ventilation

COMBINATION CONNECTOR (J1) .......................................................................................................

DC External ATA Bus

FOR SYSTEMS WITII A MOTHERBOARD ATA ADAPTER ..............................................................

FOR SYSTEMS WITII

Adapter

TECHNIQUES IN DRIVE CONFIGURATION ........................................................................................

Parking

Jumper

ATA

Board

Power

Board

(PK)

configuration

Position

(J 1,

Drive

Interface

.............................................................................................................................

Bus

Connector

..................................................................................................................................

........................................................................................................................................

......................................................................................................................................

Section

Activity

Connector

AN

Installation

................................................................................................................

Position

A) ..............................................................................................................

ATA ADAPTER

........................................................................................................

.........................................................................................................

............................................................................................................

LED

.........................................................................................................

(J 1, Section

...........................................................................................................

C)

BOARD

.............................................................................

...........................................................................

1-3

2-1 2-3 2-3

3-1 3-2 3-4 3-5

3-6 3-6 3-6 3-6 3-7

3-7 3-7

3-8

3-8 3-11 3-11 3-11

3-12 3-12 3-12 3-13

3-13 3-13

3-15

Quantum

Fireball

CR

4.3/6.4/.8.4/12.7AT iii

Table

of

Contents

The 528-Megabytes Barrier ...........................................................................................................

The 8.4-Gigabytes Barrier .............................................................................................................

Operating system limitations .............................................................................................

SYSTEM

STARTIJP

Chapter 4

SPECIFICATIONS

SPECIFICATION FORMA1TED DATA

TRANSFER

TIMING

POWER

Power Sequencing ............................................................................................................................

Power Reset Limits ...........................................................................................................................

Power Requirements ..............................•..........................................................................•..............

ACOUSTICS

MECHANICAL ENVIRONMENTAL SHOCK HANDliNG the

RELIABILITY

ELECTROMAGNETIC EMI1TED DISK

ERRORS

CAPACITY

SPECIFICATIONS

...................................................................................................................................................... 4-5

............................................................................................................................................... 4-7

AND

VIBRATION

...........................•............................•...............•.......................•...•...•...••••.•.........•..••••......... 4-10

VIBRATION

.........................................................................................................................................

3-15 3-16 3-16

AND

OPERATION

SUMMARY

RATES

........................................................................................................................................... 4-8

CONDmONS

DRIVE

SUSCEPTIBILITY

................................................................................................................... 4-1

............................................................................•...................•........................

....................................................................................................................... 4-3

.......................................................................................................................

........................................................................................................................

............................................................................................................................

................................................................................................................•...........

............ ,

...........................................................................................................

...................................................................................•...........

...

, ...............................................................................

3-17

4-3

4-4

4-5 4-5 4-6

4-8 4-9 4-9

4-10 4-10 4-10

Chapter 5

BASIC PRINCIPLES OF OPERATION

Quantum Fireball

Base

Casting Assembly .................................................................................................................... 5-3

DC

Motor Assembly ......................................................................................................................... 5-3

Disk

Stack Assemblies ..................................................................................................................... 5-3

Headstack Assembly ....................................................•...................................................................

Rotary Positioner Assembly ............................................................................................................

Automatic Actuator

Air Filtration ..................................................................................................................................... 5-5

DRIVE

ELECTRONICS

Integrated pProcessor, Disk Controller Read/Write

PreAmplifier and Write Driver ..................................................................................................... 5-10

FIRMWARE

Caching ................................................................................................................................... 5-11

Disk Head and Error Detection and

Defect Management ............................................................................ , .......................................... 5-20

CR

DRIVE

ASIC

...........................................................•................................................................... 5-9

FEATURES

Cylinder Skewing .......................................................................................................... 5-13

MECHANISM

Lock

............................................•...................................................................

......................................................................................................•......................•

...............•.................•.....................•..............•......•....•.•..•.......•.•.•..................... 5-11

Correction .....................................................................................................

......................................................................................... 5-1

5-4

5-5

and

ATA

Interface Electronics .....................................

5-6

5-14

iv Quantum Fireball CR 4.3/6.4/.8.4112.7AT

Chapter 6

ATA BUS INTERFACE AND ATA COMMANDS

INTRODUCTION

SOFTWARE

MECHANICAL

Drive

ELECTRICAL

ATA Bus Interface ............................................................................................................................

Host Interface Timing ......................................................................................................................

REGISTER REGISTER

Control Block Registers .................................................................................................................

Command Block Registers ............................................................................................................ 6-23

COMMAND

Recalibrate

Read Sectors 20h ............................................................................................................................

Write Sector

Read VerifY Sectors 40h ................................................................................................................

Seek

7xh

Execute Drive Diagnostic 90h ......................................................................................................

Initialize Drive Parameters 91h ....................................................................................................

Download Microcode ..................................................................................................................... 6-31

SMART

Read Multiple C4h .........................................................................................................................

Write Multiple C5h ........................................................................................................................

Set Multiple Mode C6h ..................................................................................................................

Read DMA

Write DMA CAb .............................................................................................................................

Read Buffer E4h .............................................................................................................................

Flush Cache .....................................................................................................................................

Write Buffer E8h ............................................................................................................................

Power IdentifY Drive -

Set Features EFh .............................................................................................................................

Set Features (Ultra ATA/66) ..........................................................................................................

Read Defect List ..............................................................................................................................

Configuration .................................................................................................................................

Host Protected Mode Feature .......................................................................................................

ERROR

REPORTING ...............................................................................................................................

....................................................................................................................................... 6-1

INTERFACE

DESCRIPTION

Cable

and

INTERFACE

ADDRESS DESCRIPTIONS

DESCRIPTIONS .................................................................................................................

lxh

30h

..........................................................................................................................................

BOh

....................................................................................................................................

CBh

Management

......................................................................................................................... 6-1

................................................................................................................ 6-1

Connector ............................................................................................................. 6-1

.......................................................................................................................

DECODING

..............................................................................................................................

............................................................................................................................

...............................................................................................................................

Commands ...................................................................................................

ECh

......................................................................................................................

........................................................................................................

................................................................................................................... 6-22

Table

of

Contents

6-2 6-2

6-9

6-20

6-22

6-28 6-28

6-28 6-28 6-29 6-29 6-29 6-30

6-32 6-44 6-44 6-45 6-45 6-45 6-45 6-45 6-46 6-46 6-49 6-55 6-55 6-56 6-58

6-62 6-64

Quantum Fireball

CR

4.3/6.4/.B.4/12.7AT v

List

of

Figures

Figure 3-1 Mechanical Dimensions

Quantum Fireball Figure 3-2 Drive Figure 3-3 Drive

3-4

Figure

Figure 3-5 Jumper Locations on the Interface Connector .....................................

Figure 3-6 Figure 3-7 Mounting Dimensions for the

Figure 3-8 Mounting Screw Clearance for the

Figure 3-9 Breather Filter ........................................................................................

Figure 3-10 Figure 3 -11 Drive

Figure 3-12 Figure 5-1 Quantum Fireball

Figure 5-2 Quantum Fireball

Figure 5-3 Block Diagram ......................................................................................... 5-6

Figure 5-4 Read/Write Figure 5-5 Sector Data Field with

Figure 5-6 Byte Interleaving ................................................................................... 5-16

Figure 5-7 Figure 5-8 Figure 5-9 Twelve

Figure 6-1 Figure 6-2 Multiword

Figure 6-3 Initiating a Data In Burst ..................................................................... 6-14

Figure 6-4 Sustained Data In Burst ........................................................................ 6-14

Figure 6-5 Host

Figure 6-6 Device Terminating a Data In Burst ................................................... 6-15

Figure 6-7 Host Terminating a Data In Burst ....................................................... 6-16

Figure 6-8 Initiating a Data

Figure 6-9 Sustained Data Out Burst ..................................................................... 6-17

Jumper Locations for

AT

Packing Assembly ......................................................................... 3-2

Packing Assembly

Quantum Fireball

Connector

Quantum Fireball

J1

DC

Power

Power Supply

Completing the Drive Installation ..................................................... 3-15

Hard Disk Drive Exploded View ........................................................... 5-2

Hard Disk Drive Block Diagram ........................................................... 5-5

ASIC

Correctable and Un correctable Double-Burst Errors ........................ 5-17

Correctable and Uncorrectable Quadruple-Burst Errors ................... 5-18

Correctable Random Burst Errors ......................................... 5-19

PIO

Interface Timing ............................................................................. 6-10

DMA

Pausing a Data In Burst ............................................................... 6-15

CR

and

Jumper Location .....................................................

CR

and

ATA

CR

Block Diagram ........................................................... 5-9

Bus Interface Timing ............................................... 6-11

Out Burst 6-...................................................................

of

Hard Disk Drive ................................................. 3-1

of

a 20-Pack Container ............................... 3-3

the

Hard Disk Drive .................................................

Hard Disk Drives ............................................... 3-8

Hard Disk Drives ............................................... 3-9

Bus Combination Connector ...................... 3-11

and

ATA

Bus Interface Cables ....................... 3-14

4.3/6.4/8.4/12.7AT

4.3/6.4/8.4/12.7

ECC

Check Bytes ............................................ 5-15

AT

3-4 3-4 3-6

3-10

16

Quantum Fireball

CR

4.3/6.4/8.4/12.7AT vi

Table

of

Contents

Figure 6-10 Device Pausing a Data Out Burst ...................................................... 6-17

Figure 6-11 Host Terminating a Data

Out Burst .................................................. 6-18

Figure 6-12 Device Terminating a Data out Burst ............................................... 6-19

Figure 6-13 Host Interface

RESET

Timing ............................................................ 6-19

Quantum Fireball

CR

4.3/6.4/8.4/12.7AT vii

List

AT

Table 3-1 Table 3-2 Table 3-3 Table 4-1 Table 4-2 Table 4-3 Table 4-4 Table 4-5 Table 4-6 Table 4-7 Table 4-8 Table 4-9 Table 4-10 Table 5-1 Table 5-2 Table 6-1 Table 6-2 Table 6-3 Table 6-4 Table 6-5 Table 6-6 Table 6-7 Table 6-8 Table 6-9 Table

6-10 Table 6-11 Table 6-12

Table 6-13 Table 6-14 Table 6-15 Table 6-16 Table 6-17 Table 6-18

Table 6-19 Individual threshold data structure ..................................................................................... 6-37

Table

6-20 Device attributes data structure .......................................................................................... 6-39

Table 6-21 Individual attribute data structure ...................................................................................... 6-39

Table 6-22 Valid

Table 6-23 Identify Drive Parameters ......................................................................................................

Table 6-24 Transfer/Mode Values ............................................................................................................ 6-55

Table 6-25 Table 6-26 Table 6-27

Jumper Options .................................................................................................................... 3-5

J1

Power Connector, Section A ............................................................................................ 3-12

Logical Addressing Format ................................................................................................... 3-17

Specifications ............................................................................................................................. 4-1

Formatted

Timing Specifications ............................................................................................................... 4-4

Power Reset Limits .................................................................................................................... 4-5

Typical Acoustical Characteristics-Sound Acoustical Characteristics-Sound

Environmental Specifications .................................................................................................. 4-8

Shock and Vibration Specifications ........................................................................................ 4-9

Error Rates ...............................................................................................................................

Cylinder Contents Skews Drive

Series Termination for Ultra ATA/66 ...................................................................................... 6-6

Signal Line Definitions ............................................................................................................. 6-7

Interface PIO Multiword Ultra Host Interface I/O

Port

Command Device

Drive Address Register Bits ................................................................................................... 6-23

Error Register Bits .................................................................................................................. 6-24

Drive Head Register Bits ........................................................................................................ 6-25

Status Register

Quantum Fireball

Diagnostic

Device attribute thresholds data structure ......................................................................... 6-36

READ

AT

READ

DEFECT

Capacity ................................................................................................................... 4-3

Power and Current Consumption .............................................................................. 4-6

Pressure ........................................................................... 4-7

Power ............................................................................... 4-7

...................................................................................................................... 5-3

Offsets .......................................................................................................................... 5-13

Connector Pin Assignments

Signal Name Assignments ....................................................................................... 6-8

Host Interface Timing ........................................................................................................ 6-9

DMA

Host Interface Timing ............................................................................... 6-10

DMA

Data Transfer Timing Requirements ................................................................ 6-11

RESET

Timing ................................................................................................ 6-19

Functions and Selection Addresses ....................................................................... 6-20

Block Register Initial Values .............................................................................. 6-21

Control Register Bits .................................................................................................. 6-22

Bits

................................................................................................................. 6-26

CR

4.3/6.4/8.4/12.7AT Command Codes and Parameters .................. 6-27

Codes .................................................................................................................... 6-30

Count Range ................................................................................................................. 6-48

DEFECT

LIST

DATA

LIST

LENGTH

LIST

Command Bytes .........

FORMAT

(J

1,

Section

Command Byte:; .................................................................. 6-56

............................................................................................... 6-57

C)

............................................................... 6-3

.,

................................................................. 6-57

of

Tables

4-10

6-50

Quantum Fireball

CR

4.3/6.4/8.4/12.7AT viii

Table

of

Contents

Table 6-28 Table 6-29 Accessing Table Table 6-31 Accessing the

6-30

DEFECT

ENTRY

the

Accessing the

DATA

FORMAT

READ

CONFIGURATION

SET

CONFIGURATION

SET

CONFIGURATION

........................................................................................... 6-57

Command ............................................................ 6-58

Command ................................................................ 6-59

WITHOUT

SAVING

TO

DISK

Command .............. 6-60

Table 6-32 Configuration Command Format .......................................................................................... 6-60

Table 6-33 Command Errors ..................................................................................................................... 6-64

ix Quantum Fireball

CR

4.3/6.4/8.4/12.7AT

Chapter

I

1.1

1.2

ABOUT

This chapter gives an overview

audience, how the manual

AUDIENCE

The Quantum Fireball CR™4.3j6.4/8.4/12.7AT Product Manual is intended for several

audiences. These audiences include: the end user, installer, developer, original equipment manufacturer installation, principles maintenance.

MANUAL

This manual is organized into the following chapters:

• Chapter 1 -

• Chapter 2 - General Description

DEFINITION

(OEM),

and distributor. The manual provides information about

of

ORGANIZATION

About

This Manual

of

the contents

is

organized, terminology and conventions, and references.

operation, interface command implementation, and

THIS

of

this manual, including the intended

MANUAL

1.3

• Chapter 3 - Installation

• Chapter 4 - Specifications

• Chapter 5 - Basic Principles

• Chapter 6 -

TERMINOLOGY

In the Glossary

used in this manual. In addition, the following abbreviations are used in this manual:

•

ASIC

•

ATA

• bpi

•

dB

• dBA

•

ECC

• fei

ATA

Bus Interface and

AND

at

the

back

of

application-specific integrated circuit

advanced technology attachment bits per inch decibels

decibels, A weighted

error correcting code

flux changes per inch

of

Operation

ATA

Commands

CONVENTIONS

this manual, you can find definitions for many

of

the

terms

Quantum Fireball

CR

4.3/6.4/8.4/12.7AT 1-1

About This Manual

•

Hz

•

KB

•

LSB

• rnA

•

MB

• Mbitls

• MB/s

•

MHz

•

ms

•

MSB

• mv

• ns

• tpi

•

lIS

• V

The typographical

Conventions

hertz kilobytes least significant milliamperes megabytes

storage

megabits

megabytes

megahertz

milliseconds

most significant

millivolts

nanoseconds tracks per microseconds volts

that

(1

and

per

inch

and

naming

are unique

bit

MB

= 1,000,000 bytes

1,048,576 bytes in all

second

bit

conventions used in this

to

a specific table appear

when

other

cases)

manual

in

the

referring

are listed below.

notes

to

that

disk

follow

that

table.

Typographical Conventions:

• Names the Host Software Reset bit.

• Commands: Interface

WRITE

• Register Names: Registers example is

•

Parameters: are given as all capitals

(PE),

• Hexadecimal subscript form.

•

Signal Negation: A signal a minus sign following

• Messages: A message

capitals. An example is

of

Bits: Bit names

LONG.

the

Parameters are given as initial capitals

and

Cache Enable

Notation:

Alternate

An

example is 30R.

are

presented

commands

are

given in this manual

status

Register.

when

abbreviated. Examples are Prefetch Enable

(CE).

The hexadecimal notation is given in

name

that

the

signal.

that

is

sent

ILLEGAL

in

initial capitals.

are listed in all capitals.

with

initial capitals. An

when

is defined as

An

example is

from

the

COMMAND.

drive

active

RD-.

to

the

host

An

example

An

example

spelled

9-point

low is listed with

is listed in all

out,

is

and

1-2

Quantum

Fireball

CR

4.3/6.4/8.4/12.7AT

Naming Conventions:

Host: In general, the system

• host.

in

which the drive resides

is

referred to

About This Manual

as

the

1.4

• Computer Voice: This refers to items you type at These items are listed

FORMAT

c:

/S.

in

10-point,

REFERENCES

For additional information about the

•

IBM

Technical Reference Manual #6183355, March 1986.

•

ATA

Common Access Method Specification, Revision 4.0.

AT

the

all

capitals, Courier font.

interface, refer to:

computer keyboard.

An

example

is

Quantum Fireball

CR

4.3/6.4/8.4/12.7AT 1-3

About This Manual

1-4 Quantum Fireball

CR

4.3/6.4/8.4j12.7AT

Chapter

INSTALLATION

This chapter explains how to unpack., configure, mount, and connect the Quantum Fireball start up and operate the drive.

CR

4.3/6.4/8.4/12.7

AT

hard disk drive prior to operation. It also explains how

3

to

3.1

SPACE

REQUIREMENTS

The Quantum Fireball shows the external dimensions

CR

hard disk drives are shipped without a faceplate. Figure 3-1

of

the Quantum Fireball

CR

4.3/6.4/8.4/12.7AT drives.

Figure 3·1 Mechanical Dimensions

(4.00 inches)

of

Quantum Fireball

CR

Hard Disk Drive

CR

4.3/6.4/8.4/12.7AT 3-1

Installation

3.2

UNPACKING

DRAWING

INSTRUCTIONS

CAUTION: The maximum limits for physical shock can be exceeded

drive

is

not

handled properly. Special care should be

taken

not

to

bump

or

drop the drive.

that

Quantum Fireball CR drives

hard surface after they

are

unpacked. Such handling could cause

media damage.

1.

Open the shipping container and remove

the drive.

2.

Remove the drive from the packing assembly.

CAUTION: During shipment and handling. the antistatic electrostatic

charge

(ESD)

bag

prevents electronic component

to

damage due

to

the

drive. do

and

do

not

electrostatic discharge.

not

use a sharp instrument

touch

PCB

components.

possible future use.

3. When you are ready to install the drive. remove it from the

Figure 3-2 shows the packing assembly for a single Quantum Fireball

drive. A

20-pack shipping container

TO

BE

UPDATED

is

available for multiple drive shipments.

It

is

highly recommended

are

not

stacked

the

packing assembly

To

avoid accidental damage

to

Save

the

or

placed on any

open

the

packing materials for

ESD

if

that

ESD

bag. CR

the

contains

dis-

bag

hard disk

UpperP""

Hard

Disk

Drive

Lower Pad

Figure 3-2 Drive Packing Assembly

3-2

Quantum Fireball

CR

4.3/6.4/8.4/12.7AT

Installation

DRAWING

TO

BE

Top Pad

20

Disk

Drives

20

Drive

Multi-Pack-----

Container

Corner/side

Pads

UPDATED

-----

....

-_-I-

Bottom Pad

Container

Figure 3-3 Drive Packing Assembly

__

......_......,....;

of

a 20-Pack Container

Note: The 20-pack container should be shipped in the same way it was

received from Quantum. When individual drives are shipped from the 20-pack container then it should be appropriately packaged (not supplied with the 20-pack) to prevent damage.

Quantum Fireball

CR

4.3/6.4/8.4/12.7AT 3-3

Installation

3.3

HARDWARE

The configuration

on the host system options that you must take into account prior to installation. Figure printed circuit board options.

DC

Power

Connector

Jumpers

IDE

Bus---t

Interface Header

__

----I

Back

of

Drive

--I

OPTIONS

of

a Quantum Fireball

in

which it

(PCB)

is

to be installed.

assembly, indicating the jumpers that control some

D

t;;;;;~gb~~~~~~~~~~~~~~.-J

CR

4.3/6.4/8.4/12.7 This

o

section describes the hardware

AT

hard disk drive depends

3-4

shows the

o

o Front

of

Drive

of

these

Figure

• • • • • • • • • • •

..................

3-4 Jumper Locations

-cOO

7'.

~~~~~~.~=.~.~.~.~.~=.~.~.~'.

Master

~

Default Setting

Figure

.........

3·5 Jumper Locations on the Interface Connector

for

the Quantum Fireball

Back of Drive

UHf)

Jumper Configurations

Slave Cable Select

-==-c_s-'--os

....

9

Reserved Position for Slaves

CR

Interface Connector

AT

••

DS

with

not supporting DASP

Hard Disk Drive

•

•••••••••

. . . . . . . . . .

CS

3-4

Quantum Fireball

CR

4.3/6.4/8.4/12.7AT

Installation

CS

0 0

The configuration

•

CS

- Cable Select

•

DS

- Drive Select

of

the

following four jumpers controls

the

drive's mode

• PK- Jumper Parking Position (Slave mode)

The

AT

PCB

has two jumper locations provided for configuration options in a system. These jumpers are used to configure the drive for master/slave operation The default configuration for

across

the

DS

location, and open positions in

Table 3-1 defines

the

operation

the interface. 1 indicates

jumper

is

not

installed.

Table 3·1

OS PK

0

I

X X Drive X

28

X

that

Drive

the

drive as shipped from

the

of

the jumpers and their function relative

the specified

AT

Jumper Options

is

configured as a slave

is

configured as a Master

jumper

DESCRIPTION

the

factory is with a

CS

and

PK

positions.

is installed; 0 indicates

of

operation:

in

a system.

jumper

to

that

28

the

on

I I I

I

0 0 0

I

Note: In Table 3-1, a 0 indicates

3.3.1 Cable

When two Quantum Fireball

together, they can configure

(

1).

Once of a vendor-specific pin function is allocated this specification in Chapter Master. If it is a 1 (high), the drive drives in a Master/Slave relationship using the provides the proper signal level at pin 28 drives

X X Gnd Drive X Gnd X X

Select

you

the Cable Select signal: pin

Open

that

the

ting does

jumper

not

(CS) Jumper

the

install

be

drive as a Master

the

Drive

is

configured as a slave

is

configured as a Master

Drive

is

configured

Drive

is

configured as a Master with an attached slave

does

not

is

installed, and

support

that

DASP

the

an

as

jumper

matter.

CR

configured as Master

CS

jumper, the drive is configured as a Master

that

to

CS,

4.3/6.4/8.4/12.7AT hard disk drives are daisy-chained or

or

Slave with

28

of

the

ATA

Quantum is using for a specific purpose. More

according to the

1).

If

pin 28 is a 0 (grounded),

is

configured as a Slave.

of

to

operate in a Master/Slave relationship according

a Master with slave

present

is removed, a 1 indicates

X indicates

Slave either

the

bus connector. Please note

that

CS

feature, the

by

the

jumper

CS

or

CS

jumper

or

Slave

set-

DS

jumpers.

that

than

ATA

CAM

specification (see reference to

the

drive is configured as a

In

order

to

configure two

CS

jumper,

the

ATA bus connector. This allows two

you

need to use a cable

to

the drive cable placement.

that

To

is installed

by

the

state

28 is

one

that

Quantum Fireball

CR

4.3/6.4/8.4/12.7AT

3-5

Installation

3.3.2

3.3.3

3.3.4

Drive

jumper

Master

Select

You

can also daisy-chain two drives on the

Select

To

configure a drive as the Master (Drive

The Quantum Fireball

factory (Drive removed from the

Note: The order

(OS)

(DS)

jumpers.

as

a Master (Drive 0 -

1),

the

DS

jumper must be removed.

DS

nificance.

in

jumper

ATA

bus interface by using their Drive

To

use the

CR

position may be stored on the

which drives are connected in a daisy chain has

DS

feature, the

4.3/6.4/8.4/12.7AT hard disk drives are shipped from the DS

jumper

CS

jumper must be removed.

0),

ajumper

installed).

In

this configuration, the spare jumper

must be installed on the

To

configure a drive as a Slave

PK

jumper pins.

no

sig-

Parking (PK) Position

The

PK

that

unique. The drive will bias the parking position pins to detect the presence of this

jumper. When doing so it will maintain a minimum impedance of 4.7

supply and

In combination with the current can be implemented

position is used as a holding place for the jumper for a slave drive

do

not support Cable Select. The pins used for the parking position are vendor

2.4Kn to ground.

jumper

configuration

if

necessary as follows:

DS

or

CS

jumper settings, the Slave Present

KQ

in

to the

(SP)

DS

pins.

systems

+5

volt

jumper

3.3.5

• When the drive installed, and the

jumper (both jumpers

that a

Slave drive configuration should be installed on the Master drive only if the does

not use the Drive Active/Slave Present (DASP-) signal to indicate its

presence.

Reserved Position

Do

not put a jumper at the reserved position

Pin 1

1+----+

(to pin center)

is

configured as a Master

Cable Select signal

DS

and

CS

now installed) will indicate to the drive

is

present. This Master with Slave Present jumper

Pin 1

of

(DS

jumper installed or

is

set to (0), adding an additional

(RSVD).

AT

Connector

••••••••••

29.78±O.50 (to pin center)

Connector Side

CS

jumper

Slave drive

4.55±O.50

3-6 Quantum Fireball

Figure 3-6

CR

4.3/6.4/8.4/12.7AT

AT

Connector and Jumper Location

Installation

3.4

3.4.1

3.4.2

ATA

40-Pin

BUS

ADAPTER

There are two ways disk drives

1.

2.

Most with the drives. between the drive and

You should also refer to this manual

to

Connect

PC.

of the Install

an

adapter board.

AT

A Bus

PC

motherboards have a built-in 40-pin

40-pin

If

the

to

you

communicate over the

the

drive to a

IDE-compatible adapter board in the

Connector

ATA

motherboard has an

interface

ensure signal compatibility.

can configure a system to allow the Quantum Fireball

ATA

bus

of

an

IBM

or IBM-compatible

4Q..pin

AT A bus connector (if available)

PC,

and connect the drive to the

ATA

bus connector that

of

the Quantum Fireball

ATA

connector, simply connect a 40-pin ribbon cable

the

motherboard.

the

motherboard instruction manual, and refer to Chapter 6

CR

4.3/6.4/8.4/12.7AT hard disk

on

the motherboard

is

compatible

Adapter Board

If your you must install an ATA bus adapter board and connecting cable to allow the drive to interface with the motherboard. Quantum does they are available from several third-party vendors.

PC

motherboard does

not

contain a built-in 40-pin

not

ATA

bus interface connector,

supply such an adapter board, but

CR

PC:

hard

of

Please carefully read well as Chapter 6 board and appropriate.

the

of

drive. Also, make sure

the

instruction manual that comes with your adapter board,

this manual

to

ensure signal compatibility between the adapter

that

the adapter board jumper settings are

as

Quantum Fireball

CR

4.3/6.4/8.4/12.7AT 3-7

Installation

3.S

3.S.1

MOUNTING

Drive mounting orientation, clearance, and ventilation requirements are described in the

following subsections.

Orientation

The mounting holes on the Quantum Fireball allow the drive to be mounted in any orientation. Figures 3-6 and 3-7 show the location of

the three mounting holes on each side

using

the

four mounting hole locations on the

Note:

All dimensions are in millimeters. For mounting, #6-32

It

is

highly recommended chassis for test purposes. Failure to hard mount the drive can result in erroneous errors during testing.

Drives can be mounted in any orientation. Normal position the

of

the system being used for general operation, as well as

PCB

facing down.

that

the

CR

4.3/6.4/S.4/12.7AT hard disk drives

of

the drive.

PCB

drive is hard mounted on to

The

drive can also be mounted

side of the drive.

UNC

screws are recommended.

is

the

with

101.60 ±0.25

147.00

Max

¢

28.50 ±0.50

,

±0.50

j

25.4

±0.5

Figure 3-7 Mounting Dimensions

I~

~

LJ

41.28

for

the Quantum Fireball

~

I I

~

0

95.25

±0.25

101.6

±0.25

CR

I

0

D

~

Hard Disk Drives

3-S Quantum Fireball

CR

4.3/6.4/S.4/12.7AT

Installation

f-ooII--

6.35

Figure 3-8 Mounting Screw Clearance for the Quantum Fireball

CAUTION: The

PCB

is

very close specified length for length allows damaging

full

or

placing unwanted stress on

to

the mounting holes.

the

mounting screws. The specified screw

use of

the

mounting hole threads, while avoiding

specifies the minimum clearance between in

the

mounting holes.

threads,

the

maximum

To

avoid stripping

torque

applied

to

the

the the

the exceed 8 inch-pounds. A maximum screw length of 0.25 inches may be used.

mm

Maximum

CR

Hard Disk Drives

Do

not

exceed

PCB.

Figure 3-8

PCB

and

the

mounting hole

screws must

(O.25

the

screws

not

Inches)

Quantum Fireball

CR

4.3/6.4/S.4/12.7AT

3-9

Installation

Breather Filter Inlet

Figure 3-9 Breather Filter

CAUTION:

The Quantum Fireball CR 4.3/6.4/S.4112.7AT hard disk drives use a breather filter between Blockage of this air inlet could result the

HDA and could cause damage

(see Section

to

eliminate pressure differences

the

inside and outside of

5.1.7 for

more

the

details).

that

may develop

Head Disk Assembly (HDA).

in

to

the

pressure

building

gasket sealing

up

the

inside

HDA

3-10 Quantum Fireball

CR

4.3/6.4/8.4/12.7AT

Installation

3.5.2

3.5.3

3.6

Clearance

Clearance from minimum

the

drive to any other surface (except mounting surfaces) must be a

of

1.25 mm (0.05 inches).

Ventilation

The Quantum Fireball fan, provided the ambient air temperature does

along

the

drive form factor envelope.

COMBINATION

J1 is a three-in-one combination connector. The drive's section A. The ATA bus interface the back edge

of

CR

4.3/6.4/8.4/12.7

CONNECTOR 0 I)

the

printed-circuit board

(40-pin) uses section

AT

hard disk drives operate without a cooling

(PCB),

not

exceed 131°F

DC

C.

as shown in Figure 3-10.

The connector is mounted on

(55°C)

power can be applied to

at any point

40-Pin IDE

(J1

Section

•••••••••••••••••••••

• • • • • • •

40

Figure 3-10

••

Jl

DC Power and

J1

IDE (40-Pin)/DC (4-Pin)

Combination Connector

C)

1

\ 4 3 2 1

,

•••••••••

ATA

Bus Combination Connector

Quantum Fireball

DC

4-Pin

(J1

~

•••

~...

~_~;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;=.LJ

(0

_ J

CR

4.3/6.4/8.4/12.7

Power

Section

0 0

A)

0\

AT

3-11

Installation

3.6.1

NUMBER

DC

J 1 Section A (4-Pin):

1

2

3

4

Power

The recommended

listed in Table

+12VDC Ground

Return for +12VDC

Ground Return for +5 VDC

+5VDC

Note: Labels indicate

(J

I ,

Table 3-2 11 Power Connector, Section A

VOLTAGE

LEVEL

section A are er

on

Section

mating

3-2.

4-Pin

Loose piece contacts:

Strip

the

drive.

A)

connectors

MATING

Connector:

AMP

contacts:

AMP

the

+5

and

for

the

CONNECTOR

(OR

PIN 1-480424-0

P/NVS 60619-4

P/NVS 61117-4

numbers

+ 12

volt

on

the

returns

+5

VDC

and

+ 12

TYPE

AND

EQUIVALENT)

connector.

and

Pins 2 and 3 of

are

connected

VDC

PART

input

NUMBER

togeth-

power

are

3.6.2

3.6.3

External Drive Activity

An

external drive activity

more details,

AT

A Bus Interface

On

the

connector

cable

To

prevent

removing Pin 20. This ensures See Chapter

about connector

see

the

pin description

Connector

Quantum Fireball

(J

1,

section

the

possibility

6,

"ATA Bus Interface

the

required signals. Refer

(J1, section

C).

CR

LED

may

be

connected

in

Table 6-1.

0 I,

Section

4.3/6.4/8.4/12.7AT hard disk drives, C)

is a

40-pin

of

incorrect

that a connector

and

to

Universal Header,

installation,

ATA Commands," for

Table 6-1 for

to

the

C)

the

cannot

the

DASP-I/O

connector

be

assignments

39

on

J1.

the

ATA

bus

interface

as

shown

installed upside down.

more

in Figure 3-10.

has

been

keyed

detailed information

of

the

ATA bus

For

by

3-12 Quantum Fireball

CR

4.3/6.4/S.4/12.7AT

Installation

3.7

3.8

3.8.1

FOR

SYSTEMS

You can install the Quantum Fireball

compatible system that contains a 40-pin

To

connect the drive to the motherboard, use a 40 conductor ribbon cable

ribbon cable

of

the drive

1

FOR

SYSTEMS

To

install the Quantum Fireball compatible system without a 40-pin a third-party IDE-compatible adapter board.

Adapter

Carefully read the manual that accompanies your adapter board before installing it. Make sure that all the jumpers are set properly and conflicts. You must also investigate to see combination floppy and hard disk controller board. disk drive controller functions on

Once you have disabled the hard disk drive controller functions on the floppy/hard drive controller, install the adapter board. Again, make sure that you have set all jumper straps on the adapter board to avoid addressing and signal conflicts.

Board Installation

WITH A MOTHERBOARD

CR

4.3/6.4/8.4/12.7AT hard disk drives in an ATA

if

using UltraATA/66 drive)

is

connected to pin 1

WITH

AN

AT A ADAPTER

CR

18

of

the motherboard connector.

4.3/6.4/B.4/12.7AT hard disk drive in an ATA

bus connector on its motherboard, you need

if

that

controller board before proceeding.

ATA

bus connector on the motherboard.

inches in length or shorter. Ensure that pin

ADAPTER

(80

conductor

BOARD

AT-

that

there are no address or signal

your AT-compatible system contains a

If

it does, you must disable the hard

AT-

Note: For Sections 3.7 and

puter before installing the drive.

3.B,

power should be turned off on the com-

Quantum Fireball

CR

4.3/6.4/8.4/12.7

AT

3-13

Installation

3.8.1.1

Connecting the Adapter Board and the Drive

Use

a 40-pin ribbon cable to connect the drive to the board. See Figure 3-11.

the drive to the board:

1.

Insert the 40-pin cable connector into the mating connector of Make sure that pin 1 of the connector matches with pin 1

2.

Insert the other end this end

of

the cable, make sure that pin 1

of

the cable into the header on the drive. When inserting

of

the cable connects to pin 1

on

the

cable.

drive connector.

3. Secure the drive to the system chassis by using the mounting screws, as shown in Figure 3-12.

IDE-Bus Interface Connector

40-Pin Header

Key Slot

To

connect

adapter board.

of

the

IDE-Bus Interface Cable

Power Supply Cable

Figure 3-11 Drive Power Supply and

3-14 Quantum Fireball

(3-Pin or 4-Pin)

CR

4.3/6.4/8.4/12.7AT

-......

ATA

Bus Interface

DC Power Connector

Cables

\"'"'

___

-1"

Bevel

IDE-bus

Interface

Cable

Installation

Quantum

r

Fireball

I Drive

CR

3.9

3.9.1

Mounting

Screws

TECHNIQUES

The

Older based operating systems will be limited to use only 1024 cylinders. This will reduce effective capacity

Whenever possible the Quantum Fireball on systems disk drive.

overcome this barrier.

Figure 3-12 Completing the Drive Installation

IN

DRIVE

CONFIGURATION

S28-Megabytes Barrier

BIOS

that

only support Int

of

the drive to 528 Mbytes.

that

support

If

that

• Use a third party software program that translates the hard drive parameters to an acceptable configuration for

LBA

is not possible the following are some techniques

13

commands for accessing

CR

translation to ensure the use

4.3/6.4/8.4/12.7

MS-DOS.

ATA

drives through

AT

drive should be used

of

the entire capacity

that

DOS

the

of

the

can be used to

• Use a hard disk controller that translates the hard drive parameters to an appropriate setup for both

MS-DOS

and the computer system's

Quantum Fireball

ROM-BIOS.

CR

4.3/6.4/8.4/12.7AT 3-15

Installation

3.9.2

The

S.4-Gigabytes Barrier

Newer

BIOS

allow users to configure disk drives go beyond

several

using Int barrier

To BIOS space (64 bits) resulting on 9.4 Terrabytes

Whenever possible the Quantum Fireball

on systems with are some techniques that can be used to overcome this barrier:

BIOS

translation schemes. However, while using these translations

13

functions are limited to 24 bits

at

the 8.4

overcome this barrier a new set

manufacturers. The new Int

•

Use

a third party software

extension support.

GB

BIOS

capacity.

that

support Int

that

of

addressing which results in another

ofInt

13

extensions are being implemented

13

extension allows for four words

of

accessible space.

CR

13

supplements

4.3/6.4/B.4/12.7AT drive should be used

extensions. If that is not possible the following

the

BIOS

and adds Int

528

MB

barrier

the

of

addressing

13

by

BIOS

by

using

most

3.9.3

• Obtain a board manufacturers allow their special download utilities. Information on

on the

Operating

Most popular operating systems available today have additional limitations which

affects the use corrected on improved versions to address these problems.

The most popular operating systems available today, Allocation Table

drives. A newer release system manufacturers only. This new

Terrabytes.

BIOS

upgrade from

System Board Customer Service respective web sites on the Internet.

system

the

limitations

of

a large capacity drives. However, these limitations can

BIOS

and it

(FAT)

size

of

the

system board manufacturer. Many system

BIOS

to

be upgraded on the field using

BIOS

upgrades can be obtained

is

up to the operating system manufacturers to release

DOS

of

16 bits which will only support portions up

Win 95 called

OSR2

which 32 bits

FAT

size table will support partitions

and Win 95, use a File

FAT

has been released

not

to of

be

2.1

GB

to

up to 2.2

3-16 Quantum Fireball

CR

4.3/6.4/8.4/12.7AT

Installation

3.10 SYSTEM

Once you have installed the Quantum Fireball and adapter board (if required) in the host system, you are ready to partition and format

the drive for operation.

1.

Power on the system.

2.

Run the

within the system's

making

3.

Enter the appropriate parameters.

The

SETUP

as the hard disk drive type, the floppy disk drive capacity, and the display adapter type.

The system's

switched on. For instructions on how to use the manual for your

During the Fireball geometry parameters such addressing mode. The drive can work with different

various host systems.

You can choose any drive type that does gives the logical parameters that provide the maximum capacity Fireball

STARTUP

SETUP

program allows you to enter the types

BIOS

AND

To

program. This

OPERATION

CR

4.3/6.4/8.4/12.7AT hard disk drive,

set up the drive correctly, follow these steps:

is

generally on a Diagnostics

BIOS.

Some system

BIOS

have an auto-detecting feature

unnecessary.

of

uses this information to initialize

optional hardware installed-such

the

SETUP

Pc.

AT

system

CR

hard disk drives. The drive supports the translation

CMOS

setup, you must enter the drive type for the Quantum

as

cylinders, heads, and sectors per track to a logical

BIOS

not

exceed the capacity

CR

family

of

hard disk drives.

or

Utilities disk, or

system when the power

is

program, refer to the system

of

its physical drive

drive-type tables

of

the drive. Table 3-3

on

the Quantum

of

the

LBA

Capacity CHS Capacity Logical Cylinders Logical Heads Logical SectorsfTrack

Total

Number

Logical Sectors

Note: * The

To consult the system's drive-type table. This table specifies the heads, and sectors for a particular drive type.

Table

3-3 Logical Addressing Format

4.3 6.4

4.3

GB

4,320

MB

TBD TBD

15 15

63

8,391,600 12,586,896 165,514,064 24,901,632

AT

capacity

is

artificially limited to a

match the logical specifications

QUANTUM

6.4 GB

6,480

63

of

the drive to the drive type

MB

FIREBALL

8,640

2.1

GB

CR

8.4

8.6GB MB

TBD

16

63 63

12,960

partition boundary.

of

a particular

number

of

cylinders,

12.7

12.9

TBD

GB

MB

16

BIOS,

Quantum Fireball

CR

4.3/6.4/8.4/12.7AT 3-17

Installation

You must choose a drive type

For the 4.3

AT:

Logical Cylinders x Logical Heads x Logical Sectors/Track x

For the 6.4

AT:

that

meets the following requirements:

512

= 4,296,499,200

Logical Cylinders x Logical Heads x Logical Sectors/Track x 512 = 6,444,490,752

For the 8.4

AT:

Logical Cylinders x Logical Heads x Logical Sectors/Track x 512 = 8,455,200,768

For the 12.7

AT:

Logical Cylinders x Logical Heads x Logical Sectors/Track x 512 = 12,749,635,584

4. Boot the system using the operating system installation disk-for example, MS-DOS-then follow the installation instructions in the operating system manual.

3-18 Quantum Fireball

CR

4.3/6.4/8.4/12.7AT

Chapter

SPECIFICATIONS

4

This chapter gives a detailed description

4.1

characteristics

SPECIFICATION

of

the Quantum Fireball

SUMMARY

Table 4-1 gives a summary

DESCRIPTION

Formatted Capacity Nominal rotational Number Number Data

Sectors

Recording:

of

Disks

of

RfW heads

Organization:

Zones

per

Tracks

per

Total tracks 25,030

per

track: Inside zone Outside Total

User

Bytes

per

Number

Recording technology

Maximum linear density

Encoding

Interleave

Track density

Maximum effective areal den-

sity

speed

(rpm)

surface

surface 12,515 12,515 12,515 12,515

zone

Sectors 8,391,600 12,586,896 165,514,064 24,<)01,632

sector

of

tracks

per

cylinder

method

of

the physical, electrical, and environmental

CR

hard disk drives.

of

the Quantum Fireball

Table

4-1

Specifications

QUANTUM

4.lAT

4,320

MB

5,400 5,400 5,400 5,400

6,480

6.4

AT

MB

CR

hard disk drives.

FIREBALL

8.4

8,640

AT

MB

CR

12.7

12,960

I 2 2 3

2 3

15

250 250 250

406 406

512 512

2 3 4

Multiple

Zone

260,000

24/25

13,000 tpi 13,000 tpi 13,000 tpi 13,000 tpi

fci

16117,

PRML

1:1

3,250 3,250 3,250 3,250

Mbits/in

2

15

37,545 50,060 75,090

MUltiple Multiple Multiple

Zone

260,000

24/25

Mbits/in

fci

16117, 16117,

PRML

1:1

2

4

15

406

512

Zone Zone

260,000

24/25

Mbits/in

fci

PRML

1:1 1:1

2

260,000

24/25

Mbits/in

AT

MB

6

15

250 406

512

6

fci

16/17,

PRML

2

Quantum Fireball

CR

4.3/6.4/8.4/12.7AT 4-1

Specifications

DESCRIPTION

Performance:

Seek times:

Read-on-arrival

T

rack-to-track

Average

Full

stroke

Data

transfer

Disk

2

Disk

Instantaneously'

Read Buffer (PIO Mode with IORDy) max. max.

Read Buffer

(Ultra

Buffer

Size

Reliability:

Seek

error

Unrecoverable

Error

correction

cross

(with

Projected

Contact (Ambient

Auto

head-park

write

QUANTUM

4.3

AT

9.5

ms

11.5

typo

ms

max. 11.5

1.5

ms

9.5 ms

typical typical

11.0

ms

typo

11.0

13.0 ms max. 13.0 IS.O

ms

typo

IS.O

22.0 ms max. 22.0

6.4

ms

1.5

ms

AT

typo

FIREBALL

8.4

9.5 ms

CR

AT

typo

max. 11.5 ms max. 11.5 ms max.

1.5

ms

typical

typo

11.0 ms

typo

max. 13.0 ms max.

typo

IS.O

ms

typo

max. 22.0 ms max. 22.0 ms max.

Rates:

to

Read

Once

a Revolution" 76.6 MB/sec

76.6

MB/sec

76.6 MB/sec 76.6 MB/sec

min. min. min.

12S.6 MB/sec 12S.6 MB/sec

12S.6 MB/sec

max. max. max. max.

to

Read

103.52

MBI

sec

min. sec min.

103.52

MBI

103.52

MB/

sec

min. sec min.

171.3 MB/sec 171.3MB/sec 171.3 MB/sec 171.3 MB/sec

max. max. max. max.

to

ATA

Bus

16.7 MB/sec. 16.7 MBJsec. 16.7 MB/sec. 16.7 MB/sec. max. max.

to

ATA

Bus 33 MB/sec. 33 MB/sec. 33 MB/sec. 33 MB/sec.

ATA

Mode) max. max. max. max.

512

KB

2

rate

error

method

rate

2

I

in

10° I

14

I

in

10

28S-bit 28S-bit 2SS-bit 288-bit

check) Reed Reed

Solomon

MTBF3

Start/Stop Cycles

4

625,000

hrs

625,000 hrs 625,000 hrs 625,000 hrs

50,000 min. 50,000 min.

512KB

in

10° I

14

I

in

10

Solomon

512

KB

in

10° I

14

I

in

10

Reed Reed

Solomon

50,000 min. 50,000 min.

temperature)

method

AirLock® with Magnetic

Actuator

Bias

I

2.7

AT

9.5 ms

1.5

typo

ms

typical

11.0 ms

typo

13.0 ms max. IS.O

ms

typo

min.

128.6

MB/sec

103.52

MBI

512

KB

in

10°

14

I

in

10

Solomon

1.

Disk to read buffer transfer rate is zone-dependent, instantaneous

2.

Refer to Section 4.12, "DISK

3.

CSS

specifications assumes a

idle spin down.

4-2 Quantum Fireball

CR

4.3/6.4/8.4/12.7AT

ERRORS"

duty

cycle

for details

of

one power

on

error rate definitions.

off

operation for every one

Specifications

4.2

FORMATTED

At

the

factory, low-level format the

capacity

with

DOS,

UNIX,

capacity

shown

CAPACITY

the

Quantum Fireball

that

creates

resulting from this process. Formatting done

or

other

operating systems, may result in less capacity

in

Table 4-2.

Table 4-2 Formatted Capacity

4.3

Formatted Capacity 4,320

Number

4.3

of

512-byte

DATA

sectors

Note: * The AT capacity is artificially limited

TRANSFER

Data is transferred from Data is using For more detailed information

available 8,391,600 12,586,896 165,514,064

RATES

the

transferred

programmed

from

I/O

the

with

disk to

10RDY,

CR

the

actual tracks

AT

MB

read buffer to the ATA

on

4.3/6.4/8.4/12.7AT and

sectors on

QUANTUM

6.4

6,480

the

read buffer

or

at

interface timing, refer to Chapter

a rate

FIREBALL CR

AT

MB

to

a 2.1

at

a rate bus

of

up

to

hard

disk drives receive a

the

drive. Table 4-2 shows

at

the

user level, for operation

than

the physical

8.4

AT

8,640

MB

GB

partition boundary.

of

up to

at

a rate

66 MB/s using UltraATA/66.

171

of

12.7

AT

12,960

MB

24,901,632

Mb/s in bursts.

up to 16.7 MB/s

6.

Quantum Fireball

CR

4.3/6.4/8.4/12.7AT 4-3

Specifications

4.4

TIMING

SPECIFICATIONS

Table 4-3 illustrates

the

timing specifications

drives.

Table 4-3 Timing Specifications

PARAMETER

Sequential Cylinder Switch Time" 3.0 ms

or

4

Seekf

Sequential Head Switch Time Random Average (Read Random Average

(Writef

Full-Stroke Seek

Average Rotational Latency 5.59

Power

On'

to

Drive

Readyo

Standby'

to

Interface Ready 9.0 seconds Spindown Time, Standby Command Spindown Time, Power loss

1.

Nominal conditions are as follows:

-Nominal temperature Nominal supply voltages (12.0V,

-

-No

applied shock

2.

Worst case conditions

-Worst

3.

Sequential Cylinder Switch Time a cylinder to

case temperature extremes 32 case supply voltages (12.0V ±10%, 5.0 V

the

or

vibration

are

first logical sector on

switches exceed this time).

4.

Sequential Head Switch Time is the time from beginning than

S.

Power

of

the first logical sector

6%

of

head switches exceed this time).

On

is

the

time from when the

the drive is ready to accept

6. Drive Ready is the condition in which the drive is able to accept further delay

at

power

or

long as 4S seconds for drive ready.

the

7. Standby is

the

When from

the

S.

After this time

9. Average

cylinders

condition

host sends

data

zone,

it

random

(LBA).

the

and

is

safe to move the disk drive

seek is defined as the average seek time between

TYPICAL

NOMINAL!

2.5 ms 3.0 ms

9.5

11.0

18.0

9.0 seconds

20.0 seconds

18.0 seconds

77·F (25·C)

as follows:

is

the time from

of

any

command.

and

execute commands requiring disk access

start up. Error recovery routines may

at

which the microprocessor is powered,

drive a shutdown command,

spins down

of

the

Quantum Fireball

ms

ms ms ms

S.OV)

to

131·F

the

supply

voltages reach operating

the

disks

are

to

a complete stop.

(5"C

to

5S·C)

±S%)

the

conclusion

last sector

of

the

rotating

the

CR

hard disk

WORST

2

CASE

".Oms

11.5

ms

13.0 ms

22.0 ms

-

12.0 seconds

12.0 seconds 15

seconds

30 seconds

of

than

of a track

same cylinder (no more

at

the

extend

drive parks

6

the

last

sector

6%

of

cylinder

to

the

range

to

rated speed,

without

the

time

but

not

the

heads

random

logical

of

when

and

to

as

HDA.

away

4-4

Quantum Fireball

CR

4.3/6.4/S.4/12.7AT

4.5 POWER

Specifications

4.5.1

4.5.2

The Quantum Fireball

CR

4.3/6.4/8.4/12.7AT hard disk drives operate from two supply

voltages:

• + 12V ± 10

0

/0

• +5V ±5%

The allowable ripple and noise

mV

peak-to-peak for the

Power

Sequencing

+5

Volt supply.

peak-to-peak for the +

12

Volt supply and 100

is

250

mV

You may apply the power in any order, or open either the power or power return line with no loss

being written

of

data

at

or

damage to the disk drive. However, data may be lost in the sector

the time

of

power loss. The drive can withstand transient voltages

+ 1 0% to -100% from nominal while powering up or down.

Power

Reset

Limits

When powering up, the drive remains reset until both V

reset limits in Table

HT

exceeded. When powering down, the drive becomes reset when either supply voltage

drops below the

DC

VOLTAGE

+SV

V

LT

threshold.

Table

THRESHOLD

V

= 4.6SV maximum,

LT

V

=

HT

4-4 Power Reset Limits

4,4V minimum

4.7IV

maximum,

4,43V minimum

HYSTERESIS

70 mV (typical)

4-4

of

are

+12V

V

= 9.3V maximum,

LT

8.7V minimum

V

= 9.S8V maximum,

HT

8.82V minimum

Quantum Fireball

200

mV

CR

4.3/6.4/8.4/12.7AT

(typical)

4-5

Specifications

4.5.3

MODE

OPERATION

MODEL

Startup 1 (peak)

3

Idle Operating Maximum Standb SI

eep

4

6

y

7

Power

Requirements

Table 4-5 lists the voltages and typical average corresponding currents for the various

modes

of

OF

NUMBER

Seekin~

operation

4.3

1703

192 381 664

38 38 38 38

of

the Quantum Fireball

Table

4-5 Typical Power and Current Consumption

TYPICALAVERAGE

(MA

RMS UNLESS OTHERWISE

+12V

6.4

1670

224 407 687

8.4 12.1 4.3 6.4

1670

224 407 687

38 38

1682

280 462 742

38 38

CR

hard disk drives.

CURRENT

627 624 436 442 441

110 110

2

NOTED)

+5V

434

440

439

110 110

8.4

624 434

440

439

110 110

12.7 652

450 456 455

110 110

ReadIWrite

MODEL

Startupl (peak)

3

Idle Operating

Maximum

StandbY' SI

7

eep

ReadIWrite

On

Tracks

MODE

OF

OPERATION

NUMBER

4

Seekin~

On

TrackS

1. Current

peaks greater than

2.

Power requirements reflect nominal for +

192

is

220

220 273

TYPICALAVERAGE

4.3 6.4

23.6

4.5

6.8

10.2 10 10 10

4.5

23.2

4.9

7.1

10.4

10

4.9

449

444

POWER2 (WATTS)

8.4

23.2

4.9

7.1

lOA

10 10

4.9

444

rms except for startup. Startup current is the typical peak current

10

ms

in duration.

12V

and +

5V

power.

12.7

23.4

5.6

7.8

11.2 10 10

5.6

460

of

the

4-6 Quantum Fireball

CR

4.3/6.4/S.4/12.7AT

3.

Idle mode any commands. A portion

is

in effect when the drive is not reading, writing, seeking, or executing

of

the R/W circuitry

is

powered down, the motor

speed and the Drive Ready condition exists.

4.

Operating mode is

computed based on 40% seeking, 30% on-track read,

is

defined

as

when data

is

being read from or written to the disk.

20%

idle, and

write.

5.

Maximum seeking

is

defined as continuous random seek operations with minimum

controller delay.

6.

Standby mode is defined all

electronics except the interface control are in low power state. Standby occurs

as

when the motor

is

stopped, the actuator

after a programmable time-out after the last host access. Drive ready and seek

complete status exist. The drive leaves standby upon receipt

of

a command that

requires disk access or upon receiving a spin up command.

7.

Sleep

is

defined

latched in the landing zone. Receipt

as

when the spindle and actuator motors are off and the heads are

of

a reset causes the drive to transition from the

sleep to the standby mode.

S.

Read/Write

On

Track is defined as 50% read operations and 50% write operations on

a single physical track.

Specifications

is

10%

on-track

is

parked, and

up to

It

4.6

OPERATING

ACOUSTICS

Table 4-6 and Table 4-7 specify the acoustical characteristics of the Quantum Fireball

4.3/6.4/S.4/12.7AT hard disk drives.

MODE

Idle

On

Track

OPERATING

Idle

On

Track

Table 4-6 Acoustical Characteristics-Sound Pressure

MEASURED

(SOUND

32 dBA (typical)

35 dBA (maximum)

NOISE

PRESSURE)

Table 4-7 Acoustical Characteristics-Sound Power

MODE

1,2-Disk 3.5

3,4-Disk

MEASURED

(SOUND

TYPICAL

Bels

3.8 Bels

POWER

NOISE

PER

DISTANCE

in

(I

39.3

ISO

MAXIMUM

3.6 Bels

3.9 Bels

m)

7779)

CR

Quantum Fireball

CR

4.3/6.4/S.4/12.7AT 4-7

Specifications

4.7

4.8

Temperature}

(Non-condensing)

MECHANICAL

Height: 1.0 in. Width: Depth: 5.75 in. Weight:

4.0 in.

ENVIRONMENTAL

Table

4-8

summarizes the environmental specifications

disk drives.

PARAMETER OPERATING

(25.4 mm) (101.6 mm) (146.1 mm) Quantum Fireball Quantum Firebal Quantum Fireball

CONDITIONS

Table 4-8 Environmental Specifications

5°

to

55°C

(41°

to

131°F)

CR

4.3AT

CR

6.4/S.4AT

CR12.73AT

TBD

lb (.xxx

TBD

lb (.xxx kg)

TBD

lb (.xxx kg)

of

the

Quantum Fireball

kg)

NON-OPERATING

_40°

to

65°C

(_40°

to

149°F)

CR

hard

Temperature

(Non-condensing)

Humiditl Maximum

Temperature

Humidity Altitude

Altitude

Gradient

(Non-condensing)

Wet

Bulb

Gradient

3

,4

Gradient

1.

Maximum

drive form factor envelope. Airflow

this requirement.

2.

The

not

Altitude

3.

4. The specified drive uncorrectable error rate will conditions.

operating temperature must

humidity

result

range shown is applicable

in

condensation in violation

is relative

to

sea level.

24°C/hr maximum 48°C/hr maxirnum

(75.2°F/hr)

10%

30°C

30%

-200 (-650

1.5

to

85%

(86°F)

I

m

to

10,000 ft.)

kPalmin

RH

hour

3,000 m

not

or

other

of

exceed

means must be used as needed to

for

temperatures whose combination does

the

wet

bulb specifications.

not

( 118.4°F/hr)

5%

to

95%

40°C (104°F)

30%

I

hour

-200 m to (-650

the

drive

be

exceeded over these

12,000 IT:

to

40,000 ft.)

8 kPalmin

at

any

RH

point

along

the

meet

4-8

Quantum

Fireball

CR

4.3/6.4/8.4/12.7AT

Specifications

4.9

SHOCK

The Quantum Fireball

shock base axis, as specified in Table 4-9. A functioning drive operating levels nonoperating levels loss

When packed in its withstand a drop from or onto

AND

and

of

user

three comers. The 12-pack shipping

a concrete surface

VIBRATION

CR

vibration applied to

of

shock

of

shock

data

at

power

I-pack

30

OPERATING NONOPERATING

l

Shock

1/2

sine wave, II ms duration 20.0 Gs

1/2

sine wave, 3 ms duration

1/2

sine wave, 2 ms duration

4.J/6.4/S.4/12.7AT any

of

its

and

vibration.

and

vibration,

on.

shipping container,

inches

on

any

Table

18Gs

N/A

onto

a concrete surface

container

of

its surfaces, six edges,

4·9

Shock and Vibration Specifications

hard

disk drives can withstand levels

three

mutually

When

a drive

with

power

the

200 Gs Rotational: 15,000 rad/sec2 2 applied Trapezoidal:

perpendicular axes,

can

has

been subjected

to

the

Quantum

on

any

can

withstand

or

three comers.

at

actuator

80

Gs.

be subjected to specified

drive off,

Fireball

110

pivot point

18

CR

of

its surfaces, six edges,

a drop from

70Gs

N/A

Gs

inlsec velocity change

or

principal

to

specified

there

will

drives can

30

ms

of

be

no

inches

Vibration

Random Vibration (G

Sine

112

4.10

l

wave (peak

octave

per

to

minute sweep

1.

HANDLING

Before

ensure

the

however, drive, rough earth is until

Note: To avoid causing

2

/Hz)

peak)

The specified drive unrecovered error rate will

handling that

the

drive

by

hard

strongly

ready

to

Circuit Board drive.

0.004 (10 - 300Hz)

0.0006 (300 -

I GP-P 5-400 Hz 2 Gs

the

DRIVE

the

Quantum

drive is

its edges. Quantum drives are designed

drives

handling,

install.

not

can

and

recommended. Always keep

(PCB)

450

Hz) 0.012 (300 - 500 Hz)

hard

disk drive

damaged. Use

be

damaged

mishandling. Use

any

damage

or

any

of

by

to its

both electrostatic discharge

the

components

0.05 (10

not

be

exceeded over

some

precautions need to

hands

while handling the drive and hold

to

withstand normal handling,

of a properly the

drive inside its special antistatic

drive do

not

when

touch

- 300 Hz)

P-P

5-500

(ESD),

grounded wrist strap

the

Printed

handling

the

Hz

these

conditions.

be

taken

dropping

to

the

to

the

bag

Quantum Fireball

CR

4.J/6.4/S.4/12.7AT 4-9

Specifications

4.11

4.12

4.13

RELIABILITY

Mean Time Between Failures

Component Life: 5 years Preventive Maintenance Start/Stop:

CSS

Note:

specification assumes a duty cycle

for every one idle mode spin downs.

ELECTROMAGNETIC

.4 Volts/meter over a range

EMITTED

.07

VIBRATION

Gs

peak.

(MTBF):

(PM):

SUSCEPTIBILITY

of

20Hz to 20

The projected field The Quantum

Core TR-332 Issue #6, December 1997 predictions and represent that

Quantum

the drive.

Not required 50,000 cycles at ambient temperature

(minimum)

of

one power

MHz.

MTBF

is 625,000 hours.

MTBF

numbers represent Bell-

the

minimum

or

a customer would expect from

off

operation

MTBF

4.14

Retry recovered read Multi Unrecovered data errors Seek

DISK

Table 4-10 provides

read recovered

4

errors

ERRORS

the

error rates for the Quantum Fireball

Table 4-10

ERRORTYPE

1

errors

2

errors

3

1.

Retry recovered read errors are errors which require retries for data correction. Errors

corrected is disabled to meet this specification. Errors corrected correction are

2. Multi read recovered errors are those errors which require correction algorithm to be applied for data correction. This correction is typically applied only after the programmed retry count

by

ECC

on-the-fly are

not

considered recovered read errors.

Error

Rates

MAXIMUM

I event per I 09 bits read I event I event I

error

not

considered recovered read errors. Read on arrival

per per per

NUMBER

12

10

bits read

14

10

bits read

106 seeks

is

CR

OF

by

the thermal asperity

the

exhausted.

hard disk drives.

ERRORS

quadruple-burst error

4-10

Quantum

Fireball

CR

4.3/6.4/8.4/12.7

AT

Specifications

3. Unrecovered read errors are errors that are not correctable using

ECC

or

drive terminates retry reads either when a repeating error pattern occurs,

of

programmed limit for unsuccessful retries and the application

quadruple-burst

error correction.

4.

Seek errors occur when the actuator fails to reach (or remain) over the requested cylinder and the drive requires the execution

of

a full recalibration routine to locate

the requested cylinder.

Note: Error rates are for worst case temperature and voltage.

retries. The or

after the

Quantum Fireball

CR

4.3/6.4/8.4/12.7AT 4-11

Specifications

4-12 Quantum Fireball

CR

4.3/6.4/8.4/12.7

AT

Chapter

5

5.1

BASIC PRINCIPLES

This chapter describes the operation

drives' functional subsystems. rather than a detailed theory

QUANTUM

This section describes the drive mechanism. Section 5.2 describes The Quantum Fireball

as shown in Figure 5-1.

The head/disk assembly

are sealed under a metal cover. The

• Base casting

•

DC

• Disk stack assembly

• Headstack assembly

• Rotary positioner assembly

FIREBALL CR DRIVE

CR

hard disk drives consist

(HDA)

motor assembly

of

It

of

contains the mechanical subassemblies

Quantum Fireball

is

intended

operation.

HDA

consists

OF

as

a guide to

MECHANISM

CR

of

a mechanical assembly and a

of

the

OPERATION

4.3/6.4/8.4/12.7

the

operation

the

following components:

AT

hard disk

of

the drive,

drive electronics.

of

the

drive, which

PCB

• Automatic actuator lock

• Air filter

The drive is assembled in a Class-IOO clean room.

CAUTION:To ensure that the air

contamination, never remove seals. Tampering with

Quantum Fireball

in

the

HDA remains free

or

the

HDA

CR

4.3/6.4/8.4/12.7

of'

adjust its cover and

will

void your warranty.

AT

5-1

Basic Principles

of

Operation

Cover

U:-~"';"J.~

Disk

sta

Assembly

Head

staCk~

Assembly

(8

heads)

Automatic Actuator

t~i.diSkl\

e

~.

!

~:

EMSFle~"

Shield

..

"

.....

....---

6 Screwslholes

Spacer

(placed

between

each

disk)

".--:+---DC

~

Spindle Motor

Base

Casting

Assembly

Figure 5-1 Quantum Fireball

5-2 Quantum Fireball

CR

4.3/6.4/8.4/12.7AT

4.3/6.4/B.4/12.7AT Hard Disk Drive Exploded View

Basic Principles

of

Operation

5.1.1

5.1.2

5.1.3

Base Casting

A single-piece, e-coated, aluminum-alloy base casting provides a mounting surface for the drive mechanism

assembly. a seal between the base casting, and the metal cover that encloses the drive mechanism.

DC Motor

Integral with the base casting, the spindle motor

Disk

Stack

The disk stack assembly in

secured coating.

A carbon overcoat lubricates

head contact with the disk surface occurs only in the landing zone outside is

not

beyond the last cylinder

CYLINDER

CONTENTS

System

Data

Assembly

and

PCB.

The base casting also acts

To

provide a contamination-free environment for

as

the flange for the

the

HDA,

a gasket provides

Assembly

DC

that

drives

motor assembly

the

counter-clockwise rotation

is

a fixed-shaft, brushless of

the

disks.

Assemblies

the

Quantum Fireball

by

a disk clamp. The aluminum-alloy disks have a sputtered thin-film magnetic

the

disk surface. This prevents head and media wear due to

the

disk surface during head takeoff and landing. Head contact with

rotating

at

full speed. The landing zone is located at the inner diameter

of

the

data area.

Table

ZONE!

0

5-1

Cylinder Contents

NUMBER

OF

TRACKS PERTRACK

20

CR

hard disk drives consist

of

the

data area, when the disk

SECTORS

DATA

329

RATE

153

DC

of

disks

of

the disk,

motor

DC

1.

For user data, zone

15 14 13

12

II

10

9

8 7

6

5

4

3

2

I

15

is the innermost zone and zone 1 is the outermost zone.

829 829

829 829 829 829 829 829 829 829 829 829 829 829 895

250 266 285 298 316 329 342 354

361 380 381 391 399 404

406

118

125 133 139 148 153 159 166 168

In

178 183 186 188 189

Quantum Fireball

CR

4.3/6.4/8.4/12.7AT 5-3

Basic Principles

of

Operation

5.1.4

5.1.5

5.1.6

Headstack Assembly

The headstack assembly consists by insertion molding to form a rotor subassembly, bearings, and a flex circuit. Read/write heads mounted to spring-steel flexures are swage mounted onto the rotary positioner assembly arms.

The flex circuit exits the seals the gap. The flex circuit connects the headstack assembly to the circuit contains a read preamplifier/write driver Ie.

HDA

of

read/write heads, head arms, and coil joined together

between the base casting and

the

cover. A cover gasket

PCB.

The flex

Rotary Positioner Assembly

The rotary positioner, consists around the headstack mounting hub, and a bearing shaft. The single bi-polar magnet consists prevents the heads from being driven into

Current from the power amplifier induces a magnetic field in the voice coil. Fluctuations in the field around the permanent magnet cause the voice coil to move. The movement of

Automatic

To ensure data integrity and prevent damage during shipment, the drive uses a dedicated landing zone, an actuator magnetic retract, and Quantum's patented Airlock®. The Airlock holds the headstack in the landing zone whenever the disks are not rotating. It consists that

of

upper and lower permanent magnet plates, a rotary single-phase coil molded

of

two alternating poles and

the voice coil positions the heads over the requested cylinder.

Actuator Lock

of

an air vane mounted near the perimeter

restrains the actuator arm assembly.

or

rotary voice-coil actuator,

is

bonded to the magnet plate. A resilient crash stop

the

is

a Quantum-proprietary design

spindle

or

off the disk surface.

of

the disk stack, and a locking arm

that

DC

power

is

When an

airflow

disk rotation, the locking arm pivots away from the actuator arm, enabling the headstack to move out

electronic return mechanism automatically pulls the actuator into the landing zone,

where the magnetic actuator retract force holds it until the Airlock closes and latches

in place.

on

applied to the motor and the disk stack rotates, the rotation generates

the surface

of

the landing zone. When

of

the disk. As the flow

DC

of

air across the air vane increases with

power

is

removed from the motor,

an

it

5-4 Quantum Fireball

CR

4.3/6.4/8.4/12.7AT

5.1.7

Basic Principles

Air

Filtration

The

Quantum Fireball

The heads fly very close to the media surface. Therefore, it

CR

4.3/6.4/8.4/12.7

AT

hard disk drives are Winchester-type drives.

is

essential that the air circulating within the drive be kept free of particles. Quantum assembles the drive in a Class-100 purified air environment, then seals the drive with a metal cover. When the

is

drive internal

in use, the rotation

0.3 micron filter. The internal

pressure change

by

passing air through a

of

the disks forces the air inside of the drive through an

HDA

cavity pressure equalizes to the external

0.3

micron, carbon impregnated breather filter.

of

Operation

5.2 DRIVE

Advanced circuit (Very Large Scale Integration) design and the use of miniature surfacemounted devices and proprietary including the (PCBA).

Figure 5-2 contains a simplified block diagram drive electronics.

The only electrical component not on the

It

is possible to the read/write heads improves the signal-to-noise ratio. (including the

between the

HARD ASSEMBLY

PREAMP & WRITE DRIVER

I VOICE

t:INDLE

Figure 5-2 Quantum Fireball

RDXROY

WROATA

COIL

MOTOR

DISK

HOSEl.

ELECTRONICS

ATA

bus interface, to reside on a single printed circuit board assembly

on the flex circuit (inside

PreAmplifier and Write Driver

PCB,

the

rotary positioner assembly, and read/write heads.

PCB

RD

WRDATA

-RESET

-----

I I

I

I I I I I I I

VREFOUT

I I I I

SPINDLENCM

I

POWER

I : I

II

.1

•

VCMISPINDLE CONTROL

ASIC

CR

4.3/6.4/B.4/12.7AT

VLSI

components enable the drive electronics,

of

the sealed

DATA

11

CONTROLLERIDISK

READIWRITE

SERIAL AEF

SERIAL

ATA

INTERFACE

of

the Quantum Fireball

PCBA

is

the PreAmplifier and Write Driver Ie.

HDA).

Mounting the preamplifier

IC)

provides the electrical connection

ASIC

ROIWROATA

BUS

t

BUS

tl

CONTROLLER

-PCR

A

ASIC

eLK

BADORBOATAo

0-7

0-15

~~

r

-WE

DRAM

(2S6KX

16)

Hard Disk Drive Block Diagram

The

ATAIIO

CONTROl.

CR

hard disk

as

close

flex circuit

BUS

as

Quantum Fireball

CR

4.3/6.4/8.4/12.7AT 5-5

Basic Principles

of

Operation

S.2.1 Integrated J,JProcessor, Disk

Electronics

The llProcessor, Disk Controller, proprietary

ASIC

developed

by

To/From

Quantum,

Hos!

DRAWING

TO

BE

UPDATED

Controller

and

ATA

Interface electronics are contained in a

as

shown below in Figure 5-3.

DisI<

Controller,

and

Integrated

and

ATA

ItProcessor,

ATA

Interface

ASIC

HDA

5-6 Quantum Fireball

Figure 5·3 Block

CR

4.3/6.4/8.4/12.7AT

I

------------------------

Diagram

Basic Principles

of

Operation

5.2.1.1

5.2.1.2

5.2.1.3

The integrated pProcessor, Disk Controller, and

ATA

Interface Electronics have nine

functional modules (described below):

• pProcessor

• AID Converter (8-bit)

• Error Correction

•

Formatter

Code

(ECC)

Control

• Buffer Controller

• Servo Controller, including

PWM

• Serial Interface

•

ATA

Interface Controller

• Motor Controller

J,lProcessor

The pProcessor core provides local processor services to the drive electronics under program control. The Interface internally. It also manages the Read/Write Circuit), and the

AID

Converter

Interface

pProcessor manages the resources

Spindle/VCM driver externally.

of

the Disk Controller, and

ASIC

(Application Specific Integrated

The Analog to Digital converter (AID) receives multiplexed burst analog inputs from the Read/Write inputs) and convert it to a digital signal the

ASIC.

The

A/D

is

used to sample the demodulated position information (burst

Servo Controller uses

to

position the

actuator.

Error

Correction

The Error Correction circuit

that

organized

check bytes. The quadruple-burst error correction

Code

(ECC) Control

Code

(ECC)

Control block utilizes a Reed-Solomon encoder/decoder

is used for disk read/write operations.

as

32

ECC

(Error Correction

ECC

uses eight bits per symbol and four interleaves. This allows

Code)

bytes with four interleaves, and four cross-

of

at least 96, and as many as 128 bits in error.

It

uses a total

of

36 redundancy bytes

ATA

HDA

5.2.1.4

5.2.J.5

Formatter

The Formatter controls the operation To

initiate a disk operation, the J.lProcessor loads a set

(writable control store) register. Loading and manipulating the

of

the read and write channel portions

of

commands into the

WCS

is done through the

of

pProcessor Interface registers. The Formatter also directly drives the read and write gates

ASIC

and the R/W Preamplifier, as well as passing write data to the Precompensator

circuit in the Read/Write

ASIC.

(RG,

WG)

of

the Read/Write

Buffer Controller

The Buffer Controller supports a 512 Kbyte buffer, which is organized as 256 K x The 16-bit width implementation provides a

increased bandwidth allows the eliminating the need for a separate

pProcessor to have direct access

pProcessor

60

MB/s maximum buffer bandwidth. This

to

the

buffer,

RAM

Ie.

The Buffer Controller supports both drive and host address rollover and reloading, to

allow for buffer segmentation. Drive and host addresses may be separately loaded for automated read/write functions.

The Buffer Controller operates under the direction

Quantum Fireball

of

the J.lProcessor.

CR

4.3/6.4/8.4/12.7AT 5-7

the

WCS

16

ASIC.

bits.

Basic Principles

of

Operation

5.2.1.6

5.2.1.7

5.2.1.8

5.2.1.9

Servo

TA

ATA

Controller (including PWM)

The Servo Controller contains a

a Pulse Width Modulator (PWM).

the

to

extract

motion

and

operates

control

disk J.lProcessor, The actuator driver

Controller

of

the

actuator. The Servo Controller also decodes raw

the

current position information. The position information is read

is

used

to

generate

is

an analog

under

the

direction

Processor and ReadlWrite Interface

The

TA

processor captures byte

of

more

than

two bytes anywhere

or

static recording.

The Read/Write interface allows the

Read/Write chip which has a different controller interface.

Interface Controller

The ATA Interface Controller portion

and transfer management services for the

interface is accomplished

operations are controlled

by

the

Motor Controller

The Motor Controller controls

drive.

the

14-bit

Digital to Analog converter (D/A), in

The

PWM signal is

the

actuator

power

amplifier circuit external to the ASIC. The Servo

of

the

J.lProcessor.

number

the

the Buffer Controller module.

and

wedge

in

a track. These values are used for servo, diagnostics,

integrated J.lprocessor, disk controller

of

the

ASIC provides

the

ATA interface. ConfiguratLc

J.lController across

spindle

and

voice coil motor

output

control signal

number

to

in order to locate

data

the

MAD

the Actuator Driver to

that

is

handli:- "rol,

bus. Dat:. uiii1sfer

(VCM)

the

data

sent

to

work with

mechanism

from

the

TA

form

by PWM.

events

..

01

on

of

the the

of

the

5-8 Quantum Fireball

CR

4.3/6.4/8.4j12.7AT

Basic Principles

of

Operation

5.2.2

ReadlWrite ASIC

The Read/Write

Response

data rates up to 210 Mb/s. Programming is done through a fast 50 The controller ASIC

is a low power 3.3 Volts, single supply, (1.6 Watts at full power nominal

data rate), with selective power down capabilities

The Read/Write

• Pre-Compensator

• Variable Gain Amplifier

• Butterworth Filter

•

FIR

• Flash

• Viterbi Detector

•

ENDEC

• Servo Detector and Sample/Hold

• Clock Synthesizer

• PLL

• Serial Interface

•

TA

Detector

(EPR4)

Filter

AID

ASIC

shown in Figure

processor, a 16/17 Encoder-Decoder

and

data interface through a 8-bit wide data interface. The Read/Write

ASIC

comprises

(VGA)

Converter

5-4

integrates an Extended Class 4 Partial

12

main functional modules (described below):

(ENDEC),

«15mW

and a Servo Detector with

MHz

serial interface.

at

highest

at

power down mode).

Figure 5-4 Read/Write

Quantum Fireball

ASIC

Block Diagram

CR

4.3/6.4/8.4/12.7AT 5-9

Basic Principles

oj

Operation

5.2.2.1

5.2.2.2

5.2.2.3

5.2.2.4

5.2.2.5

5.2.2.6

5.2.2.7

Pre-Compensator

The pre-compensator introduces pre-compensation to the write data received from the sequencer module in the DelIA. The pre-compensated data Amplifier and written to the disk. Pre-compensation reduces the write interference from adjacent write bit.

Variable Gain Amplifier (VGA)

Digital and analog controlled

Butterworth

Continuous time data filter which can be programmed for each zone rate.

FIR

(Finite Impulse Response) Filter

Digitally controlled and programmable filter for partial response signal conditioning.

Flash AID Converter

Provides very high speed digitization

Viterbi

Decodes

ENDEC/QBlock

Provides 16/17 code conversion to and detection.

Filter

Detector

ADC

result into binary bit stream.

AGC

function with input attenuator for extended range.

of

the processed read signal.

NRZ.

Includes preamble and sync mark generation

is

then passed to the

R!W

Pre-

5.2.2.8

5.2.2.9

5.2.2.10

5.2.2.11

5.2.2.12

5.2.2.13

S.2.3

Servo

Clock

Detector

Peak detection with weighted averaging and multiple sample and hold

Synthesizer

Provides programmable frequencies for each zone data rate.

and Sample/Hold

of

servo bursts.

PLL

Provides digital read clock recovery.

Serial

ServoADC

TA

PreAmplifier and

Interface

High speed interface for digital control

Provides 9 bit analog to digital conversion

Detector

Detects thermal asperities' defective sectors and enables early thermal asperity recoveries.

Write

The PreAmplifier and Write Driver provides write driver and read pre-amplifier functions,

and R/W head selection. PreCompensator module in the Read/Write

the

heads in the form amplifies the low-amplitude differential voltages generated by the transmits them to the the

pController. The preamp also contains internal compensation for thermal asperity induced amplitude variation.

Driver

The

write driver receives precompensated write data from the

of

a corresponding alternating current. The read pre-amplifier

VGA

module in the Read/Write

of

all

internal blocks.

of

servo burst amplitude.

ASIC.

The write driver then sends this data to

ASIC.

R/W

Head select

heads, and

is

determined

by

5-10 Quantum Fireball

CR

4.3/6.4/8.4/12.7AT

Basic Principles

of

Operation

5.3

5.3.1

5.3.1.1

FIRMWARE

This section describes

• Disk caching

• Head and cylinder skewing

• Error detection

• Defect management

FEATURES

the

following firmware features:

and

correction

Disk Caching

The Quantum Fireball

418 K (approximate) disk cache, to enhance drive performance. This integrated feature is

user-programmable and can significantly improve system throughput. Read and

write caching can be enabled or disabled by using the

Adaptive Caching

The cache buffer for

more efficient use and write operations is dynamically allocated. The cache can be flexibly divided into several segments under program control. Each segment contains one cache entry.

A cache entry consists Adaptive segmentation allows the drive

of

stored data can be increased.

CR

4.3/6.4/S.4/12.7AT hard disk drives incorporate DisCache, a

the

Quantum Fireball

of

the

buffer's

of

the requested read data plus its corresponding prefetch data.

CR

RAM.

With this feature,

to

make optimum use

Set Configuration command.

drives features adaptive segmentation for

the

buffer space used for read

of

the

buffer. The amount

5.3.1.2

Read Cache

DisCache anticipates host-system requests for data and stores When the host requests a particular segment

strategy to "look ahead", and automatically store the subsequent high-speed than

Since typically 50 percent or more probability that subsequent data requested will be in the cache. This cached data can be retrieved in microseconds rather than milliseconds. substantial time savings during DisCache could save most rotational latency delays that dominate the typical disk transaction. For example, in a lK data transfer, these delays make up to

DisCache works transferring data requested by the host.

controller continues a read operation after the requested data has been transferred host system. This read operation terminates after a programmed amount data has been read into the cache segment.

The cache memory consists

data, which can be directly accessed by the host commands. of

cache memory. The unit 512 byte sector). Therefore, all accesses to the cache memory must sector size.

RAM.

the disk.

The

All

If

the host requests this subsequent data,

of

at

of

by

continuing to fill its cache memory with adjacent

memory functions as a group

non-read/write commands force emptying

least

the disk transaction time by eliminating

of

a 418 K (approximate)

of

data stored is the logical block (that is, a multiple

of

data, the caching feature uses a prefetch

all

disk requests are sequential, there is a high

As a result, DisCache can provide

half

of

all disk requests. In these instances,

90 percent

Unlike a noncaching controller, Quantum's disk

of

the elapsed time.

DRAM

by

means

of

segments with rollover points at the end

that

data

from

the

RAM

is accessed rather

the

data

buffer allocated

of

the

READ

be

in multiples

of

the cache:

for faster access.

the

seek and

after

of

subsequent

to

and

WRITE

disk into

to

the

hold

the

of

the

of

the

Quantum Fireball

CR

4.3/6.4/S.4/12.7AT 5-11

Basic Principles

of

Operation

5.3.1.3

5.3.1.4

Write

Cache

When a write command to be written in a

DRAM

is

cache buffer, and immediately sends a

to the host before the data

executed with write caching enabled, the drive stores the data

GOOD

STATUS

is

actually written to the disk. The host

is

then free to move on to other tasks, such as preparing data for the next data transfer, without having to wait for the drive to seek to the appropriate track,

is

While the host

preparing data for the next transfer, the drive immediately writes the cached data to the disk, usually completing the operation in less than GOOD

STATUS. only about 3 ms host for about

With WriteCache, a single-block, random write, for example, requires of

host time. Without WriteCache, the same operation would occupy the

20

ms.

or

rotate to the specified sector.

20

ms

after issuing

WriteCache allows data to be transferred in a continuous flow to the drive, rather as

individual blocks advantage with a

of

the ability to write blocks

1:

1 interleave. This means write cache and the head passes over the next sector the next block

of

data separated by disk access delays. This

of

data sequentially on a disk

as

the last byte

transferred, thus there

data

is

ready to

that

be

is

achieved by taking

that

of

data

is

transferred out

of

the disk, the first byte

is

no interruption or delay in

is

the data transfer process. The

WriteCache algorithm fills the cache buffer with new data from the host while

simultaneously transferring data to the disk

that

the host previously stored in the cache.

Performance Benefits

In a drive without DisCache, there

if

rotational latency, even

the disk actuator already is positioned at the desired cylinder.

is

a delay during sequential reads because

DisCache eliminates this rotational latency time (5.59 ms on average) when requestf'd data resides in the cache.

message

than

formatted

of

the

of

the

of

the

Moreover, the disk must often service requests from multiple processes in a multitasking

or

muitiuser environment.

In

these instances, while each process might request data sequentially, the disk drive must share time among all these processes. In most disk drives, the heads must move from one location to another. With

DisCache, even

if another process interrupts, the drive continues to access the data sequentially from its high-speed memory.

In

handling multiple processes, DisCache achieves its most impressive performance gains, saving both seek and latency time when desired data resides in the cache.

The cache can be flexibly divided into several segments under program control. Each

of

segment contains one cache entry. A cache entry consists

the requested read data pius

its corresponding prefetch data. The requested read data takes up a certain amount

the corresponding prefetch data can essentially occupy the rest

of

space in the cache segment. Hence,

of

the space within the

segment. The other factors determining prefetch size are the maximum and minimum

prefetch. The drive's prefetch algorithm dynamically controls the actual prefetch value based on the current demand, with the consideration

of

overhead to subsequent

commands.

5-12 Quantum Fireball

CR

4.3/6.4/8.4/12.7AT

Basic Principles

of

Operation

5.3.2

5.3.2.1

5.3.2.2

5.3.2.3

Head

Cylinder

Skewing

and

Cylinder

Head

and

drives minimize latency time and

cylinder skewing in the Quantum Fireball

Skewing

thus

increases

CR

data

throughput.

4.3/6.4/8.4/12.7 AT hard disk

Skewing

Head skewing reduces the latency time

to

heads of

and but

sequential head-switch time is well defined on

addresses can

time during a head switch. See Table 5-2.

access sequential data. A head skew is employed such

data

to

be accessed will be under

the

data

is

ready

to

be accessed. Thus, when sequential data is

on

a different disk surface, a head switch is needed

be

optimally positioned across track boundaries to minimize

that

the

read/write

results

when

head

the

Quantum Fireball

the

drive must switch read/write

once

but

Skewing

Cylinder skewing is also used to minimize the latency time associated

the

sector

of

the

drives,

to

minimize

with

In

the

ID-less environment, the drive's track

of

wedges instead

ATA interface contains a "Wedge Skew Register"

the

skew offset must now be calculated with every read/write operation. The firmware

will program

The integrated

the

wedge number in the

away

from

wedge

the to

read/write head. Therefore,

data

on

cylinder. Since single-cylinder seeks are well defined on

the

sector addresses can be optimally positioned across cylinder boundaries

the

latency time associated with a single-cylinder seek. See Table 5-2.

ID-Iess

the

IIprocessor, disk controller and ATA interface will

the

0,

index. For example,

then

if

logical sector

drive such

continue accessing data,

the

last head

of

the traditional sectors. The integrated IIprocessor, disk controller and

skew offset into this register every time

the

skew register

that

of

ID

calculator, effectively relocating

of

data

that

after a single-cylinder seek is performed, and

the

a cylinder, and

is

cylinder skew takes place between

if

without skew, sector 0

set

to

10, sector 0 will be found following wedge 10.

crosses a cylinder

sector

to

be

accessed is positioned directly

the

first sector

and

cylinder skewing will to

assist in

the

that

the

not

the

drive goes

the

is

on

the

a seek. Since

CR

drives,

with

boundary

of

data

on

the

Quantum Fireball

be

task

of

skewing, where

to

then "first" sector to

add this value

be found following

logical sector

same cylinder

the

sector

the

latency

a single-

is

when

the

last

the

first head

based in

a new track.

of

the

unit

to

track

5.3.2.4

Since

the

cylinder skew off-sets will fulfill the requirement for all recording zones.

Skew

Offsets

wedge-to-wedge time

Table

Head

Skew

Cylinder

Note: Nominal wedge-to-wedge time

stantaneous spindle variation

provide a safety margin.

Wedge offsets are rounded

Skew

is

constant

over

5-2 Skews Offsets

SWITCH

Quantum Fireball

TIME

2.16

ms

2.88

ms

of

102.88 !!s is used. Worst case

(±0.250f0)

to

the

closest whole number.

the

entire disk, a single set

WEDGE

is used while calculating

CR

4.3/6.4/8.4/12.7AT 5-13

OFFSET

21

28

in-

to

of

head

and

Basic Principles

of

Operation

S.3.2.S

5.3.3

Runtime

Calculation

Since the wedge-to-wedge time is constant over the entire disk, a single set

of

cylinder skew offsets will fulfill the requirement for all recording zones. The formula used

to compute the wedge skew for a given cylinder and head is: Wedge skew Where:

=

[C*

((#

of

heads -

C = Cylinder number

H

= Head number

TS

= Head Skew Offset

CS

Cylinder Skew Offset

1) * TS + CS)

+ H *

TS]

MOD

108

(wedges/track = 108)

Error

Detection

As disk drive areal densities increase, obtaining extremely low error rates requires a new

generation

and

Correction

of

sophisticated error correction codes. Quantum Fireball

CR

hard disk drive series implement 288-bit quadruple-burst Reed-Solomon error correction techniques to reduce the uncorrectable read block error rate to less

than

one bit in 1 x

10

14

bits read.

When errors occur, an automatic retry, a double-burst, and a more rigorous quadrupleburst correction algorithm enable the correction incorrect bytes each,

or

up to sixteen multiple random one-byte burst errors. In addition

of

any

sector with four bursts

to these advanced error correction capabilities, the drive uses an additional crosschecking code and algorithm to double check the main reduces the probability

of

a miscorrection.

ECC

correction. This greatly

head and

of

four

5-14 Quantum Fireball

CR

4.3/6.4/8.4/12.7AT

Basic Principles

of

Operation

5.3.3.1

1 2

d 1

Background Information

A sector on the Quantum Fireball

of

user data, followed by four cross-checking

check bytes (288 bits). The four cross-checking bytes are used

ECC

correction and reduce the probability one sector can be corrected degree

The drive does those errors

of

data integrity with no impact on the drive's performance.

not

that

are corrected on-the-fly. Errors corrected in this manner are invisible to

on

Error

Correction

CR

4.3/6.4/8.4/12.7AT drive is comprised

Code

and ECC On-the-Fly

(XC)

bytes

(32

of

miscorrection. Errors

bits), followed by 32

of

to

double check the main

of

up to 64 bits within

"on-the-fly," in real time as they occur, allowing a high

need to re-read a sector on the next disk revolution or apply

the host system.

When errors cannot be corrected on-the-fly, an automatic retry, and a more rigorous

quadruple-burst error correction algorithm enables the correction bursts

of

four incorrect bytes each (up to

16

contiguous bytes), or up to

of

any sector with four

16

multiple random one-byte burst errors. In addition to this error correction capability, the drive's implementation main

ECC

The

32

ECC cross-checking and is

first written.

3

4

of

an additional cross-checking code and algorithm double checks the

correction, and greatly decreases the likelihood

check bytes shown in Figure 5-5 are used

ECC

data is computed and appended to the user

5

512 513 516 517 518

d 512 xc 1 xc 2 ecc 1

to

of

miscorrection.

detect and correct errors. The

data

when the sector

512 bytes

ECC

for

548

512 data bytes

Figure 5-5

cross-check

Sector Data Field with

4

bytes

ECC

Check Bytes

32

ECC bytes

Quantum Fireball

CR

4.3/6.4/8.4/12.7AT 5-15

Basic Principles

of

Operation

To

obtain the within the sector interleave byte

1,

is

in interleave

ECC

check byte values, each byte (induding cross-checking and

is

interleaved into one

the second byte

4,

the fifth byte is in interleave

is

in interleave

of

four groups, where the first byte

2,

the third byte

1,

is

in interleave 3, the fourth

and so on,

ECC

bytes)

is

in

as

shown in Figure 5-6.

Interleave 2 Interleave 3

Interleave 4

~

Note:

ECC

interleaving

Figure 5-6

is

Byte

Interleaving

not the same as the sector interleaving that

is

done on the disk.

Each of the four interleaves is encoded with 8

at the end

The combination

of

the sector.

The

four cross checking bytes are derived from all 512 data bytes.

of

the interleaving, and the nature

bytes, resulting in the 32

of

the

ECC

formulas enable the drive

ECC

to know where the error occurs.

ECC

Because the

cross-checking bytes can be corrected. Due to the power and sophistication errors found within the

Each time a sector

of

ECC

set

check bytes follow the cross checking bytes, errors found within the

of

the code,

of

ECC

check bytes can also be corrected.

data

is

read, the Quantum Fireball

CR

drives will generate a new

check bytes and cross-checking bytes from the user data. These new check bytes are compared to the ones originally written to the disk. The difference between the newly computed and original check bytes

is

reflected in a set of

32

syndromes and three

cross checking syndromes, which correspond to the number of check bytes. If all the syndrome values equal zero, and cx syndrome value equals 0 or

no

with

errors, and the sector

is

transferred to the host system. If any

OFF,

the data was read

of

the syndromes do not equal zero, an error has occurred. The type of correction the drive applies depends on the nature and the extent of the error.

bytes

ECC

High speed on-the-fly error correction saves several milliseconds double- burst error, because there sector under

Correction of Single-,

Single-burst errors may have up to four erroneous bytes provided that each of the four bytes occur in a different interleave.

The Quantum Fireball

the-fly as well. Double-burst errors can be simply viewed as two spans one sector. More specifically, correctable double-burst errors must have two erroneous bytes per interleave.

The drive's Reed-Solomon

that the error consists

5-16 Quantum Fireball

the

head for re-reading.

or

Double-Burst Errors On-the-Fly

CR

of

two or fewer bytes residing in each

CR

4.3/6.4/8.4/12.7AT

on

is

no need to wait for a disk revolution to bring the

(32

bits) within a sector,

each single-, or

drives have the capability to correct double-burst errors on-

of

errors within

or

fewer

ECC

corrects double-burst errors

up

to

64

bits long, (provided

of

the interleaves).

Basic Principles

Double-Burst Error Examples

In the example shown in Figure 5-7

more than two erroneous bytes per interleave.

The other two 64-bit errors, shown in Figure 5-7 A and

more than two error bytes

Note: Any 57-bit error burst can be corrected on-the-fly using double-

burst error correction because no more than two bytes can occupy each interleave.

of

C,

the 58-bit error

the entire error reside

is

un correctable since it occupies

B,

are correctable because no

in

anyone

of

the interleaves.

of

Operation

Byte 1

A ~

••

,...,.-~----.-~

Byte 1

r---r-

__

-r-

BD···

Byte 1

C

~

•••

~----L--::...--r+--->::-~~'-----l.----'----=----'--~...I..-...,;;~--:...---+r--=---»

1 bit 1 bit

Figure 5-7

CORREC

__

-r-_C_O_R.,.R_E_C_T_A_BT"L_E_(O_n_-_thT"e_-F_ly_>_r--

Correctable

...

T....,A,...B_L_E_....,....

UNCORRECTABLE

and

Uncorrectable

__

-r-

__

Double-Burst

-r-

__

r----r--7

Errors

-r-"""'7'

Byte 526

••

1]

Byte 526

..

1]

Quantum Fireball

CR

4.3/6.4/8.4/12.7AT 5-17

Basic Principles

Correction of Quadruple-Burst Errors

of

Operation

Through sophisticated algorithms, Quantum Fireball the capability to correct quadruple-burst errors, even though the probability occurrence

is

low. Quadruple-burst errors can be simply viewed

CR

4.3/6.4/8.4/12.7AT drives have of

as

four spans within one sector. More specifically, correctable quadruple-burst errors must have four or

fewer erroneous bytes per interleave, and will not

ECC

The drive's Reed-Solomon

that

(provided If

the quadruple-burst correction

the error consists

corrects quadruple-burst errors up to

of

four

or

fewer bytes residing in each

is

successful, the data from the sector can be written to

be

corrected on-the-fly.

128

bits long,

of

the interleaves).

a spare sector, and the logical address will be mapped to the new physical location.

Quadruple-Burst Error Examples

In the example shown in Figure 5-8

C,

the 120-bit error

is

un correctable since it occupies

more than four erroneous bytes per interleave.

The other two

12S-bit errors, shown in Figure 5-8 A and

more than four error bytes

of

the entire error reside in

B,

are correctable because no

anyone

of

the interleaves.

Note: Any 121-bit error burst can be corrected using quadruple-burst er-

ror correction because no more than four bytes can occupy each interleave.

.

their

of

errors

UNCORRECTABLE

1

bR

Figure 5-8

Correctable

and

Uncorrectable

Quadruple-Burst

Errors

1 bit

5-18 Quantum Fireball

CR

4.3/6.4/8.4/12.7AT

Basic Principles

of

Operation

Multiple Random

The drive's incorrect bytes follow the guidelines for correctable quadruple-burst errors. of

multiple random errors can be corrected on-the-fly, provided follow the guidelines for correctable double-burst errors. random errors can be corrected on-the-fly if two bytes per interleave contains an error.

If more than four bytes

Figure 5-9 shows an example (128 bits). This random burst error each interleave are in error.

INTERLEAVE

I

~

1

I

5

I I

9

I

•

• •

•

..-r-1

85

I

89

I

93

I

~

I

I I I

• • •

•

• • •

Burst

ECC

can correct up to

INTERLEAVE

I

10

I

L

r:::=1

86

I

90

I

94

<::::::

Errors

128

in

anyone

2 6

interleave are in error, the sector cannot be corrected.

of

a correctable random burst error consisting

is

correctable because no more

2

I I

:;oJ

•

• •

I

I I

I 1

J

• • •

bits

of

INTERLEAVE

I

L

~

I

~

multiple random errors, provided

that

Up

to 64 bits

than

3

I

7

I

11

I

;;:::;

• •

•

-,

87

91 95

I I

I 1 I I

Up

the incorrect bytes

of

multiple

of

four bytes within

INTERLEAVE

4

8

12

I

c=;::;

•

..-r-1

88 92

96

~

•

that

the

to 64 bits

16 bytes

4

I

I I

I

~

505

I

509

I

513XC

I

~

c::J

(

508 512

516XC

c:::::::

•

507 511

XC

fJ

I I I

J

Burst

Errors

CR

4.3/6.4/8.4/12.7AT 5-19

r:::=1

I 1 I 1

I 1

•

• • • •

•

BYTE

CONTAINING

Figure

506 510

514XC

c::::::::::=cJ

AN

ERROR

Twelve Correctable Random

5·9

I I

I

• • •

• •

Quantum Fireball

r

I

1515

c:::::::

~

I I I

J

Basic Principles

of

Operation

5.3.3.2

ECC Error Handling

When a data error occurs, the Quantum Fireball

is

error on-the-fly, the error is corrected and the

If data correctly without applying the triple-, invoking the complex triple-, to recover from an error prevents invoking correction on non-repeatable errors. Each time a sector in error

read a set and xc syndrome value equals to sector an error has occurred, the syndrome values are retained, and another re-read

Note: Non-repeatable errors are usually related to the signal to noise ratio

When the sets syndrome has been achieved. This event automatic read reallocation correction feature has been enabled and a stable syndrome has been achieved, triple-, or quadruple-burst the host system (e.g., corrected data, etc.).

Note: These features can be enabled

correctable on-the-fly. This process takes about 200

data

the data

is

not correctable on-the-fly, the sector

or

quadruple-burst

by

attempting to re-read the data correctly. This strategy

of

ECC

syndromes

is

transferred to the host system.

of

the system. They are not due to media defects.

of

syndromes from two consecutive re-reads are the same, a stable

ECC

correction

Configuration quadruple-burst correction before all the automatic reallocation

of

the re-reads have been exhausted. The

is

computed.

0

or

early correction features have been enabled. If the early

is

applied, and the appropriate message

command. The

if

of

OFF,

If

any

may

or

EEC

a stable syndrome has been achieved

defective sectors.

CR

hard disk drives check to see

Jls.

If

the error

is

transferred to the host system.

is

re-read in an attempt to read the

or

quadruple-burst

ECC

algorithm, the drive

If

all

of

the

ECC

the data was read with no errors, and the

of

the syndrome values do not equal zero,

be significant depending on whether the

disabled through the

bit enables early

ECC

syndrome values equal zero,

ATA

ECC

triple-, or

ARR

bit enables

is

correctable

correction. Before

will

always try

is

transferred to

Set

if

the

is

re-

invoked.

5.3.4

If

the automatic read reallocation feature is enabled, the drive, when encountering triple-, set in the

Note: The Quantum Fireball

Defect

The Quantum Fireball

media

of

the defective sector are assigned logical block addresses such that a sequential ordering

of

to eliminate slow data transfer

cylinder. If

sparing technique replaced with the nearest available pool

or

quadruple-burst errors, will attempt to re-read up to 8 times the retry count

AT

Configuration bytes.

CR

4.3/6.4/8.4/12.7AT drives are shipped from the factory with the automatic read reallocation feature enabled so that new defective sectors can be easily and automatically reallocated for the average

AT

end user.

any

Management

CR

drives allocate 32 sectors per 65,504 sectors. In the factory, the

is

scanned for defects.

the sector logical blocks

more than 32 sectors are found defective within 65,504 sectors, the above inline

is

added to the drive's defect list. Sectors located

is

maintained. This inline sparing technique

is

applied to the

If

a sector on a cylinder

that

would result from a single defective sector on a

32

sectors only. The remaining defective sectors are

of

spares.

is

found to be defective,

phYSically

is

employed in an attempt

the

subsequent to

address

5-20 Quantum Fireball

CR

4.3/6.4/8.4/12.7AT

Basic Principles

of

Operation

Defects that occur found in the field, the sector factoxy for those sectors that are found defective after the first 32 spares per pool spares; that is, inline sparing is

reallocated to

Sectors are considered to contain grown defects must be applied to recover the data. If this algorithm stored in the newly allocated sector. If the algorithm

in

the field are known as grown defects. If such a defective sector

an

available spare sector on a nearby available pool

is

reallocated according to the same algorithm used at the

is

not performed on these grown defects. Instead, the sector

of

spares.

if

the quadruple-burst

is

successful, the corrected data

is

not successful, a pending defect

ECC

is

of

algorithm

is

will be added to the defect list. Any subsequent read to the original logical block will

if

return an error

the read

will result in 4 write/read/verifies of the suspect location. If any

is

not successful. A host command to over-write

of

the 4 write/read/

the

location

verifies fail, the new data will be written to a spare sector, and the original location will be

added to the permanent defect list. If all 4 write/read/verifies pass, data will be written

be

to the location, and the pending defect will

removed from the list.

Quantum Fireball

CR

4.3/6.4/8.4/12.7AT 5-21

Basic Principles

of

Operation

5-22 Quantum Fireball

CR

4.3/6.4/8.4/12.7AT

Chapter 6

ATA

6.1

6.2

BUS

This chapter describes the interface between Quantum Fireball

hard disk drives and the

the drive are listed, as well

interface.

INTERFACE

ATA

bus. The commands

as

the electrical and mechanical characteristics

AND

ATA

that

COMMANDS

CR

4.3/6.4/8.4/12.7AT

are issued from the host to control

of

the

INTRODUCTION

Quantum Fireball bus interface, and are compatible with systems on the motherboard. It may also be used with a third-party adapter board in systems that do not have a built-in expansion slot in an AT-compatible computer. A cable connects the drive to the adapter board.

SOFTWARE

The Quantum Fireball

program residing in an directly with status information from the drive.

CR

4.3/6.4/8.4/12.7AT hard disk drives use the standard

ATA

adapter. The adapter board plugs into a standard 16-bit

that

provide an

ATA

IBM

interface connector

INTERFACE

CR

drives are controlled by the Basic Input/Output System

IBM

PC

AT,

or

IBM

the

drive's built-in controller. It issues commands to the drive and receives

compatible

PC.

The

BIOS

communicates

PC

(BIOS)

ATA

6.3

6.3.1

MECHANICAL

DESCRIPTION

Drive Cable and Connector

The hard disk drive connects to the host computer 40-pin connector

host computer. a host expansion slot,

that

At

plugs into the drive, and a 40-pin connector that plugs into the

the host end, the cable plugs into either an adapter board residing in

or

an on-board

ATA

Quantum Fireball

adapter.

by

means

CR

4.3/6.4/8.4/12.7

of

a cable. This cable has a

AT

6-1

ATA

Bus Interface and ATA Commands

6.4

6.4.1

6.4.1.1

6.4.1.2

ELECTRICAL ATA

Bus

A 40-pin

interface between the drive and a host contains bus drivers and receivers compatible with the standard interface signals extended

The

ATA the host system, and decodes addresses on the host address bus. The Command Block Registers on the drive accept commands from the host system

Note: Some host systems

INTERFACE

Interface

ATA

interface connector on the motherboard

that

uses an

DS-D

15,

INTRQ,

I/O-bus connector.

interface buffers data and controls signals between the drive and

issues an interrupt. In such cases, the interrupt may not be acknowledged. configure a jumper on interrupts to be controlled by motherboard or adapter board manual carefully to find out do

this.

To

and

IOCS

16-

require the

do

not

read the Status Register after the drive

overcome this problem, you may have to

the

motherboard or adapter board to allow

the

drive's interrupt logic. Read your

or

an adapter board provides an

IBM

PC

AT

bus. The

AT

bus. The AT-bus

ATA

adapter board to have an

BIOS.

how

ATA

the

to

Electrical Characteristics

All signals are transistor-transistor logic volts and less

than

5.25 volts; and logic a greater than 0.0 volts and less

(TTL)

compatible-with logic 1 greater

than

Drive Signals

The drive connector ATA

adapter in the host computer. J

rows of connecting cable is a

flat ribbon cable with a maximum length

20

pins on lOa-mil centers.

(Jl,

section

40-conductor (SO-conductor for

C)

connects the drive to an adapter board

1,

section C

Jl

has been keyed by removing pin 20. The

of

IS inches.

is

a 40-pin shrouded connector with two

UDMA

or

modes 3 and 4 operation)

interface

AT

bus

than

2.0

O.S

volts.

onboard

of

Table

6-1

use all

ofthe

the drive connector

Note: In Table 6-1, the following conventions apply:

6-2 Quantum Fireball

describes the signals on

signals provided by

(Jl,

section

A minus sign follows the name

active low. Direction IN OUT I/O

CR

(DIR)

is

in

indicates input to the drive.

indicates output from the drive.

indicates that the signal is bidirectionaL

4.3/6.4/8.4/12.7AT

the

ATA

C)

and

reference

drive connector (JI, section

bus. Table 6-4 shows the relationship between

the

ATA

of

to

the drive.

bus.

any signal

that

is asserted as

C).

The drive does

not

ATA

Bus Interface and

ATA

Commands

SIGNAL

Reset

Ground

Data Bus

Table 6·1 Drive Connector Pin Assignments (Jl, Section

NAME

RESET-

Ground

DDO DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8

DD9 DDlO DDll DD12 DD13 DD14

DD15

DIR

IN

- 2

I/O

Drive reset signal from the host system, inverted on

1

the adapter board or motherboard. This signal from the host system will be asserted beginning with the application asserted until at least stabilized within tolerance during power on. It will be

negated thereafter unless some event requires device(s) be reset following power on. ATA

devices will not recognize a signal assertion

shorter than

respond to any signal assertion greater than

and will recognize a signal equal to or greater ].ls. The drive has a

Ground between the host system and the drive. An 8/16-bit, bidirectional data bus between the host

3-18

and the drive.

as

registers and 17 15

13

11

9

7 5 3 4

6

8 10 12

14 16 18

DESCRIPTION

25

20 ns

as

a valid reset signal. Devices may

lOill

pull-up resistor on this signal.

DO-D7

are used for 8-bit transfers, such

ECC

bytes.

].ls

after voltage levels have

Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5

Bit 6 Bit 7 Bit 8 Bit 9

10

Bit Bit

11

Bit

12

Bit

13 Bit 14 Bit

15

C)

of

power, and held

that

20 ns,

than

the

25

Ground

Keypin

DMA

Ground

Request

Ground KEYPIN DMARQ

Ground

-

OUT

-

19

Ground between the host system and the drive.

20

Pin removed to key the interface connector. Asserted by the drive when it

21

data with the host. The direction determined by DIOW- and DIOR-. conjunction with pull-down resistor on this signal.

22

Ground between the host system and the drive.

Quantum Fireball

DMACK-.

CR

4.3/6.4/8.4/12.7AT 6-3

is

ready to exchange

of

DMARQ

The drive has a

the data transfer

is used in

lOill

is

ATA

Bus Inteiface and

ATA

Commands

Table

SIGNAL

I/O

Write

Ground

I/O

Read

Ground

I/O

Channel Ready

Cable Select

DMA

Acknowledge DACKl-

Ground

Interrupt Request

6-1

Drive Connector Pin Assignments (Jl, Section

NAME

mow-

Ground

mOR-

Ground

IORDY

Ground

INTRQ

DIR

IN

-

IN

-

OlIT

-

IN

-

OlIT

23

The rising edge for data transfers from DDO-DD

24

Ground between the host system and the drive.

25 The rising edge

data transfers from a register or the drive's data port

to the host

rising edge

26 Ground between the host system and the drive.

27

When the drive is not ready transfer request, the low to extend

register read

deasserted, it is in a high-impedance state and it is host's responsibility to pull this signal up to a high level (if necessary).

28 This

be configured as drive 0 when the signal

(grounded), and as drive 1 when the signal The drive has a

29 Used by the host to respond to the drive's

signal.

available for the host.

30 Ground between the host system and the drive. 31

An interrupt to the host system. Asserted only when the drive microprocessor has a pending interrupt, the

drive Device

is

impedance state, regardless

of

15)

to a register

data

of

or

is

a signal from

DMARQ

is

selected, and the host clears

Control Register. When nlEN

not

selected, this output signal

a pending interrupt.

C)

(Continued)

DESCRIPTION

ofthis

write strobe provides a clock the

host data bus

or

to

the drive's data port.

of

this read strobe provides a clock for

bus

(DDO-DD7

DIOR- latches data at the host.

IORDY

the

host transfer cycle

write access. When

the

lOill

pull-up resistor on this signal.

signals

that

or

to

respond to a data

signal

host

that

there

ofthe

(DDO-DD7

DDO-DD1S).

is

asserted active

of

any host

IORDY

allows the drive

is

presence or absence

is

0

is

DMARQ

more data

nlEN

in the

is

a 1 or the drive

in a high-

or

The

the

to

1 (high).

16-Bit

I/O

Drive Address Bus

6-4 Quantum Fireball

IOCSl6-

OlIT

CR

4.3/6.4/8.4/12.7AT

INTRQ

setting

when the host writes to the Command Register

reads the Status Register.

When data is being transferred in programmed

(PIO)

data block transfer. Exception:

executes:

BUFFER,

32 An open-collector output signal. Indicates to the host

system

is deasserted

of

SRST

mode,

INTRQ

at

the

beginning

occurs when any

and that the drive is ready to send or receive a word. When transferring data in is

not IOCS16- is asserted, DO-DIS are used for 16-bit data transfers.

A 3-bit, binary-coded address supplied by the host when accessing a register or the drive's data port.

FORMAT

or

WRITE

that

the I6-bit data port has been addressed,

asserted,

by

an

in the Device Control Register,

is asserted

of

the

of

TRACK,

LONG.

DO-D7

assertion

first data block transfer

the

following commands

Write Sector,

are used for 8-bit transfers;

or

RESET

at

the beginning

INTRQ

is

PIO

mode, ifIOCS

not asserted

WRITE

-,

the

or

I/O

of

that

I6-bit

each

16-

if

Table

6-1

Drive Connector Pin Assignments (Jl, Section

ATA

Bus Interface and

C)

ATA

(Continued)

Commands

SIGNAL

NAME

Bit 1 DAI Bit 0 Bit 2

DAO DA2

Passed Diagnostics PDIAG-

DIR

IN

I/O

DESCRIPTION

33 35 36

Drive 0 (Master) monitors this Drive 1 (Slave) open-

34

collector output signal, which indicates the result

or

diagnostics command

reset. The drive has a

pull-up resistor on this signal.

Following the receipt

or

reset,

RESET-drive 1 negates PDIAG- within 1

PDIAG- indicates to drive 0

of

a power-on reset, software

that

drive 1 (BSY=I). Then, drive 1 asserts PDIAG- within 30 seconds, indicating (BSY

=0)

and can provide status information. Following the assertion to accept commands until drive 1 that

is, until the reset procedure for drive 1

that

drive 1

of

PDIAG-, drive 1

is

no longer busy

is

ready complete. Following the receipt

DIAGNOSTIC within 1

command, drive 1 negates PDIAG-

ms,

indicating to drive 0 that it

of

a valid

EXECUTE

has not yet passed its internal diagnostics. If drive 1 present, drive 0 waits for drive 1 to assert PDIAG- for up to 5 seconds after the receipt DRIVE

DIAGNOSTIC

command. Since PDIAG-

of

a valid

indicates that drive 1 has passed its internal

is

diagnostics and clears

BSY

prior to asserting PDIAG-.

ready to provide status, drive 1

10K

is

busy

is

unable

(DRDY = 1)-

is

DRNE

is

busy and

EXECUTE

of

ms.

a

is

Chip

Select 0 CStFX-

Chip

Select 1

CS3FX-

IN

If

drive t fails to respond during reset initialization,

0 reports its own status after completing its

drive internal diagnostics. Drive commands until drive until the reset procedure for drive 0

37

Chip-select signal decoded from the host address bus.

0

is

unable to accept

is

ready

(DRDY = I)-that

is

complete.

Used to select the host-accessible Command Block Registers.

Chip select signal decoded from the host address bus.

38

Used to select the host-accessible Control Block Registers.

CR

Quantum Fireball

4.3/6.4/8.4/12.7

AT

is,

6-5

ATA

Bus Interface and

ATA

Commands

Table

SIGNAL

Drive Active/Slave

6-1

Drive Connector Pin Assignments (Jl, Section

NAME

DASP-

DIR

I/O

39

Present activity

Ground Ground

- 40

Series termination resistors are required at both the host and the device for operation in any

of

the

termination

Ultra ATA/66 modes. Table 6-2 describes recommended values for series

at

the host and the device.

Table 6-2 Series Termination

C)

(Continued)

DESCRIPTION

A time-multiplexed signal

or

that drive 1

initialization, DASP-

ms

to indicate that drive 1 is present. If drive 1 present, drive the drive-activity

0 asserts DASP- after 450 ms to light

LED.

An open-collector output signal, DASP-

following the receipt or after

DA5P-

the

drive is ready, whichever occurs first. Once

is

deasserted, either hard drive can assert

DASP- to light the drive-activity

a

10K

pull-up resistor on this signal.

If

an external drive-activity

that

indicates either drive

is

present. During power-on

is

asserted by drive 1 within 400

is

deasserted

of

a valid command by drive 1

LED.

Each drive has

LED

is

used

to

monitor

is

not

this signal, an external resistor must be connected in series between the signal and a to limit

the

current to 24 rnA maximum.

+5

volt supply in order

Ground between the host system and the drive.

for

Ultra

ATA/66

SIGNAL

DIOR-/HDMARDY -/HSTROBE

DIOW-/STOP

CSO-,

C51-

DAO,

DAl,

DA2

DMACK-

DD

15 through

DDO

DMARQ

INTRQ

IORDY/DDMARDY

-/D5TROBE

Note: Only those signals requiring termination are listed

a signal

an

Ultra ATA/66 mode.

in

HOST

TERMINATION

33.Q 82.Q

33.Q

33.Q 82.Q

33.Q 33.Q

82.Q 33.Q

is

not listed, series termination

DEVICE

TERMINATION

82.Q

in

is

not required for operation

this table. If

6-6 Quantum Fireball

CR

4.3/6.4/8.4/12.7AT

ATA

Bus Interface and ATA Commands

6.4.1.3

AT

A Bus Signals

See Table 6-4 for

Signal Line Definitions

Several existing

the

relationship between

(Ultra

ATA

signal lines are redefined during

ATA/66)

the

drive signals

and

the

ATA

bus.

the

Ultra ATA/66 protocol to

provide new functions. These lines change from old to new definitions the moment the

host decides to allow a

chosen via Set Features. The drive becomes aware

DMA

burst,

ifthe

Ultra ATA/66 transfer mode was previously

of

this change upon assertion

-DMACK line. These lines revert back to their original definitions upon the deassertion

of

-DMACK at

NEW

the

termination

Table

DEFINITION

DMARQ

-DMACK

of

the

DMA

burst.

6-3 Signal Line Definitions

OLD

DEFINITION

=DMARQ

= -DMACK

(These two signals remain unchanged to ensure backward compatibility with

PIO

modes)

=

-DMARDY

STROBE

STOP

-CBUD

IORDY

= -DIOR

=

IORDY

on

WRITE

on

READ

on

WRITE

on

READ

=-DIOW

-PDIAG

commands

ofthe

Quantum Fireball

CR

4.3/6.4/8.4/12.7AT 6-7

ATA

Bus Interface and

ATA

Commands

6.4.2

6.4.2.1

SYMBOL

Host

Programmed

to

t1

t2

t2i DIOW-/DIOR- Negated Pulsewidth

t3 t4 t5

t5a

t6 DIOR- Data Hold min

t6z DIOR- Data Tristate

t7 Address Valid to t8

t9 DIOW-/DIOR- to Address Valid Hold tA tB

tR

Interface

Timing

110 (PIO) Transfer Mode

The

PIO

host interface timing shown in Table 6-5 is in reference to signals and 2.0 volts. All times are in nanoseconds, unless otherwise noted. Figure 6-1 provides a timing diagram.

Table

DESCRIPTION

Cycle Time

Address Valid

DIOW-/DIOR- Pulsewidth (8-

mOW-Data Setup min mowDIOR- Data Setup

DIOR-

Address Valid to I05C16- Deassertion

IORDY

Read Data Valid

(if

lORDY

is

6-5 PIO Host Interface Timing

to

DIOW-/DIOR-Setup

or

16-bitl

Data Hold

to

Data Valid

IOCS

16-

Assertion

Setup Time

Pulse Width

to

initially low after tAl

IORDY

active

MINIMAX

min

min 25 min 70 70 min 25

min 10 10 min 20

max

max 30 max max

min min max 1250 1250

min 0 0

MODE 4

(local bus)

1

FIREBALLCR

120

20 20

-

5 5

N/A N/A

N/A

10 35

at

0.8 volts

QUANTUM

AT

120

25

20

-

30

N/A

10

35

1. ATA Mode 4 timing is listed for reference only.

Quantum Fireball

CR

4.3/6.4/8.4/12.7AT 6-9

ATA

Bus Interface and

ATA

Commands

Address

OIOWOIOR-

IOROY

6.4.2.2

t 1

__

*".----

Multiword

DMA

t 2

---

Figure

6-1

Transfer Mode

The multiword DMA host interface

at

O.B

volts

and

2 provides a

2.0 volts. All times are in nanoseconds, unless otherwise noted. Figure

timing

diagram.

to

....

+II1II1---

~------t2i

PIO Inteiface Timing

t 9

timing

shown in Table

------~

6-6

is in reference

to

signals

6-

Table 6-6 Multiword

SYMBOL

to

tD DIOR-/DIOW- Pulsewidth min

Cycle

tE tF

tFz

tG

tH

tl

tJ DIOR-/DIOW-

tK tL

DMACK

DIOR-/DIOW- Negated Pulsewidth

DIOR-/DIOW-

tz

1.

ATA Mode 2

2.

The Quantum Fireball

3. Symbol

tz

only

DESCRIPTION

Time

DIOR-

to

Data Valid

DIOR- Data Hold

DIOR- Data Tristate"

DIOW- Data Setup

DIOW-

DMACK-

timing

applies

Data

to

DIOR-/DIOW- Setup min

to

DMACK- Hold min

to

DMARQ

Data

is listed for reference only.

CR

4.3/6.4/B.4/12.7AT drive tristates after each word transferred.

on

the

last tristate

Hold

Tristate':!

DMA

Delay

at

the

Host Interface Timing

MINIMAX

min

max

min

max

min min

min max max

end

of

MODE

(local bus)

120 120

70

20 20 20

10 10

25 35 35 25 25

a multiword

- -

5

0 0 5

DMA

21

transfer

QUANTUM

FIREBALL

AT

70

5

20

5

25

cycle.

CR

6-10

Quantum Fireball

CR

4.3/6.4/B.4/12.7AT

OMARQ

OMACK-

OIOWOIOR-

Read

000-15

Write

ODO-15

rr_tG

_____

to

_

ATA

Bus Inteiface and

"--tL--I~

ATA

Commands

~~----------

Figure 6-2 Multiword DMA Bus lnteiface Timing

NAME

Tcyc

T2cyc

Tds

Tdh

Tdvs 70

Tdvh 6

Tfs

Tli 0 150

MODE

(ns) (ns)

Min Max Min Max Min

114

235 156

15

5 5

0 230

Table 6-7

0

Ultra

DMA Data Transfer Timing Requirements

MODEl

75

10

48 34

6

0 200

0 150

MODE2

55

117

7 7 5 5

6 6

0

MODE

(ns) (ns) (ns)

Max Min

170

0 150 0 100 0 100

39

86

20

0

Max

130

--------~

3

MODE

Min Max

25

57

5 5 6 Data ".JHd setup time (at

6 Data valid hold time (at

0

4

120

COMMENTS

Cycle time (from edge

to

STROBE

Two cycle time (from rising

edge

to

next rising edge or from falling edge to next falling edge

Data setup time (at receiver)

hold time (at receiver)

Data

sender) - time from data bus being valid until STROBE

sender) - time from

edge until data may invalid

First

STROBE device to send first STROBE.

Limited interlock time time allowed between an

action

or

host

following action by the other agent

of

~.'"

edge

by

one agent (either

device) and the

STROBE

edge)

STROBE)

STROBE

go

- time for

Quantum Fireball

CR

4.3/6.4/8.4/12.7

AT

6-11

ATA

Bus Interface and

ATA

Commands

NAME

Tmli

Tui Taz

Tzah Tzad

Tenv

Tsr

Trfs

Trp

Tiordyz

Tziordy

Tack

Tss

MOOED

(n5) (n5) (n5) (n5) (n5)

Min

Max

20

0 0 0

20

0 0 0

20

160

0 0 0

20

50

MODE

Min

Max

20

10

20

70

20

70

50 30

75

60

125

20

20 20

20

50

I

MODE

Min

20

20 20

20

100

20

50

2

MODE

Min

Max

20

0 0

10

0 0

70

20

NA

50

100 100

0 0

20 20

3

Max

10

55 55

NA

60 60 Ready-to-final-STROBE

20

50 50

MODE4

Min

Max

20

COMMENTS

Interlock time with

minimum Unlimited interlock time

Maximum time allowed for

10

outputs to release

20 Minimum delay time

required for output drivers

turning

on

(from released

state)

Envelope time (all control

signal transitions are within

the

DMACK

envelope by

this much time)

NA

STROBE

to

DMARDYresponse time to ensure the synchronous pause case (when the receiver is pausing)

time (this long after receiving

DMARDYnegation, no more edges may be sent)

Ready-to-pause

time-time until a receiver may assume that the sender has paused

of

after negation

20

Pull-up time before allowing

IORDY

DMARDY-

to be

released Minimum time device shall

wait before driving Setup and hold times before

assertion and negation DMACK-

Time from

STOP

STROBE

assertion (when the

sender is stopping)

STROBE

IORDY

of

edge to

6-12 Quantum Fireball

CR

4.3/6.4/8.4/12.7AT

ATA

Notes:

1. The timing parameters Tui and

interlocks,

that

is, one agent (either host or device)

Tli

indicate device-to-host

respond with a signal on the bus before proceeding.

Tli

is

or one which has no maximum time value.

a limited time-out, or one which

has a defined maximum.

2.

All

timing parameters are measured at the connector parameter applies. For example, the sender shall stop toggling after the negation measurements are taken

All

timing measurement switching points

3. be taken at

1.5V.

of

DMARDY-.

at

Both

STROBE

the connector

and

of

the sender.

(low

to high and high to

Bus interface and ATA Commands

or

host-to-device

is

waiting for the other agent to

Tui

is

an unlimited interlock,

of

the device to which the

DMARDY-

STROBE

timing

low)

Trfs ns

are to

Quantum Fireball

CR

4.3/6.4/8.4/12.7AT 6-13

ATA

Bus Interface and

ATA

Commands

Figures 6-3 through 6-12 define the timings associated with transfers.

Table 6-7 contains the values for the timings for each of the Ultra

~

(device+-)

DMACK-

(host)

--------'

STOP

(host)

HDMARDY

(host)

DSTROBE

(device)

_____

--------------j

---------------,

r-------------------------------

;(

!t--Tui

Tack Tenv

all

phases of Ultra

DMA

transfer modes.

Figure 6-3 Initiating a Data In Burst

11-------

Tcyc

DSTROBE

at device

DD(

15:0)

-----.l:~~ioo_---__.l~~r_---__.l:~~~---

at device

DSTROBE

at host

o O(

15:0)----t-7'C':~~~~~-'Oiib~0"IIi~~mioo__;_~~~~~';T

at host

Figure 6-4 Sustained Data In Burst

Note:

DD(15:0)

and

to emphasize

not

shall

allow the data signals to

DSTROBE that

T2cyc

-------tI

Tcyc

11-------+---

T2cyc---t!

signals are shown at both the host and the device

cable settling time as

well

as cable propagation delay

be

considered stable at the host until well

after they are driven by the device.

6-14 Quantum Fireball

CR

4.3j6.4j8.4j12.7AT

ATA Bus Interface and

DMARQ

(device)

DMACK---------------------------------------------------

(host)

ATA

Commands

STCP

(host)

(host

y

)

HDMARD

DSTROBE

(device

)

Tsr---a

i'-

"roo....

~

Trp

Trfs

.... ~ ....

DD(15:?kxxxxx)(

(device)

Figure 6·5 Host Pausing a Data In Burst

Note: The host knows the burst is fully paused Trp

may then assert

asynchronous pause.

OMARa

(device)

DMACK--------r------------------r----+~

(host)

Tli

STCP

(host)

xxxxxxx

STOP

to terminate the burst. Tsr timing need

1

ns

J

y----------------

after

HDMARDY -is

1"'------------

negated and

not

be met for an

HDMARDY-------+-------~

(host)

DSTROBE

(device)

DAO,DA1,DA2,------------------------------------~xxx:~~~~

CSO-,

CS1-

Tack~

--

-

Figure 6·6 Device Terminating a Data In Burst

Quantum Fireball

CR

4.3/6.4/8.4/12.7AT 6-15

ATA

Bus Interface and

ATA

Commands

Tli

DMARQ

(device)

DMACK---------+-----~r----~~

--------------~--------~I

(host)

Tmli

--:---tI

1'-------

STOP

(host)

---+-----1

Trp

HDMARDY-

(host)

~)----~t------j~~---t-~-~L------

Tack

DAO,DA1,DA2-,

CSO-,

CS1-

OMARQ

(

device

-------------------+)()(~~)(~

------------------------'-----~~~

)-------'

Figure 6-7 Host Terminating a Data In Burst

1-

Tui

1

DMACK-

(host)

---------

Sfa=>

(host)

DDMARDY---------r~1

(device)

~

(host)

D D

(host)~~~~~~~~~~~~~~~~~----~~~~~

_

______________

------~~-+--------~-,I

(15:rrc:i'"O~~~~:7'Iii::7d:~~~~~:7"Ii:~7"\Ur--_..;b~~~~

6-16 Quantum Fireball

-...---I--Tenv

4

;---

"'-

______

Figure 6-8 Initiating a Data Out Burst

CR

4.3/6.4/S.4/12.7AT

J

....

-Tui

ATA

Bus Interface and

ATA

Commands

HSTROBE

at host

00(15:0)

at host

HSTROBE

at

device

00(15:0)

at device

Note:

*-------

----+~~.----+~rl----+.~~---

Figure 6-9 Sustained Data Out Burst

DD(15:0) emphasize that cable settling time allow the data signals to be considered stable at the device until well after they are driven by the host.

and

HSTROBE

Tdvs

T2cyc

------"*

Tcyc

T2cyc

signals are shown at both the device and

as

well as cable propagation delay shall not

the

host to

DMARQ

(device)

OMACK-

(host)

STOP

(host)

OOMARO

(device

HSTROBE

(host)

00(15:0)

(host)

Note: The device knows the burst

Tsr---l

y-

)

XXXXXX

Figure 6-10 Device Pausing a Data

and may then negate for an asynchronous pause.

Trp

......--

Trfs

xxxxxxx

Out

is

fully paused

DMARQ

to terminate the burst. Tsr timing need not be met

1

)r,

Trp

Burst

ns after

..

I

'~'--

--

- -

------

DDMARDY-

- -

---

is

negated

Quantum Fireball

CR

4.3/6.4/8.4/12.7AT 6-17

ATA

Bus Interface and

ATA

Commands

Drv1ARQ

(device)

DMACK-

(host)

Tss

Tli

SlOP

(host)

DDMARDY-

(device)

Tli

HSTROBE

(host)

DD(15:0r-~~~~~~~~~~~~~dr~~~~~~7C~

(host)---~~~~~~~~~~~~~~~~~~~~~~~~

DAO,

DA1,

CSO-,

DA2,--------------------.lXXXh~~

CS1-

------------------------

___________________________________

Tiordyz

Tack

Tack 4

'------

\.

---

-L

----

-------

_____

~~~

--

Figure 6-11 Host Terminating a Data Out Burst

6-18 Quantum Fireball

CR

4.3/6.4/8.4/12.7AT

OMARa

(device)

ATA

Bus Interface and

ATA

Commands

Trp

---Tmi----~

OMAeK_----~--------~----~====~Tmm]li======~

(host)

STOP

(host)

OOMAROY-

(device)

Trfs

Tli

HSTROBE------------~~-------h~---------------r------~--

(h a st)

00(15:

(host)---'~~~~--~~~~~~~~~~~~~T_~~~~~

____________

-L-"'"-

____

--'

,-

--

Tack 1

OAO,OA1,OA~2,----------------------------------------~)()(~~

eso-,

es1-------------------------------------------~~---~

6.4.2.3

_R_ES_E_T_-

Figure

Host

Interface

The host interface and

2.0 volts. All times are in nanoseconds, unless otherwise noted. Figure 6-13 provides

a timing diagram.

SYMBOL DESCRIPTION

tM

___

~---------tM--------~~~-------------

RESET-Pulse

6-12 Device Terminating a Data out Burst

RESET

Table

Figure

Timing

RESET

6-8 Host Interface RESET Timing

6-13 Host Interface RESET Timing

timing shown in Table 6-8 is in reference to signals at 0.8 volts

MINIMUM MAXIMUM

width

Quantum Fireball

300

CR

4.3/6.4/8.4/12.7AT 6-19

-

ATA

Bus Interface and

ATA

Commands

6.5 REGISTER ADDRESS

The

host

select

CSIFX- and CS3FX-, and IOR-

A3-A9

lines

• Chip Select

• Chip Select CS3FX- is valid during Status Register.

The drive selects the primary

addresses

bit

A7.

Data bus lines data. The drive transfers

15

are invalid during transfers

I/O

to

or

from the drive occurs from selected registers, CS3FX-, DA2, DAl, Registers when transmitting commands when transmitting control, like a software reset. Table 6-9 lists

these

for

registers.

Table

FUNCTION

the

generate

CSIFX-

8-15

6·9

I/O

drive

the

are valid

by

DAO,

Port Functions and Selection Addresses

DECODING

by

using programmed I/O. Host address lines AO-A2, chip-

and

IOW- address

two chip-select signals, accesses

ECC

using DIOR-,

the

eight Command Block Registers.

8-bit

or

secondary command block addresses by setting Address

only

when

IOCS

information only

of

ECC

information.

over

an I/O

port

the

following encoded signals from the host:

and

DIOW-. The

to

the

CS

IFX-

transfers to

16-

is

active and

on

data

bus lines

that

routes input

host

writes

drive,

and

HOST

the

disk registers. Host address

and CS3FX-.

or

from

the

Alternate

the

drive

is

transferring

0-7.

Data bus lines

or

output

data

CS

to

the

Command Block

to

the

Control Block Registers

the

selection addresses

SIGNALS

to

or

IFX-,

8-

CONTROL

READ

Data

Bus

High

Data Bus High Impedance

BLOCK

(DIOR-)

Impedance

REGISTERS

WRITE

Not

(DIOW-)

Used N

Not Used

Data Bus High Impedance Not Used N

Alternate

Status Device Control N A

Drive Address Not Used N

COMMAND

READ

(DIOR-)

BLOCK

REGISTERS

WRITE

(DIOW-)

Data Port Data Port A

Error Register

Features

Sector Count Sector Count

0-7

8-15

High

16-23

4

5

4

5

4

5

Sector Number

LBA

Bits

0-7

Cylinder Low A

LBA

Bits

8-15

Cylinder High A N 1 0

LBA

Bits

16-23

Drive/Head A

Sector

Number

LBA

Bits

Cylinder Low

LBA

Bits

Cylinder

LBA

Bits

Drive/Head

CSIFX-

1

N A

CS3FX-

N

3

A

DA2

X2

DAI

X X

0 X

1 0 X

1 1

A 1 1

N

0 0 0 A N 0 0 A N 0 1 0 A N A

N N

A

N 1

0 1

1 0 0

0

A N 1 0

N 1 1

DAO

X

0

1

0

1 1

0

6-20

Quantum Fireball

CR

4.3/6.4/8.4/12.7AT

ATA

Bus Interface and

ATA

Commands

FUNCTION

LBA

Bits

24-27

5

Status

Invalid Address

1.

N = signal deasserted

2.

X = signal either asserted

3. A = signal asserted

4.

Mapping

5.

Mapping

of

registers in

of

registers in

After power the values shown in Table 6-10.

LBA

Bits 24-27

HOST

A N 1 1 0

SIGNALS

Command A N 1 1 1

Invalid Address A A X X X

or

deasserted

CHS

mode

LBA

mode

on

or

following a reset,

the

drive initializes the Command Block Registers to

Table 6-10 Command Block Register Initial Values

REGISTER VALUE

Error Register

Sector Count Register

Sector Number Register

01 01 01

Cylinder Low Register 00

Cylinder High Register 00

Drive/Head Register 00

Quantum Fireball

CR

4.3/6.4/8.4/12.7AT 6-21

ATA

Bus Interface and

ATA

Commands

6.6 REGISTER

The Quantum Fireball

and Control Block Registers. Functional descriptions next two sections.

6.6.1

6.6.1.1

6.6.1.2

Control Block Registers

Alternate

The Alternate Status Register contains the same information

command block. Reading the Alternate acknowledgment description

Device

This write-only register contains two control bits,

Status

Control

BIT

7 Reserved

6 Reserved -

5

4

3

2

1

0 0

DESCRIPTIONS

CR

4.3/6.4/8.4/12.7

Register

of

an interrupt by the host or clear a pending interrupt. See the

of

the Status Register in section 6.6.2.8 for definitions

Register

Table 6-11 Device

MNEMONIC

AT

hard disk drives emulate the

of

these registers are given in the

Status Register does not imply the

as

shown in Table 6-11.

Control

Register Bits

DESCRIPTION

-

Reserved Reserved

1

SRST

nIENz

Host software reset bit

Drive interrupt enable bit

-

Always 1

Always 0

ATA

Command

as

the Status Register in the

of

bits in this register.

1.

SRST the drive interface, this bit resets both drives simultaneously.

2.

nIEN the host has selected the drive, the drive enables the host interrupt signal When interrupt signal regardless interrupt.

6-22 Quantum Fireball

= Host Software Reset bit. When the host sets this bit,

is

reset. When two drives are daisy-chained on the

= Drive Interrupt Enable bit. When

INTRQ

nIEN

equals 1 or the drive

of

the presence or absence of a pending

CR

4.3/6.4/8.4/12.7AT

through a tristate buffer to the host.

INTRQ

is in a high-impedance state,

nIEN

equals 0

is

not selected, the host

or

AT

A Bus Interface and .ATA Commands

6.6.1.3

Drive Address Register

The Drive Address Register returns the head-select addresses for the drive currently

selected. Table 6-12 shows the Drive Address bits.

Table 6-12 Drive Address Register Bits

DESCRIPTION

High Impedance bit

Write Gate bit

Head Address msb

-

Head Address lsb Drive 1 Select bit Drive 0 Select bit

--

BIT

7 6

5

4 3 2

1

0

1.

MNEMONIC

I

HiZ

2

nWTG

3

nHS3

nHS2 nHS}

nHSO

4

nDS1

nDSO

HiZ

= High Impedance bit. When the host

reads the register, this bit will be in a high impedance state.

2.

nWTG operation to the drive equals

= Write Gate bit. When a write

is

in progress,

nWTG

O.

3. nRSO-nHS3 = Read Address bits. These bits are equivalent to the one's complement binary-coded address.

of

the head currently

of

the

selected.

4.

nDSO-nDS 1 = Drive Select bits. When drive 1

is

selected,

nDS1

nDSO

equals

O.

When drive 0

is

6.6.2

6.6.2.1

6.6.2.2

Command

Data

Port Register

Block Registers

All data transferred between the device data buffer and the host passes through the Data Port Register. The host transfers the sector table to this register during execution FORMAT

TRACK

command.

Error Register

The

Error Register contains status information about the last command executed by the

drive. The contents

is

Register

set to

the completion

code. When the error bit in the Status Register is set to Register bits

of

this register are valid only when the Error bit

1.

The contents

of

the drive's internal diagnostics, when the register contains a status

as

shown

in

Table 6-13.

of

the Error Register are also valid at power on, and at

1,

the host interprets the Error

Quantum Fireball

CR

4.3/6.4/8.4/12.7AT 6-23

(ERR)

in the Status

of

the

ATA

Bus Interface and

ATA

Commands

Table 6-13 Error Register Bits

MNEMONIC

# # # # #

ABRT

# #

6.6.2.3

6.6.2.4

BIT

DESCRIPTION

7 6 5 4 3

2 Requested command aborted due to a drive status error, such as Not

Ready or Write Fault, or because the command code

1

0

Sector

Count

Register

The Sector Count Register defines the

host

bus

for a subsequent command. If the value in this register is 0,

is

256 sectors. this register the the that

When the

Sector

Sector Count Register command's

must

the

value

Number

If

the

at

Sector Count Register command executes successfully, the

command completion is

to

execution is unsuccessful, this register contains

be

transferred to complete

drive executes an

INITIALIZE

in this register defines

Register

The Sector Number Register contains

a

subsequent

number

command. The sector number

of

sectors per track. As

reflect

the

number

O.

the

number

the

DRIVE

number

the

of

sectors

of

data

As the drive transfers each sector, it decrements

of

sectors remaining to be transferred.

original request.

PARAMETERS

of

sectors

ID

number

is

a value between one and

of

per

the

track.

first sector

drive transfers each sector, it increments

is

invalid.

to

be transferred across

the

number

or

Format Track command,

to

be accessed

the

Number Register. See the command descriptions in section 6.7 for information about

contents

of

the

Sector Number Register after successful

or

unsuccessful command

completion.

sector

count

value

of

sectors

maximum

the

Sector

in

If

by

the

LBA

In this

6.6.2.5

Cylinder Low Register

The Cylinder Low Register contains

address for the current into

LBA

In updates

6.6.2.6

Cylinder High Register

The Cylinder High Register contains

address for the current into

6-24 Quantum Fireball

mode, this register contains bits 0 to 7.

register

to

reflect

the

current

LBA

bits 0

the

any

disk access. On multiple sector transfers

drive updates this register when command execution

cylinder number. The host loads

the

Cylinder Low Register.

At

command completion,

to

7.

eight low-order bits

that

is

the

least significant bits

of

the

cross cylinder boundaries,

complete,

mode, this register contains bits B to 15. At command completion,

this

register

any

drive updates this register

cylinder number. The host loads

the

Cylinder High Register.

CR

4.3/6.4/B.4/12.7AT

to

reflect

the

current

LBA

bits B

the

eight high-order bits

to

disk access. On multiple sector transfers

at

the

completion

the

of

command execution, to reflect

most significant bits

15.

of

that

the

cross cylinder boundaries,

the

host updates

starting cylinder

to

reflect

of

the

cylinder address

the

drive

starting cylinder

of

the

cylinder address

the

In

LBA

mode, this register contains bits

updates this register to reflect the current

ATA

Bus Interface and

16

to

23. At command completion, the host

LBA

bits

16

to 23.

ATA

Commands

6.6.2.7

Drive/Head Register

The Drive/Head Register contains the drive

completion this register

In

LBA

mode, this register contains bits 24 to 27. At command completion, the drive

is

updated by the drive to reflect the current head.

updates this register to reflect the current

Table 6-14 shows the Drive/Head Register bits.

Table 6-14 Drive Head Register Bits

MNEMONIC

Reserved 7

L

Reserved

DRV

HS3

HS2

HS1

HSO

BIT

1

2

6

5

3

4

3

2

1

0

ID

number and its head numbers.

LBA

bits 24 to 27.

DESCRIPTION

Always 1

o for

CHS LBA

mode

1 for

Always 1

o indicates the Master drive is selected

1 indicates the Slave drive is selected

Most significant Head Address

Bit 24

of

the

LBA

Address in

Head Address bit for

Bit 25

of

the

LBA

Address in

Head Address bit for

of

the

LBA

Bit 26

Address in

Least significant Head Address bit in

Bit

27

of

the

LBA

Address in

bit

CHS

in

LBA

mode

LBA

mode

LBA

At

command

CHS

mode

CHS

mode

6.6.2.8

1.

Bits

5-7

define the sector size set in hardware (512 bytes).

2.

Bit 6 is the binary encoded Address Mode Select. When bit 6 is set to

addressing

3.

Bit 4 primary drive; the Slave

4.

In

CHS selected head. At command completion, the host updates these bits the address contain bits 24-27 updates this register to reflect the current

is

(DRV)

mode, bits

by

CHS

mode. When bit 6 is set

contains

of

the

binary encoded drive select number. The Master is the

is

the secondary drive

3-0

(HSO-HS3)

contain the binary encoded address

the head currently selected. In

of

the

LBA

Address. At command completion,

to

1,

LBA

bits 24 to 27.

addressing is

mode, bits

by

3-0

LBA

to

(HSO-HS3)

the

Status Register

The Status Register contains information about the status

of

The drive updates the contents

the Busy bit is set the Busy bit is not set Block Registers

(BSY = 1),

is

valid.

(BSY=O),

this register at the completion

no other bits in the Command Block Registers are valid. When

the information in the Status Register and Command

When an interrupt is pending, the drive considers interrupt when it reads the Status Register. Therefore, whenever

of

the

drive

and

the controller.

of

each command. When

that

the host has acknowledged the

the

host reads this register, the drive clears any pending interrupt. Table 6-15 defines the Status Register bits.

Quantum Fireball

CR

4.3/6.4/B.4/12.7AT 6-25

0,

mode.

of

the

reflect

host

ATA

Bus Interface and

ATA

Commands

Table 6-15 Status Register Bits

MNEMONIC

tl:,y

DRDY

# 5 # 4

DRQ

Obsolete 2 Obsolete 1

ERR

BIT

'/

6

3

0

DESCRIPTION

tlusy

tnt. :,et by the controller

drive has access to

and

the host is locked

lOgIC

Block Registers. BSY

is set

under

the following conditions:

• Within 400 ns after the

Device Control Register. Following a reset,

longer

than

30 seconds.

• Within 400 ns Read,

READ

LONG,

DRIVE

PARAMETERS,

DIAGNOSTIC

• Within 5 Jlsec after tion

of

a Write, Format Track,

of

bytes ecution

When reading

data

of a WRITE

BSY==l,

the

any

Command Block Register returns

the

of

a host write

READ

command.

the

and

the

appropriate

LONG

host

cannot

deassertion

BUFFER,

Read Verify, Identify Drive, or

transfer

command.

write to a Command Block Register

Register. Drive

Ready

When

bit. Indicates

an

error occurs, this bit remains

that

the

Status Register, then again indicates

bit

should be cleared,

and

ready

to

accept a command.

Data

Request bit. When set, this

fer a word

Error

or

byte

bit.

When set, this an error. The other bits in contain

additional information

and

should remain cleared until

bit

of

data

from

the

bit

indicates

the

Status Register

about

ot

the

dnve

whenever the

out

of

the

Command

of

RESET-or after

to

the

Command Block Registers with a

SEEK,

BSY

will be set for no

RECALIBRATE,

EXECUTE

of

512

bytes

of

data

or

WRITE

number

drive is

unchanged

that

the

indicates

host

to

that

the

BUFFER command,

of

ECC

the

contents

ready

to

drive is ready. At power on, this

that

the

data

the

previous command resulted in

and

the

cause

of

during

bytes during

of

accept a command.

until

the

drive is up to speed

drive is ready

port.

bits in the Error Register

the

error.

SRST

is

INITIALIZE

the

or

and

the Status

host reads

set in

DRIVE

execu-

512

the

ex-

the

to

trans

Note: The

content

Bits 2

and

6.6.2.9 Command Register

The host sends a command to the drive by means

Command Register. As soon as the drive receives the it begins execution and parameters for each executable command. The code extended commands. Each a detailed description found later in this chapter.

6-26 Quantum Fireball

CR

4.3/6.4/8.4/12.7AT

of

# bit is command dependent.

1 are obsolete according

to

the

ATA-4 specification.

of

an

8-bit

command

of

the command. Table

6-16

lists

the

hexadecimal command codes

FOh

of

these commands is distinguished

of

each command, see Section 6.7, "COMMAND

code written to

in

its Command Register,

is common

by

a unique subcode. For

to

the

all

DESCRIPTIONS,"

of

the

ATA

Bus Interface and

ATA

Commands

Table 6-16 Quantum Fireball

COMMAND

NAME

RElALJ.HKAl~

I

KtAJJ

;).t:LfU.K!S

WRITE

I

KtAJJ

SEEK

EXH

IlNll.AL1Z~

IUuvv.

;)MAK.l

KtAJJ

I

VV

S.bT

IKtAJJ

VV.KIT.b S'AANUBY IMMF.lllt\:JE

IIDL.b

S'

IlDll

KtAJJ

SLEEP l'LU;)l1

VV

lD~NHI:'1

.K.bA1J

KtAJJ

StT

SLAN V U.bT READ SET

;)~I~lUKS

V~1"Y

IT.b

MUL1U'll

.Kll ~ MUL

MULUPL.b MUlJ.b

DMA

IMMI-'IIIA

'ANURY

MUD.b

BUrr.b.K .b4n

HI-'IK

t'UVV~K

MUD.b .b6n

..A~11~'

.KIlb

HUt'

U.b1".bCl

LUNt'lUUKAUUN-extenaea

SlAN

NATIVE

MAX

S.bClU.KS

lJ.KIV.b lJIAUNU;).11L

.lJ.KlV~

IA

MUDE

1"

DRIVE

IJN

...

~1"

V.b.K1t'I

A 11IlKI-'''''

t'A.t<A1VI..Cl~K;)

MIL.KULuu.t:

llt'll

.

.I:'.

(AUTU t'uVV.t:K-UUVVNJ

tAUlU

IUU.KATlUN· extended cmnd.

t'UVV.b.K-DUVVNJ

MODE

optIonal

.b.K

USI-extenaea

I

-extended SlAIUs-extenaea

MAX

jl.IJlJK

cmna.

cmnd.

....

cmna.

SS

CR

cmna.

4.3/6.4/B.4/12.7AT

CODE

lXh

20n 30h 40n

7Xh

90h !:lIn V 92n Hun L4n CSh L6n (8h

LAn

EOh .bIn E2n V .b3n

ESn V

~7n

.b8n E(h

1"on

rOh 1"un

1"On

cmna.

1"on

F8

.

r9 V

Command

PARAMETER

SC

Ex. Sub

Code

uun Ulh

SN

V V V

V

V V

V V V

V

V V V

~~~

1"Ut v rDn

V

Codes

CY

V

V V

V V V V

v

V

V V V

V

and Parameters

OS

V V V V

V V

V V V

v

V

i

HD

..

'

V V V V

V V

V

v

V

V V

V

_

..

,..-

FR

Note: The

SC SN CY = DS HD

V =

FR

following

= Sector

Cylinder

=

Drive

= 4 Head Select

Must

= Features Register

information Count Number

Low

Select

contain

Register

and

bit

Bits

valid

applies

High

(Bit 4 of

Registers

Drive/Head Register)

(Bits

0-3

information

Quantum Fireball

to

Table

of

Drive

for

this command

6-16:

Head Register)

CR

4.3/6.4/8.4/12.7AT

6-27

ATA Bus Interface and

ATA

Commands

6.7 COMMAND DESCRIPTIONS

6.7.1

The Quantum Fireball drive decodes, applications involving the

selected drive executes DIAGNOSTIC the

selected drive is as follows:

1.

Wait for

2.

Activate

3. Wait for

4. Load the required parameters into

5. Write

Execution Register. The remainder commands are listed in

Recalibrate 1

The

RECALIBRATE

to

cylinder command status, negates posts

the

then

command,

the

of

the

xh

O.

On

to

cylinder

message

CR

hard

executes, commands loaded into the Command Block Register. In

two

as

drive

to

the

Interrupt Enable (-lEN) bit.

the

drive

to

command

BSY,

of

the

command

receiving

O.

The

and

generates

TRACK 0 NOT

disk drives support all standard ATA drive commands. The

hard drives, both drives receive all commands. However,

commands-with explained below. The procedure for executing a command

indicate

set

code

begins as soon as

this

same

this

that

RDY

[RDY:;l).

to

the

section describes the function

order they appear in Table 6-16.

moves

the

command,

drive then waits for the seek operation to complete, updates

an

FOUND.

the exception

it

is

no longer busy

the

Command Block Register.

Command Register.

the

drive loads

read/write heads from

the

drive sets the

interrupt.

If

the drive

of

the

EXECUTE

(BSY:;O).

the

Command Block

of

each command. The

any

BSY

cannot

location on

bit

and issues a seek

seek to cylinder 0,

DRIVE

the

only

on

disk

it

6.7.2

6.7.2.1

6.7.3

Read

Multiple

Write

Sectors

The Read Sectors command reads from 1 As specified in sectors. When command.

Sector

Multiple sector reads when

the sector buffer is full,

the

host

If

an error occurs during a multiple sector read, the read terminates

the

error occurred. The Command Block Register contains the cylinder, head,

numbers Block Register the

data

buffer.

Sector

The

WRITE sector. As specified in 256 sectors. When fill

the an DRQ,

sector buffer with

interrupt

sets

20h

the

Reads

empties

of

the

to

error

is

30h

SECTOR

to

BSY,

to

256 sectors, beginning

the

Command Block Register, a sector count equal

drive accepts this command, it sets

set

DRQ.

After reading each sector, the drive generates an interrupt and

the

sector buffer,

sector

in

which

determine

correctable

the

start

the

and begins execution

what

or

uncorrectable,

command

the

drive accepts this command, it sets

first buffer-fill operation. Once the buffer is full, the drive clears

writes from 1

Command Block Register, a sector

the

data

drive is ready for the

the

drive immediately clears

the

error occurred. The host

kind

of

error has occurred, and in which sector. Whether

the

drive loads

to

256 sectors, beginning

to

be written to the drive. The drive does

of

the command.

BSY

at

the

and

DRQ

to

begins execution

host

to

read

DRQ

at

can

then

the

data

count

equal to 0 requests

and waits for

specified sector.

0 requests 256

the

and

sets

the

sector

read

the

into

at

of

data. Once

BSY.

in

and

Command

the

sector

the specified

the

host

not

generate

the

which sector

to

6-28 Quantum Fireball

CR

4.3/6.4/8.4/12.7AT

ATA

Bus Interface and

ATA

Commands

6.7.3.1

6.7.4

6.7.5

Multiple

Sector

The

MULTIPLE whenever the sector buffer drive immediately clears

If an error occurs during a multiple sector write operation, the write operation terminates at the sector in which the error occurred. The cylinder, head, and sector numbers then read the in which sector.

Writes

SECTOR

Command Block Register to determine what kind

WRITES

DRQ

command sets

is

ready to be filled. When the host fills the sector buffer,

and sets

BSY.

of

the sector in which the error occurred. The host can

DRQ.

The drive generates an interrupt

Command Block Register contains

of

error has occurred, and

Read Verify Sectors 40h

The execution

SECTORS DRQ,

the drive transfers no data to the host, and the Long bit

READ

VERIFY sectors, it clears Block Registers contain the cylinder, head, and sector numbers

If an error occurs during a multiple sector verify operation, the read operation terminates at the sector in which the error occurred. The cylinder, head, and sector numbers in which the error occurred.

Seek

7xh

The

SEEK Head registers point. When the drive receives this command in its Registers, it performs the following functions:

of

the

READ

command. However, the Read Verify command does not cause the drive to

command, the drive sets

BSY

command causes the actuator to seek the track to which the Cylinder

VERIFY

and generates an interrupt.

SECTORS

BSY.

command is identical

When the drive has verified the requested

On

command completion, the Command

Command Block Registers contain

to

that

of

the

is

invalid.

of

On

receiving

the last sector verified.

and

Command Block

the

READ

set

the

Drive/

6.7.6

1.

Sets

BSY

2.

Initiates the seek operation

3. Resets

4.

The drive does not wait for

bit is not set in the Status Register, the drive can accept and queue subsequent commands while performing the seek. If the sets the

Execute

The

EXECUTE

implemented on the drive. Drive If

Drive 1 is present:

• Both drives execute diagnostics.

• Drive 0 waits up to six seconds for drive 1 to assert PDIAG-.

BSY

Sets the Drive Seek Complete

the

seek to complete before it sends an interrupt.

Cylinder registers contain an illegal cylinder,

ERR

bit in the Status Register and the

Drive Diagnostic 90h

DRIVE

DIAGNOSTIC

0 sets

(DSC)

bit

in

the

Status Register

If

the

IDNF

bit in the Error Register.

command performs the internal diagnostic tests

BSY

within 400 ns

of

receiving

of

the command.

the

BSY

drive

Quantum Fireball

CR

4.3/6.4/8.4/12.7AT 6-29

ATA

Bus Interface and

ATA

Commands

• If drive 1 does not assert PDIAG- to indicate a failure, drive 0 appends 80h with its own diagnostic status.

•

If

the host detects a drive 1 diagnostic failure when reading drive 0 status,

it sets the

DRV

bit, then reads the drive 1 status.

If Drive 1

• Drive 0 reports only its own diagnostic results.

• Drive 0 clears

If drive I fails diagnostics, drive that code into the Error Register. drive Register.

The diagnostic code written to the Error Register the diagnostic codes.

is

not present:

0 appends

BSY

and generates an interrupt.

0 appends 80h with its own diagnostic status and loads

If

drive 1 passes its diagnostics or no drive 1 is present,

OOh

with its own diagnostic status and loads

Table 6-17 Diagnostic Codes

DIAGNOSTIC

CODE

Olh 02h Formatter Device Error 03h

04h OSh

8Xh Drive 1 Failed

Controlling Microprocessor Error

DESCRIPTION

No

Sector Buffer Error

ECC

that

code into the Error

is

a unique 8-bit code. Table 6-17 lists

Error Detected

Circuitry Error

6.7.7

6-30 Quantum Fireball

Initialize Drive Parameters

The

number

the drive sets the The only two register values used by this command are the Sector

specifies the number

of

heads, minus 1. The

This command does not check the sector count and head values for validity. values are invalid, the drive will not report an error until another command causes an

illegal access.

INITIALIZE

of

DRNE

heads and the logical number

CR

4.3/6.4/8.4/12.7AT

PARAMETERS

BSY

bit, saves the parameters, clears

of

sectors; and the DriveIHead Register, which specifies

DRV

91

h

command enables the host to

of

sectors per track.

bit assigns these values

BSY,

to

drive 0

set

the logical

On

receiving the command,

and generates an interrupt.

Count Register, which

or

drive

the

number

1,

as appropriate.

If

these

ATA

Bus Interface and ATA Commands

6.7.8

Sector Number

Cylinder

Cylinder High

Download Microcode

COMMAND TYPE PROTOCOL -PIO INPUTS - The head bits

and

high together as a 16-bit sector

code.

Register 7

Features

Sector Count

Low

Device/Head 1

Command

NORMAL

CODE -92h

- Optional

low registers will

OUTPUTS-

data

out

of

the

be

count

6

I

I I

None. required.

device/head register will always be set to zero. The cylinder

set to zero. The sector number and

value. The feature register specifies the subcommand

I

5

Sector

1

4

I

Subcommand code

Sector

I

count

OOh OOh

D

92h

I

(low order)

(high order)

I

3

0

I

the

sector count are used

2

0

I

0

I

0

DRDY

V

ERROR

not

value.

Status

DF

I

V

I

PREREQUISITES -

DESCRIPTION - This command enables

transferred using

All transfers will be an integer multiple

determined The sixteen bit sector count value. The

eight bits and

zero in both

data is to transferred. This allows transfer sizes from

byte increments.

The Features register will be used

sub command. The values for

01h - download is for immediate, temporary use

07h - save downloaded code for immediate

OUTPUTS-

accept

the

Register

CORR I ERR

I

I I

by

Sector Number register will

Aborted command

microcode data. Aborted error

BBK

V

DRDY

set equal

the

DOWNLOAD

the contents

the

Sector Count register will be

the

Sector Number register

I

I I I

to

MICROCODE

of

the

Sector Number register and the Sector Count register.

be

used to extend

Sector Number register will be

to

determine

the

Feature Register are:

if

the

device does not support this command

if

subcommand code is

Error Register

UNC

one.

the

of

and

IDNF I ABRT

I

host

to

alter the device's microcode. The data

command is vendor specific.

the

sector size. The size

the

Sector Count register, to create a

the

least significant eight bits. A value

the

Sector Count register will indicate no

0 bytes to 33, 553, 920 bytes in 512

the

effect

of

and

future use.

I

V

I l

of

the

DOWNLOAD

TKONF

or

not

a supported

I

the data transfer is

most significant

MICROCODE

did

AMNF

of

Either

or

both values may

be

supported. All other values are reserved.

CR

Quantum Fireball

4.3/6.4/8.4/12.7AT 6-31

ATA

Bus Interface and

ATA

Commands

6.7.9

Sector Number

Cylinder Low 4Fh

Cylinder High

SMARTBOh

SMART DISABLE OPERATIONS

COMMAND

TYPE

command shall be implemented. PROTOCOL INPUTS

to 4Fh. The

Register

Features

Sector

Count

Device/Head 1

Command

NORMAL

CODE -BOh

- Optional -

- The Features register shall be set

SMART

- Non-data command

Cylinder High register shall be set to C2h.

7

I

OUTPUTS

- None

Feature set.

6

I

j

If

the

SMART

to

D9h. The Cylinder Low register shall

I

4

D

5

1

feature set is implemented,

I

D9h

C2h

3

I

2

I I I

BOh

I

this

be

set

I

0

J

ERROR or Aborted command error is posted.

Status Register

DRDY

V V

DF

PREREQUISITES DESCRIPTION - This command disables all

including any and all timer functions related exclusively this command longer

disabled) will be preserved by

Upon receipt sets

After receipt

exception by

Aborted command error.

OUTPUTS -If

if

the

values in

CORR

be

monitored or saved

BSY,

the

of

disables

of

SMART

device (including

the

device does not support this command,

the

Features, Cylinder

ERR

DRDY

the

device will disable all

the

SMART

this command

BBK

set equal to one.

by the

SMART

ENABLE

DISABLE

capabilities and functions, clears

OPERATIONS,

SMART

Low

or Cylinder High registers are invalid,

Error Register

UNC

the

device. The state

device across power cycles.

OPERATIONS

by

the

device, all other

DISABLE

IDNF

SMART

operations. Attribute values will

are disabled

OPERATIONS

enabled.

capabilities within

command from

if

SMART

ABRT

V

to

this feature. After receipt

of

SMART

and

commands), returning

(either enabled

BSY

and

commands, with

invalid and shall be aborted

TKONF

the

host,

asserts

is

not

AMNF

device

the

INTRQ.

enabled

an

of

no

or

device

the the

6-32 Quantum Fireball

CR

4.3/6.4/8.4/12.7AT

ATA

Bus Interface and

ATA

Commands

6.7.9.1

SMART ENABLE/DISABLE COMMAND

TYPE

command is optional and

PROTOCOL

INPUTS

to 4Fh. The

OOh

Register 7

Features D2h

Sector

Count

Sector Number

Cylinder

Cylinder High C2h

Device/Head 1

Command Bah

Low

NORMAL

CODE·

- Optional -

- Non-data command

- The Features register shall Cylinder High register shall be set to C2h. The Sector Count register

to disable attribute autosave

BOh

SMART

I

I I

OUTPUTS

not

6

- None

ATTRIBUTE

Feature set.

recommended.

and

5

I

1

AUTOSAVE

If

the

SMART

be

set

to D2h. The Cylinder Low register shall be set

a value

I

of

4

OOh

D

feature set is implemented, this

FIh

is

set to enable attribute autosave.

I

or

4Fh

Flh

I

2

3

I

I I I I

I

is

set to

0

DRDY

V

ERROR if Aborted command error

Status register

DF

PREREQUISITES -DRDY DESCRIPTION

feature allow the device, after some attribute values to non-volatile memory; feature to disabled) will be preserved

A value this command will cause this feature preclude other normal operation such

error recovery sequence.

A value this command will cause this feature to be enabled.

any other non-zero value written

OUTPUTS -If

the

values in the Features, Cylinder Low

CORR

of

the device. Depending

be

disabled. The

of

zero written

the

device from

of

F 1 h written

the device does

is

posted.

ERR

V V

- This command enables and disables

BBK

set equal

vendor

state

by

the

saving

by

the

of

the

host

attribute values to non-volatile memory during some

as

during a power-on

host

not

UNC

to

one.

upon

the

specified event, to automatically save its updated

the

attribute autosave feature (either enabled

device across power cycles.

into

the device's Sector Count register before issuing

to

be

into the device's Sector Count register before issuing

by

the

support this command,

or

Cylinder High registers are invalid,

Error register

IDNF

SMART

implementation, this command may either

or

disabled. Disabling this feature does

host into this register before issuing this

enabled.

the

optional attribute autosave

this command may cause

or

power-off sequence

Any

if

SMART

ABRT

other meaning

TKONF

the

is disabled

AMNF

autos ave

not

or

during an

of

this value or

or

an

or

Quantum Fireball

CR

4.3/6.4/8.4/12.7AT 6-33

Quantum CR43A013, Fireball CR 4.3AT Manual

Specifications and Main Features

Frequently Asked Questions

User Manual