Quanta ZRZL Schematic
5
4
3
2
1
ZRZ/ZRZL BLOCK DIAGRAM
VR
hannel A (CZ)
DDRI
II-SODIMM1
P9
D D
II-SODIMM2
DDRI
P10
S
ATA - HDD
ATA - ODD
S
B3 Con.
US
US
C C
CR Con.
P25
B B
USB2 DB
B3 Con.
rdreader
Ca
RT
S5170-GRT
IO
Board
Connector
P24
P24
P25
P25 P25
P25
P25
alia
Az
AUDIO CODEC
C255 -CG
AL
A A
Ph
Jack
one
P22
peaker DMIC
S
5
P22
Knowles
NeoMEMS
C
IE 0~3
PC
PC
IE 4~7 (CZ)
Channel B
FP4
TDP:15W
C
IM
CARRIZO(15h)
PEG
TX
/RX
60h-6Fh
CARRIZO-L(16h)
A 0
SAT
A 1
USB3 - 3
B2 - 7
US
USB Charger
P22 P30
P22
USB3 - 2
B2 - 6
US
US
B2-1 (CCD)
USB2-2 (Touchpad)(CZ-L)
USB2-4 (M.2)
USB2-3 (Touch Screen)
US
USB2-0
D
LE
6
P2
4
SAT
A0
SAT
A1
USB3.0
U
AP
BG
A 968
USB2.0
B2-3
P2,3,4,5,6,7,8
CLK
HDA
LP
C
EC
8987E/BX
IT
LL SENSOR
B Con.
K/
B BL Con.
K/
P28 P17 P28 P27
HA
P28
SAT
30h-3Fh
DP
DP1
DP
GP
SPI
RT
0
2
P
C
I2C-0 (Touc hpad) (CZ)
I2
C-1 (Touch Scree n)(CZ)I2C
DP
0
PS8339B
1
DP
DP DeMUX
P18
DP
2
X'
TAL
32.768KHz
X'TAL 48MHz
SPI
CZ
:1.8V / CZ-L:3.3V
T
BAT
P7
N Con.
FA
(DAC)
3
ROM 8M
2
PS/
uch Pad
To
Con.
P6
O GPU
GE
so XT 25W
Me
Exo XT 25W
S3
23mm X 23mm
P11,12,13,14,15 P16
X'
TAL
27.0MHz
US
B2-2 (Touch)
USB2-5 (CCD)
DP to VGA
IT6516
P19
GPP1
B2-4
US
GP
P0
annel
Ch
P/TS/CCD Con.
eD
I Con.
HDM
CRT
Con.
M.2
WLAN+BT
w/ Debug
VR
VRAM DDR3-256Mb*16*4 = 2GB
CZ@ :CARRIZO
CZL@ :CARRIZO-L
SP@ :special part
UBT@ :USB TS
P17
I2CT@ :I2C TS(only CZ reserve)
EV@ :GPU
Maso@ :Maso GPU
Exo@ :Exo GPU
EV_SP@:GPU special part
TPM@ :TPM
TPM_I@:SLB9655TT1.2
TPM_N@:NPCT650AAAWX
P18
GS@ :G-sensor
HDT@ : Debug
KBL@ :KB Backlight
IOAC@ :IOAC
P19
NIOAC@:non-IOAC
P21
LAN
L8111H
2
RT
USB2-1 (CZ-L)
TYPE1 : CZ
TYPE2 : CZL
P20
24737
BQ
Ba
tery Charger
TP
S51225
3V
/5V
8237
RT
0.
95V
G5
316
+1
.5V_SUS
ze Document Number Rev
ze Document Number Rev
ze Document Number Rev
Si
Si
Si
Date: Sheet
Date: Sheet
Date: Sheet
TP
M
NPCT650
0ohm
option
X'
TAL
25MHz
P2
I2
C-0 (CZ)
CY
USB to I2C
(CZ-L)
3
7C65211
AM DDR3-128Mb*16*4 = 1GB
AM
Reset Button
RJ
45 Con.
P20
L62771
IS
CP
U CORE / VDDNB
0
P3
RT
8068
1.
8V
1
P3
L62771
IS
VG
PU CORE
P32
RT
8068
GP
U_POWER / VDDC_GFX
P3
3
anta Computer Inc.
anta Computer Inc.
anta Computer Inc.
Qu
Qu
Qu
PROJECT :
PROJECT :
PROJECT :
ock Diagram
ock Diagram
ock Diagram
Bl
Bl
Bl
1
P34,35
P36
P3
7
8
P3
Z
Z
Z
ZR
ZR
ZR
1Wednesday, March 18, 2015
1Wednesday, March 18, 2015
1Wednesday, March 18, 2015
of
of
of
14
14
14
1A
1A
1A
1
PU)
(C
LAN
A A
1.05V VDDP only for CZ with DDR-2133 memory
If running DDR-1866 or slower memory,
Platform VDDP should be set to 0.95V
WLAN
PCIE_RXP0[20]
PC
IE_RXN0[20]
PC
IE_RXP1[21]
IE_RXN1[21]
PC
VD
DP_0.95V
2
CZ: (196R_CS11962FB00)
CZL:(1.69K_CS21692FB01)
R3
99 SP@196/F_4
TX_ZVDD_095
P_
3
U1
0
P_
GPP_RXP[0 ]
U9
P_GPP_RXN[ 0]
T6
P_GPP_RXP[ 1]
T5
GPP_RXN[1 ]
P_
T9
GPP_RXP[2 ]
P_
T8
P_
GPP_RXN[2 ]
P7
P_
GPP_RXP[3 ]
P6
P_GPP_RXN[ 3]
U7
ZVDDP
P_
4
U28B
PCIE
R1
R2
R4
R3
N1
N2
N4
N3
U6
PCIE_TXP0_C
PC
IE_TXN0_C
PC
IE_TXP1_C
IE_TXN1_C
PC
RX_ZVDD_095
P_
P_
GPP_TXP[0]
P_GPP_TXN[0 ]
P_GPP_TXP[1 ]
GPP_TXN[1]
P_
GPP_TXP[2]
P_
P_
GPP_TXN[2]
P_
GPP_TXP[3]
P_GPP_TXN[3 ]
ZVSS/P_ RX_ZVDD P
P_
5
AC-coupling capactior
CZ :Gen3 (220nF) CH4222K9B04
CZL:Gen1/2 (100nF) CH4103K1B08
Current device no Gen3
58 0.1U/16V/X7R_4
C5
C5
57 0.1U/16V/X7R_4
C5
44 0.1U/16V/X7R_4
43 0.1U/16V/X7R_4
C5
00 CZL@1K/F_4
R4
R4
01 CZ@196/F_4
VD
DP_0.95V
6
PCIE_TXP0 [20 ]
PC
IE_TXN0 [20]
PC
IE_TXP1 [21]
IE_TXN1 [21]
PC
LA
N
WLAN
7
8
P1
0
P_
L10
P9
N6
N5
N9
N8
L7
L6
L9
K6
K5
K9
K8
J7
J6
GFX_RXP[ 0]
GFX_RXN[ 0]
P_
GFX_RXP[ 1]
P_
GFX_RXN[ 1]
P_
P_
GFX_RXP[ 2]
P_
GFX_RXN[ 2]
P_
GFX_RXP[ 3]
GFX_RXN[ 3]
P_
GFX_RXP[ 4]
P_
P_
GFX_RXN[ 4]
GFX_RXP[ 5]
P_
P_GFX_R XN[5]
P_
GFX_RXP[ 6]
GFX_RXN[ 6]
P_
P_GFX_R XP[7]
P_
GFX_RXN[ 7]
FP
4 REV 0.93
SP@FP4
_RXP0[11]
PEG
PEG
_RXN0[11]
_RXP1[11]
PEG
_RXN1[11]
PEG
PEG
_RXP2[11]
PEG
_RXN2[11]
_RXP3[11]
PEG
_RXN3[11]
X4 : CARRIZO-L (G EN2)
B B
C C
X8 : CARRIZO (GEN3 )
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
_RXP4[11]
_RXN4[11]
_RXP5[11]
_RXN5[11]
_RXP6[11]
_RXN6[11]
_RXP7[11]
_RXN7[11]
P_
GFX_TXP[0 ]
GFX_TXN[ 0]
P_
GFX_TXP[1 ]
P_
GFX_TXN[ 1]
P_
P_
GFX_TXP[2 ]
P_
GFX_TXN[ 2]
P_
GFX_TXP[3 ]
GFX_TXN[ 3]
P_
GFX_TXP[4 ]
P_
P_
GFX_TXN[ 4]
GFX_TXP[5 ]
P_
P_GFX_TXN[ 5]
P_
GFX_TXP[6 ]
GFX_TXN[ 6]
P_
P_GFX_TXP[ 7]
P_
GFX_TXN[ 7]
M2
M1
L1
L2
L4
L3
J1
J2
J4
J3
H2
H1
G1
G2
G4
G3
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
_TXP0_C
_TXN0_C
_TXP1_C
_TXN1_C
_TXP2_C
_TXN2_C
_TXP3_C
_TXN3_C
_TXP4_C
_TXN4_C
_TXP5_C
_TXN5_C
_TXP6_C
_TXN6_C
_TXP7_C
_TXN7_C
59 EV_SP@0.22u/10V_4
C5
C5
60 EV_SP@0.22u/10V_4
C5
46 EV_SP@0.22u/10V_4
45 EV_SP@0.22u/10V_4
C5
C5
61 EV_SP@0.22u/10V_4
C5
62 EV_SP@0.22u/10V_4
48 EV_SP@0.22u/10V_4
C5
47 EV_SP@0.22u/10V_4
C5
C5
63 EV_SP@0.22u/10V_4
C5
64 EV_SP@0.22u/10V_4
50 EV_SP@0.22u/10V_4
C5
C5
49 EV_SP@0.22u/10V_4
C5
65 EV_SP@0.22u/10V_4
66 EV_SP@0.22u/10V_4
C5
C5
51 EV_SP@0.22u/10V_4
C5
52 EV_SP@0.22u/10V_4
AC-coupling capactior
CZ-8Lane :Gen3(220nF) CH4222K9B04
CZL-4Lane:Gen1/2(100nF) CH4103K1B08
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
_TXP0 [11]
_TXN0 [11]
_TXP1 [11]
_TXN1 [11]
_TXP2 [11]
_TXN2 [11]
_TXP3 [11]
_TXN3 [11]
_TXP4 [11]
_TXN4 [11]
_TXP5 [11]
_TXN5 [11]
_TXP6 [11]
_TXN6 [11]
_TXP7 [11]
_TXN7 [11]
X4 : CARRIZO-L (G EN2)
X8 : CARRIZO (GEN3 )
D D
anta Computer Inc.
anta Computer Inc.
anta Computer Inc.
Qu
Qu
Qu
PROJECT :
PROJECT :
ze Documen t Number Rev
ze Documen t Number Rev
ze Documen t Number Rev
Si
Si
Si
Date: Sheet
Date: Sheet
1
2
3
4
5
6
Date: Sheet
4 PCIE I/F(1/7)
4 PCIE I/F(1/7)
4 PCIE I/F(1/7)
FP
FP
FP
PROJECT :
7
ZRZ
ZRZ
ZRZ
1Friday, March 06, 2015
1Friday, March 06, 2015
1Friday, March 06, 2015
of
of
of
24
24
24
8
1A
1A
1A
1
(C
PU)
M_
A_A[15:0][9]
A A
M_
A_BS#[2..0][9]
A_DM[7..0][9]
M_
A_DQS0[9]
M_
M_
VREF
M_
06
ACE CLOSE TO APU
M_
M_
A_DQS#0[9]
M_
A_DQS1[9]
A_DQS#1[9]
M_
A_DQS2[9]
M_
A_DQS#2[9]
M_
M_
A_DQS3[9]
A_DQS#3[9]
M_
M_
A_DQS4[9]
A_DQS#4[9]
M_
A_DQS5[9]
M_
A_DQS#5[9]
M_
M_
A_DQS6[9]
M_
A_DQS#6[9]
A_DQS7[9]
M_
A_DQS#7[9]
M_
A_CLK0[9]
M_
A_CLK0#[9]
M_
A_CLK1[9]
M_
A_CLK1#[9]
M_
A_RESET#[9]
A_EVENT#[9]
A_CKE0[9]
M_
A_CKE1[9]
M_
A_ODT0[9]
M_
A_ODT1[9]
M_
A_CS#0[9]
M_
A_CS#1[9]
M_
A_RAS#[9]
M_
A_CAS#[9]
M_
M_
A_WE#[9]
A_VRFDQ[9]
M_
C6
07
1000P/50V_4
B B
C C
.5VSUS
+1
21
R5
1K/F_4
22 *short_4
R5
R5
23
1K/F_4
D D
C6
0.1u/16V_4
PL
M_
A_A0
M_A_A1
M_
A_A2
M_A_A3
M_
A_A4
M_A_A5
M_
A_A6
M_A_A7
A_A8
M_
M_A_A9
A_A10
M_
M_A_A11
A_A12
M_
M_
A_A13
A_A14
M_
M_
A_A15
M_
A_BS#0
A_BS#1
M_
M_
A_BS#2
M_
A_DM0
A_DM1
M_
M_
A_DM2
A_DM3
M_
M_
A_DM4
A_DM5
M_
A_DM6
M_
A_DM7
M_
2
Channel A:CZ ONLY
AE28
MA
_ADD[0]
Y27
_ADD[1]
MA
Y29
MA
_ADD[2]
Y26
MA
_ADD[3]
W28
_ADD[4]
MA
W29
MA
_ADD[5]
W26
MA
_ADD[6]
U29
MA_ADD[7]
W25
MA
_ADD[8]
U26
MA
_ADD[9]
AG29
MA_ADD[10]
U27
MA
_ADD[11]
T28
MA
_ADD[12]
AK26
MA_ADD[13]
T26
MA
_ADD[14]/MA_BG[1]
T25
MA
_ADD[15]/MA_ACT_L
AG26
MA_BANK[0]
AG27
MA_BANK[1]
T29
MA
_BANK[2]/MA_BG[0]
E19
MA_DM[0]
D21
MA
_DM[1]
K21
_DM[2]
MA
F2
9
MA_DM[3]
AP2
8
_DM[4]
MA
AV2
6
_DM[5]
MA
22
AR
MA_DM[6]
BC
22
_DM[7]
MA
9
K2
_DM[8]
MA
9
H1
_DQS_H[0]
MA
G19
_DQS_L[0]
MA
2
B2
MA
_DQS_H[1]
A22
_DQS_L[1]
MA
3
F2
MA
_DQS_H[2]
E23
MA
_DQS_L[2]
G2
7
_DQS_H[3]
MA
F27
MA
_DQS_L[3]
AP2
5
MA
_DQS_H[4]
AP26
MA
_DQS_L[4]
AW
27
MA
_DQS_H[5]
AV2
7
MA
_DQS_L[5]
AV2
2
MA
_DQS_H[6]
22
AU
MA
_DQS_L[6]
BA2
1
MA
_DQS_H[7]
1
AY2
MA
_DQS_L[7]
L27
MA
_DQS_H[8]
L26
MA
_DQS_L[8]
AE2
5
MA_CLK_H[0]
6
AE2
MA
_CLK_L[0]
AD
26
MA
_CLK_H[1]
27
AD
MA_CLK_L[1]
AB2
8
MA
_CLK_H[2]
9
AB2
MA
_CLK_L[2]
AB2
5
_CLK_H[3]
MA
AB2
6
_CLK_L[3]
MA
N2
9
_RESET_L
MA
AE2
9
MA
_EVENT_L
7
P2
_CKE0
MA
P2
9
MA
_CKE1
AK27
MA
0_ODT[0]
26
AL
0_ODT[1]
MA
AH25
MA
1_ODT[0]
25
AL
1_ODT[1]
MA
AH
26
MA
0_CS_L[0]
AL29
0_CS_L[1]
MA
AH
29
1_CS_L[0]
MA
AL28
1_CS_L[1]
MA
AG
24
_RAS_L/MA_RAS_L_ADD[16]
MA
9
AK2
_CAS_L/MA_CAS_L_ADD[15]
MA
AH
28
MA
_WE_L/MA_WE_L_ADD [14]
9
B1
MA
_VREFDQ
2
T3
VREF
M_
FP
U28A
MEMORY A
4 REV 0.93
SP@FP4
MA
MA
MA
MA
MA
MA
MA
MA_DATA[7]
MA
MA_DATA[9]
MA
MA
MA_DATA[12]
MA
MA
MA_DATA[15]
MA
MA_DATA[17]
MA_DATA[18]
MA
MA
MA_DATA[21]
MA
MA
MA
MA
MA_DATA[26]
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA_DATA[47]
MA
MA_DATA[49]
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
_ZVDDIO_MEM_S
_DATA[0]
_DATA[1]
_DATA[2]
_DATA[3]
_DATA[4]
_DATA[5]
_DATA[6]
_DATA[8]
_DATA[10]
_DATA[11]
_DATA[13]
_DATA[14]
_DATA[16]
_DATA[19]
_DATA[20]
_DATA[22]
_DATA[23]
_DATA[24]
_DATA[25]
_DATA[27]
_DATA[28]
_DATA[29]
_DATA[30]
_DATA[31]
_DATA[32]
_DATA[33]
_DATA[34]
_DATA[35]
_DATA[36]
_DATA[37]
_DATA[38]
_DATA[39]
_DATA[40]
_DATA[41]
_DATA[42]
_DATA[43]
_DATA[44]
_DATA[45]
_DATA[46]
_DATA[48]
_DATA[50]
_DATA[51]
_DATA[52]
_DATA[53]
_DATA[54]
_DATA[55]
_DATA[56]
_DATA[57]
_DATA[58]
_DATA[59]
_DATA[60]
_DATA[61]
_DATA[62]
_DATA[63]
_CHECK[0]
_CHECK[1]
_CHECK[2]
_CHECK[3]
_CHECK[4]
_CHECK[5]
_CHECK[6]
_CHECK[7]
3
H17
M_
J17
F20
H20
E17
F17
K18
E20
A21
C21
C23
D23
B20
B21
B23
A23
G22
H22
E25
G25
J20
E22
H23
J23
F2
E2
J2
J2
H2
E2
G2
G29
AN26
AP2
AR26
AP2
AN29
AN
AR29
AR
AU
AV2
AU
AW
AU
AU
AW
AT
AV2
AW
AV2
AW
AR
AT
AR
AT
BB2
BB2
BB2
AY1
BA2
BC
BC21
BB2
K2
K28
N2
N28
J2
K25
L29
N2
AD
A_DQ0
M_A_DQ1
M_
A_DQ2
M_A_DQ3
M_
A_DQ4
M_A_DQ5
M_
A_DQ6
M_A_DQ7
M_A_DQ8
A_DQ9
M_
M_A_DQ10
A_DQ11
M_
M_
A_DQ12
A_DQ13
M_
M_
A_DQ14
A_DQ15
M_
A_DQ16
M_
M_
A_DQ17
A_DQ18
M_
M_
A_DQ19
A_DQ20
M_
M_
A_DQ21
A_DQ22
M_
M_
A_DQ23
6
M_
A_DQ24
7
A_DQ25
M_
6
A_DQ26
M_
7
A_DQ27
M_
5
M_
A_DQ28
6
M_
A_DQ29
8
A_DQ30
M_
A_DQ31
M_
M_
A_DQ32
9
A_DQ33
M_
M_
A_DQ34
4
A_DQ35
M_
A_DQ36
M_
27
A_DQ37
M_
M_
A_DQ38
27
M_
A_DQ39
26
A_DQ40
M_
9
M_
A_DQ41
25
A_DQ42
M_
25
M_
A_DQ43
29
A_DQ44
M_
28
A_DQ45
M_
26
A_DQ46
M_
25
A_DQ47
M_
3
A_DQ48
M_
23
A_DQ49
M_
0
A_DQ50
M_
20
A_DQ51
M_
23
M_
A_DQ52
23
A_DQ53
M_
20
A_DQ54
M_
20
A_DQ55
M_
3
M_
A_DQ56
2
A_DQ57
M_
0
M_
A_DQ58
9
A_DQ59
M_
3
A_DQ60
M_
23
A_DQ61
M_
M_
A_DQ62
1
M_
A_DQ63
6
6
9
5
29
MA
_ZVDDIO
24 CZ@39.2/F_4
R1
+1
.5VSUS
4
M_
A_DQ[0..63] [9]
5
M_
B_A[15:0][10]
M_
B_BS#[2..0][10 ]
M_
B_DM[7..0][10]
B_DQS0[10]
M_
M_
B_DQS#0[10]
M_
B_DQS1[10]
B_DQS#1[10]
M_
B_DQS2[10]
M_
B_DQS#2[10]
M_
M_
B_DQS3[10]
B_DQS#3[10]
M_
M_
B_DQS4[10]
B_DQS#4[10]
M_
B_DQS5[10]
M_
B_DQS#5[10]
M_
M_
B_DQS6[10]
M_
B_DQS#6[10]
B_DQS7[10]
M_
B_DQS#7[10]
M_
B_CLK0[10]
M_
B_CLK0#[10]
M_
B_CLK1[10]
M_
B_CLK1#[10]
M_
M_
B_RESET#[10]
B_EVENT#[10]
M_
B_CKE0[10]
M_
B_CKE1[10]
M_
B_ODT0[10]
M_
B_ODT1[10]
M_
B_CS#0[10]
M_
B_CS#1[10]
M_
B_RAS#[10]
M_
B_CAS#[10]
M_
M_
B_WE#[10]
B_VRFDQ[10 ]
M_
M_
B_A0
M_B_A1
M_
B_A2
M_B_A3
M_
B_A4
M_B_A5
M_
B_A6
M_B_A7
B_A8
M_
M_B_A9
B_A10
M_
M_B_A11
B_A12
M_
M_
B_A13
B_A14
M_
M_
B_A15
M_
B_BS#0
B_BS#1
M_
M_
B_BS#2
M_
B_DM0
B_DM1
M_
M_
B_DM2
B_DM3
M_
M_
B_DM4
B_DM5
M_
B_DM6
M_
B_DM7
M_
6
AW
AW
AW
AG31
AC30
AC31
AB32
AA32
AA33
AA31
AA30
W32
AG32
W33
AL31
W30
AH32
AG33
W31
AR
BC
BC
AR
AR33
BA2
AY2
BA2
AY2
AE3
AE3
AE3
AE3
AD
AD
AC
AC
AG
AL30
AM
AJ32
AM
AJ
AL32
AJ
AL33
AH
AK3
AJ
Y33
Y32
V32
D25
D29
E33
J3
30
30
30
26
N3
B2
A26
B3
A30
F3
E32
K3
J32
32
32
33
P3
N3
32
33
33
32
T3
30
U3
U3
32
33
33
30
33
31
A1
MB
_ADD[0]
_ADD[1]
MB
MB
_ADD[2]
MB
_ADD[3]
_ADD[4]
MB
MB
_ADD[5]
MB
_ADD[6]
MB_ADD[7]
MB
_ADD[8]
MB
_ADD[9]
MB_ADD[10]
MB
_ADD[11]
MB
_ADD[12]
MB_ADD[13]
MB
_ADD[14]/MB_BG[1]
MB
_ADD[15]/MB_ACT_L
MB_BANK[0]
MB_BANK[1]
MB
_BANK[2]/MB_BG[0]
MB_DM[0]
MB
_DM[1]
_DM[2]
MB
3
MB_DM[3]
_DM[4]
MB
_DM[5]
MB
MB_DM[6]
_DM[7]
MB
3
_DM[8]
MB
6
_DQS_H[0]
MB
_DQS_L[0]
MB
0
MB
_DQS_H[1]
_DQS_L[1]
MB
2
MB
_DQS_H[2]
MB
_DQS_L[2]
2
_DQS_H[3]
MB
MB
_DQS_L[3]
MB
_DQS_H[4]
MB
_DQS_L[4]
MB
_DQS_H[5]
MB
_DQS_L[5]
9
MB
_DQS_H[6]
9
MB
_DQS_L[6]
5
MB
_DQS_H[7]
5
MB
_DQS_L[7]
2
MB
_DQS_H[8]
2
MB
_DQS_L[8]
3
MB_CLK_H[0]
2
MB
_CLK_L[0]
0
MB
_CLK_H[1]
1
MB_CLK_L[1]
MB
_CLK_H[2]
MB
_CLK_L[2]
_CLK_H[3]
MB
_CLK_L[3]
MB
3
_RESET_L
MB
MB
_EVENT_L
2
_CKE0
MB
3
MB
_CKE1
MB
0_ODT[0]
0_ODT[1]
MB
MB
1_ODT[0]
1_ODT[1]
MB
MB
0_CS_L[0]
0_CS_L[1]
MB
1_CS_L[0]
MB
1_CS_L[1]
MB
_RAS_L/MB_RAS_L_ADD[16]
MB
2
_CAS_L/MB_CAS_L_ADD[15]
MB
MB
_WE_L/MB_WE_L_ADD [14]
9
MB
_VREFDQ
FP
MEMORY B
4 REV 0.93
U28I
SP@FP4
MB
MB
MB_DATA[12]
MB
MB
MB_DATA[15]
MB
MB_DATA[17]
MB_DATA[18]
MB
MB
MB_DATA[21]
MB
MB
MB
MB
MB_DATA[26]
MB
MB
MB
MB
MB
MB
MB
MB
MB
MB
MB
MB
MB
MB
MB
MB
MB
MB
MB
MB
MB_DATA[47]
MB
MB_DATA[49]
MB
MB
MB
MB
MB
MB
MB
MB
MB
MB
MB
MB
MB
MB
MB
MB
MB
MB
MB
MB
MB
MB
MB
_ZVDDIO_MEM_S
MB
_DATA[0]
_DATA[1]
MB
MB
_DATA[2]
MB
_DATA[3]
_DATA[4]
MB
MB
_DATA[5]
MB
_DATA[6]
MB_DATA[7]
MB
_DATA[8]
MB_DATA[9]
_DATA[10]
_DATA[11]
_DATA[13]
_DATA[14]
_DATA[16]
_DATA[19]
_DATA[20]
_DATA[22]
_DATA[23]
_DATA[24]
_DATA[25]
_DATA[27]
_DATA[28]
_DATA[29]
_DATA[30]
_DATA[31]
_DATA[32]
_DATA[33]
_DATA[34]
_DATA[35]
_DATA[36]
_DATA[37]
_DATA[38]
_DATA[39]
_DATA[40]
_DATA[41]
_DATA[42]
_DATA[43]
_DATA[44]
_DATA[45]
_DATA[46]
_DATA[48]
_DATA[50]
_DATA[51]
_DATA[52]
_DATA[53]
_DATA[54]
_DATA[55]
_DATA[56]
_DATA[57]
_DATA[58]
_DATA[59]
_DATA[60]
_DATA[61]
_DATA[62]
_DATA[63]
_CHECK[0]
_CHECK[1]
_CHECK[2]
_CHECK[3]
_CHECK[4]
_CHECK[5]
_CHECK[6]
_CHECK[7]
7
A25
M_
C25
C27
D27
B24
B25
B27
A27
A29
C29
B32
D32
B28
B29
A31
C31
E30
E31
G33
G32
C33
D33
G30
G31
J3
J3
L33
L32
H3
H3
L30
L31
AN31
AP3
AT32
AU
AN33
AN
AR31
AT
AU
AV3
BA3
AY3
AU
AU
AW
AY3
BC
BB3
BB2
AY2
BB3
BA3
BC
BB2
BB2
BB2
BB2
AY2
BA2
BC
BC25
BB2
N3
N31
R3
R32
M3
M33
R3
R3
AF
B_DQ0
M_B_DQ1
M_
B_DQ2
M_B_DQ3
M_
B_DQ4
M_B_DQ5
M_
B_DQ6
M_B_DQ7
M_B_DQ8
B_DQ9
M_
M_B_DQ10
B_DQ11
M_
M_
B_DQ12
B_DQ13
M_
M_
B_DQ14
B_DQ15
M_
B_DQ16
M_
M_
B_DQ17
B_DQ18
M_
M_
B_DQ19
B_DQ20
M_
M_
B_DQ21
B_DQ22
M_
M_
B_DQ23
0
M_
B_DQ24
1
B_DQ25
M_
B_DQ26
M_
B_DQ27
M_
2
M_
B_DQ28
3
M_
B_DQ29
B_DQ30
M_
B_DQ31
M_
M_
B_DQ32
2
B_DQ33
M_
M_
B_DQ34
32
B_DQ35
M_
B_DQ36
M_
32
B_DQ37
M_
M_
B_DQ38
33
M_
B_DQ39
30
B_DQ40
M_
2
M_
B_DQ41
3
B_DQ42
M_
2
M_
B_DQ43
33
B_DQ44
M_
31
B_DQ45
M_
31
B_DQ46
M_
3
B_DQ47
M_
31
B_DQ48
M_
0
B_DQ49
M_
8
B_DQ50
M_
7
B_DQ51
M_
2
M_
B_DQ52
1
B_DQ53
M_
29
B_DQ54
M_
9
B_DQ55
M_
7
M_
B_DQ56
6
B_DQ57
M_
4
M_
B_DQ58
3
B_DQ59
M_
7
B_DQ60
M_
27
B_DQ61
M_
M_
B_DQ62
5
M_
B_DQ63
0
3
2
0
1
32
MB
_ZVDDIO
15 39.2/F_4
R5
+1
.5VSUS
8
M_
B_DQ[0..63] [10]
Qu
Qu
Qu
anta Computer Inc.
anta Computer Inc.
anta Computer Inc.
PROJECT :
PROJECT :
ze Document Number Rev
ze Document Number Rev
ze Document Number Rev
Si
Si
Si
FP
FP
FP
4 DDR3 I/F(2/7)
4 DDR3 I/F(2/7)
4 DDR3 I/F(2/7)
Date: Sheet
Date: Sheet
1
2
3
4
5
6
Date: Sheet
7
PROJECT :
ZRZ
ZRZ
ZRZ
of
of
of
34
34
34
8
1A
1A
1A
1Friday, March 06, 2015
1Friday, March 06, 2015
1Friday, March 06, 2015
1
PU)
(C
VD
D_18
R496 300_4
R439 300_4
A A
APU_PWRGD
_RST#
APU
Serial VID
D_18
VD
R4
65
*1K_4
B B
64
R4
*220_4
VF
R4
59
*1K_4
58
R4
*220_4
IX MODE
R4
R4
91
60
*2.2K_4
*1K_4
APU
APU_SVC
APU_SVD
APU
_PWRGD_SVID_R EG
90
R4
*220_4
Override table (VDD)
VID
SVDSVC
0
0
0
1100.9V
11
(Hardware Debug Tool ) Connector
HDT
C C
D_18
VD
R5
20
HDT@1K/F_4
APU
C6
13
D D
HDT@0.01u/50V_4
_TRST#
D_18
VD
19 HDT@33_4
R5
R5
R5
R5
D_18
VD
_SVT
ot Voltage
Bo
1V
1.
1.0V
0.
8V
18 HDT@10K_4
17 HDT@10K_4
16 HDT@10K_4
HDT
R4
71
*CZ@1K_4
R4
70
*CZ@220_4
_TRST#
2
R4
79
*CZ@1K_4
R4
78
*CZ@220_4
CN8
1
CP
U_VDDIO
3
GN
5
GN
7
GN
9
CP
U_TRST_L
11
U_DBRDY3
CP
13
U_DBRDY2
CP
15
U_DBRDY1
CP
17
GN
19
U_VDDIO
CP
DT@HDT
*H
PLA
D
D
D
D
DP DEMUX
eDP
R4
72
*CZ@1K_4
GF
X_SVT
GFX_SVC
GFX_SVD
APU
_PWRGD_SVID_R EG[34,35]
FOR DEBUG, PLACE THESE CAPS CLOSE TO APU
CE HDT+ HEADER ON TOP
CP
U_PWROK_BUF
U_RST_L_BUF
CP
CP
CP
CP
CP
APU
APU
APU
GF
X_SVT[35]
GF
GF
CP
U_TCK
CP
U_TMS
U_TDI
CP
CP
U_TDO
U_DBRDY0
U_DBREQ_L
U_PLLTEST0
U_PLLTEST1
_SVT[34]
_SVC[34]
_SVD[34]
X_SVC[35]
X_SVD[35]
APU
C5
89
*27p/50V_4
APU
APU
2
4
6
8
10
12
14
16
18
20
3
DP
2_TX0[19]
DP
2_TX0#[19]
2_TX1[19]
DP
DP
2_TX1#[19]
MUX_TX0[18]
MUX_TX0#[18]
MU
X_TX1[18]
X_TX1#[18]
MU
MU
X_TX2[18]
MUX_TX2#[18]
MU
X_TX3[18]
X_TX3#[18]
MU
ED
P_TX0[17]
EDP_TX0#[17]
ED
P_TX1[17]
ED
P_TX1#[17]
*APU_SVT & GFX_SVT need 0R in power side
No
te: Place resistor for SVT on VRM side (Power side)
R4
61 *short_4
R4
57 *short_4
67 *shortCZ@0_4
R4
69 *shortCZ@0_4
R4
89 *short_4
R4
92 HDT@0_2
R4
_PWRGD_D
APU
_PWRGD
_RST#
APU
C5
72
*27p/50V_4
U2
9
1
_RST#
_PWRGD_D
1A
2
3
1Y
D
C
GN
VC
2Y
2A
HDT@SN74LVC2G07DCKR
APU
_TCK
APU
_TMS
HDT
R5
_APU_TDI
44 HDT@0_4
_TDO
APU
_PWROK_BUF
APU
_RST_L_BUF
APU
APU
_DBRDY
HDT
R5
_DBREQ#
_TEST19
_TEST18
39 HDT@33_4
C6
*HDT@0.01u/5 0V_4
24
APU
APU
APU
APU
X_SVC_R
GF
GF
X_SVD_R
APU
APU
APU
APU
APU
APU
APU
APU
APU
APU
APU
APU
APU
VD
6
5
4
APU
APU
4
B6
A6
D7
C7
A7
B7
D9
C9
A2
A3
B4
A4
D5
C5
A5
B5
E2
E1
E3
E4
D1
D2
C1
B1
C1
D1
_SVC_R
D1
_SVD_R
B1
B1
A1
B1
_SIC
C1
_SID
D1
_RST#
C1
_PWRGD
A1
_PROCHOT#
B1
_ALERT#
H1
_TDI
H1
_TDO
D1
_TCK
G1
_TMS
J1
_TRST#
C1
_DBRDY
A1
_DBREQ#
D_18
C6
14
HDT@0.1U/16V/X7R_4
APU
_RST_L_BUF
_PWROK_BUF
APU
R5
33 HDT@1K/F_4
R5
32 HDT@1K/F_4
_TDI
R5
43
42 HDT@1K/F_4
R5
41 HDT@1K/F_4
R5
_DBREQ#
R5
40 HDT@1K/F_4
23
C6
HDT@0.01u/50V_4
Soldermask open ings for all bottom side vias/TPs under FP4
2_TXP[0]
DP
2_TXN[0]
DP
2_TXP[1]
DP
DP
2_TXN[1]
DP
2_TXP[2]
2_TXN[2]
DP
DP2_TXP[3]
DP
2_TXN[3]
1_TXP[0]
DP
DP
1_TXN[0]
DP
1_TXP[1]
DP
1_TXN[1]
DP
1_TXP[2]
1_TXN[2]
DP
DP1_TXP[3]
DP
1_TXN[3]
0_TXP[0]
DP
DP0_TXN[0]
DP
0_TXP[1]
DP0_TXN[1]
0_TXP[2]
DP
0_TXN[2]
DP
DP0_TXP[3]
DP
0_TXN[3]
5
T0
SV
7
SVC0
9
D0
SV
5
T1
SV
6
SV
C1
8
D1
SV
CZL:3V_S0
8
SIC
CZL:3V_S0
7
SI
D
5
SET_L
RE
9
PW
ROK
5
PR
OCHOT_L
7
AL
ERT_L
5
TD
I
4
O
TD
3
TC
K
5
TMS
4
TR
ST_L
3
DB
RDY
1
REQ_L
DB
DISPLAY/SVI2/JTAG/TEST
2 : CZ only
DP
CZ
:1.8_S0
U28C
CZ:1.8_S0 CZL:3V_S0
(XX,PD)
(XX,PD)
CZ:1.8_S0 CZL:3V_S0
CZL:3V_S0
CZL:3V_S0
FP
4 REV 0.93
FP4
SP@
_AUX_ZVSS
DP
DP
TE
MPINRETURN
_STEREOSYNC/TEST36
DP
VD
DCR_GF X_SENS E
VD
DCR_NB_ SENSE
DCR_CP U_SENSE
VD
VD
VS
DP
DP_BLON
DP
_VARY_BL
DP
DP
DP
DP
DP
DP
DP_SENS E
S_SENSE
CO
D_18
VD
HDT@1K/F_4
_ZVSS
_DIGON
2_AUXP
2_AUXN
DP2_HPD
1_AUXP
1_AUXN
DP
0_AUXP
0_AUXN
DP
RSVD_1
TE
MPIN0
TEMPIN1
TE
MPIN2
TE
TE
TE
ST28_H
TE
RE_PWM_PROCHOT#[29,30,34,35]
5
1_HPD
0_HPD
TE
TE
TE
TE
TEST17
TEST11
TEST18
TE
ST28_L
TE
TE
A9
DP
_ZVSS
B9
DP
_AUX_ZVSS
G5
G6
APU_DIGON
1
F1
APU
_BLPWM
H9
G9
E9
F7
E7
F5
F8
E8
G8
K2
4
VD
RS
E15
APU_TEMPIN0
4
E1
_TEMPIN1
APU
E1
2
APU
_TEMPIN2
4
F1
APU
_TEMPRETURN
AK2
4
APU_TEST410
ST410
24
AL
_TEST411
APU
ST411
P2
4
_TEST4
APU
TE
ST4
4
N2
APU
AN
24
AB8
Y9
B1
0
1
D1
A1
0
1
C1
B1
1
4
A1
B1
4
A1
3
B1
3
6
P2
1
E1
7
A1
1
H1
2
J1
2
G1
18
AY
2
H1
_TEST5
_TEST14
APU
APU
_TEST15
APU_TEST16
_TEST17
APU
_TEST11
APU
APU
_TEST18
APU
_TEST19
_TEST28_H
APU
APU
_TEST28_L
APU
_TEST31
DP_STEREOSYNC
APU
_VSS_SENSE
ST5
TE
ST6
TE
ST9
TE
ST10
ST14
ST15
ST16
ST19
ST31
ST37
R4
R4
TP
46
37
TP
32
TP
43
TP
R4
40 *short_4
R4
43 *shortCZ@0_4
R5
06 *0_4
CRB CLOSE TO APU
3V_S0
5V_S0
TH
ERM_ALERT#[28]
(G991 Internal PU)
37 2K/F_4
36 150/F_4
_DISP_BLEN [17,29]
APU
DP
2_AUX [19]
2_AUX# [19]
DP
2_HPD [19]
DP
MUX_AUX [18]
MUX_AUX# [18]
MUX_HPD [18]
P_AUX [17]
ED
ED
P_AUX# [17]
ED
P_HPD [17]
TP12
TP
TP
TP
TP
8
TP7
TP10
TP
9
TP36
TP
39
TP
38
V
+3
R4
94
10K_4
6
40
5
4
R448 *0_4
R4
35 *1K/F_4
34 *1K/F_4
R4
46 *1K/F_4
R4
R4
47 *1K/F_4
R445 1K/F_4
R4
44 1K/F_4
46 *39.2/J_4
R1
R1
45 *39.2/J_4
R4
52 1K/F_4
R4
53 *1K/F_4
83 *1K/F_4
R4
82 *1K/F_4
R4
APU
APU
APU
APU
APU
APU
APU
0_18S0
33S
Q4
0
5
2
6
CZ : 1.8V
CZL : 3.3V
_BLPWM
APU
APU
_DIGON
: 1.8V
CZ
CZL : 3.3V
DP
DP
D_18
VD
0_18S0
33S
VD
D_18
_VDDGFX_RUN_FB_H [35]
_VDDNB_RUN_FB_H [34]
_VDD_RUN_FB_H [34]
_VDDP_RUN_FB_H [32]
_VDD_RUN_FB_L [34]
_VDDGFX_RUN_FB_L [35]
_VDDP_RUN_FB_L [32]
43
_PROCHOT#
APU
1
_ALERT#
APU
1
2_AUX
2_AUX#
TEST CONN ECTION TBD
M_
PU ->enable HDMI video/audi o
PD->Disable HDMI audio
(APU_VDD_RUN_FB_L = APU_VDDNB_RUN_FB_L)
PJT138K
SMBUS (Internal Thermal sensor)
0_18S0
33S
Q4
2
2N
D_MBCLK[12,29]
3V_S5
(PU in EC side )
D_MBDATA[12,29]
2N
5
2
6
PJT138K
43
_SIC
APU
1
APU
_SID
7
33S
0_18S0
2
7
Q3
PJA138K
R410*short_4
R6
46 *CZ@100K_4
R6
47 *CZ@100K_4
33S
0_18S0
VD
D_18
+3
V
+3
V
R4
26
10K_4
3
R5
02 1K/F_4
08 1K/F_4
R5
97 1K/F_4
R4
93 1K/F_4
R4
R5
12 CZ@0_4
05 CZL@0_4
R5
LCD 3.3V
APU
APU
:>1.5V
EN
8
_DISP_PWM [17]
_DISP_ON [17]
+3V
_SIC
APU
_SID
APU
_ALERT#
APU
_PROCHOT#
APU
33S
0_18S0
anta Computer Inc.
anta Computer Inc.
anta Computer Inc.
Qu
Qu
Qu
PROJECT :
PROJECT :
Si
Si
Size Document Number Rev
ze Document Number Rev
ze Document Number Rev
4 DISPLAY/MISC(3/7)
4 DISPLAY/MISC(3/7)
4 DISPLAY/MISC(3/7)
FP
FP
FP
Date: Sheet
Date: Sheet
1
2
3
4
5
6
Date: Sheet
7
PROJECT :
ZRZ
ZRZ
ZRZ
1Friday, March 06, 2015
1Friday, March 06, 2015
1Friday, March 06, 2015
44
44
44
of
of
of
8
1A
1A
1A
(C
1
PU)
2
3
4
5
6
7
8
VDD_18_S5
(CZ,CZL)
R3
82
22K_4
PC
IE_WAKE#
SCL1
SDA1
LR
_LED_L
S0
A3
SWON#
DNB
US
B_OC1#
US
B_OC2#
USB_OC3#
AGPIO4
PIO8
AG
PIO40
AG
D29 RB500V-40
10ms RC-delay (PU,PU)
C5
26
1u/10V_4
PC
A A
V_S5
+3
R3
R8
R79 CZL@10K_4
R78 10K/F_4
R8
R7
R3
R3
R6
R93 CZL@10K/F_4
R8
R8
H_RSMRST#[29]
92 NIOAC@10K/F_4
1 CZL@10K_4
0 10K/F_4
7 10K/F_4
89 10K/F_4
96 10K/F_4
64 10K/F_4
5 CZ@10K/F_4
6 CZ@10K/F_4
PL
TRST#[21,23,29]
IERST#[11,17,20,21]
PC
IE_LAN_WAKE#[12,20,21]
PC
_S5_MUX_CTRL[39]
APU
SI
SI
SI
+3V
R4
76 2.2K_4
R4
66 2.2K_4
77 CZ@10K/F_4
R4
73 CZ@10K/F_4
R4
R4
98 CZL@10K/F_4
R504 CZL@10K/F_4
R5
00 CZ@10K/F_4
B B
86 *10K/F_4
R3
V_S5
+3
J1
1 2
HORT_ PAD
*S
R6
74 CZ@1K_4
R4
30 CZ@1K_4
R6
75 CZ@1K_4
76 CZ@1K_4
R6
32 *10K/F_4
R4
05 CZ@10K/F_4
R1
R1
11 CZ@10K/F_4
D_18
VD
R4
49 CZ@2.2K_4
R4
55 CZ@2.2K_4
25 SP@10K_4
R4
20 SP@10K_4
R4
CZ :12C Touch interface:2.2K(CS22202JB18)
USB interface:10k(CS31002FB26)
CZL:NC
C C
Te
st mode setting (Follow AMD's suggestion)
+3
V_S5
,no in stall b y default
NC
R8
7 *2.2K_4
3 *1K_4
R8
83 *2.2K_4
R3
CL
K_SCLK
K_SDATA
CL
K_REQ3
CL
PC
IE_REQ_GPU#_R
AGPIO64
AGPIO66
AG
PIO69
SYS_
RST#
SYS_
RST# internal
40K pull up
AC
Z_RST#_R
AC
Z_BCLK_R
Z_SYNC_R
AC
Z_SDOUT_R
AC
H_AZ_CODEC_SDIN0
PC
AZ
_SDIN1
AZ
_SDIN2
I2
C_SCL_TP
I2
C_SDA_TP
C_SCL_TS
I2
C_SDA_TS
I2
APU
_TEST0
_TEST1
APU
APU
_TEST2
R8
8 15K_4
0 15K_4
R9
84 15K_4
R3
PC
IE_REQ_LAN#[20]
PCIE_CLKREQ_WL AN#[21]
PC
IE_REQ_GPU#[12]
PC
H_AZ_CODEC_BITCLK[22]
H_AZ_CODEC_SDIN0[22]
PC
H_AZ_CODEC_RST#[22]
PC
PC
H_AZ_CODEC_SYNC[22 ]
PC
H_AZ_CODEC_SDOUT[22]
TEST2 TEST1 TEST0 Description
0
00
D D
0
0
0
1
1
TMS
1TMS
1
FCH TAP accessible from APU when TAPEN is asserted
FCH JTAG pins are overloaded for multiple
functions, in this configuration the FCH JTAG are
used as non-JTAG pins
1
Reserved
X
Reserved
FCH JTAG multi-function pins are configured as
JTAG pins, in this configuration the FCH TAP
0
can be accessed from FCH JTAG pins
Use on ATE only
1
Yuba JTAG enabled
2
73 150P/50V_4
DNBSWON#[29]
O_A20GATE[29]
O_EXT_SCI#[29]
O_EXT_SMI#[29]
C5
C569 150P/50V_4
SU
SB#[29]
SUSC#[29]
KBR
ST#[29]
R4
50 33_4
R4
19 33_4
PC
H_RSMRST#_R
SYS_
R3
90 *short_4
C534 *EV@100P/50V_4
SYS_
PCIE_WAKE#
S0
A3
APU
_TEST0
APU
_TEST1
_TEST2
APU
ACPRESENT[30] ACCEL_INTA [23]
LR
_LED_L
69
TP
CL
R4
US
US
US
41 33_4
R4
R4
31 33_4
33 33_4
R4
38 33_4
R4
C_SCL_TP[27]
I2
C_SDA_TP[27]
I2
C_SCL_TS[17]
I2
I2
C_SDA_TS[17]
RT
C_CLK[6]
SU
S_CLK[21]
C5
32.
768KHZ
C5
74 *EV@0_4
B_OC1#[25]
B_OC2#[25]
B_OC3#[25]
6818p/50V_4
12
Y4
6722P/50V_4
PCIE_REQ_GPU#_R
Z_BCLK_R
AC
AZ
_SDIN1
AZ
_SDIN2
Z_RST#_R
AC
Z_SYNC_R
AC
Z_SDOUT_R
AC
66 *33_4
R6
09
R4
20M_4
K_REQ3
LP
C_RST#_R
PCIE_RST#
PWRGD
RST#
32K
_X1
_X2
32K
BB1
2
LP
AN7
P
AE4
RS
AE1
PW
9
BC
PW
AF
2
SYS_
2
AG
WAKE_L/AGPIO2
AK7
SL
5
AH
SL
AE8
S0
AH8
S
AH
6
TE
AK8
TE
AE3
TE
15
AY
ESPI_RESET_L/KBRST_L/AGPIO129
BC
19
GA
7
AD
LP
BB1
3
LP
AG
3
AC
5
AD
IR
AL
8
IR_TX1/USB_OC6_L/AGPIO14
AN8
IR
AE2
IR
BC
15
CL
7
BB1
CLK_REQ1_L/AGPIO115
BC
17
CLK_REQ2_L/AGPIO116
8
BB1
CL
BB1
6
CL
9
AH
US
AG
1
USB_OC 1_L/ TDI/ AGPIO 17
AH
2
US
AL
9
US
AU
6
AZ
8
AR
AZ
AP6
AZ
5
AR
AZ_SDIN2 /I2S _DATA_M IC[1]
9
AU
AZ
9
AT
AZ
AR
7
AZ
BB1
0
I2
BB9
I2
BB7
I2
7
BC
I2
7
AG
RT
1
AT
X3
AT
2
X3
3V_S5? S0?
C_RST_L
3V_S5
CIE_RST_L/EGPIO26
1.8V_S5
MRST_L
3V_S5
R_BTN_L/AGPIO0
CZ:3V_S0 CZL:1.8V_S0
R_GOOD
RESET_L/AGPIO1
P_S3_L
P_S5_L
3V_S5
A3_GPIO/AGPIO10
CZ ONLY
5_MUX_CTRL/EGPIO42
(,PD)
ST0
(,PD)
ST1/TMS
(,PD)
ST2
20IN/AGPIO126
C_PME_L/AGPIO22
C_SMI_L/AGPIO86
_PRES/ USB_OC 4_L/ IR_R X0/AGP IO23
_TX0/USB_OC5_L/AGPIO13
_RX1/AGPIO15
_LED_L/LLB_L/AGPIO12
K_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92
K_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131
K_REQG_L/OSCIN/EGPIO132
B_OC0 _L/ TRST_L /AGPI O16
B_OC2 _L/ TCK/AG PIO1 8
B_OC3 _L/ TDO/AGP IO24
_BITCL K/I2 S_BCL K_MI C
_SDIN0/ I2S_ DATA_MI C[0]
_SDIN1/ I2S_ LR_P LAYBAC K
_RST_L /I2S _LR_ MIC
_SYNC/I 2S_B CLK_ PLAYBAC K
_SDOUT/I 2S_D ATA_PLAY BACK
C0_SCL/EGPIO145
C0_SDA/EGPIO146
CZ:1.8V_S0 CZL:3V
C1_SCL/EGPIO147
C1_SDA/EGPIO148
3V_S5
(PU,)
CCLK
2K_X1
2K_X2
(,PD)
SYS PWRGD
D9
D8
D1
Q3
8
*1N4148WS
*1N4148WS
0 1N4 148WS
HW
C5
77
*CZ@1U/10V_4
PG[29]
VD
DGFX_EN [35]
RST#[6]
SYS_
SB#
SU
ROK_EC[29]
PW
0 *CZ@RB500V-40
D3
80 CZ@47K_4
VR
ON[29,34]
DGFX_PD
VD
3
88 CZ@10K/F_4
R4
R4
2
78
C5
CZ@1000P/50V_4
4
3
CZ@2N7002K
1
U28D
ACPI/SD /AZ/GP IO/RT C/I2C /UART/MI SC
(PU,PU)
(PU,PU)
(PU,PU)
(PD,PU)
3V_S0
(PU,PU)
3V_S0
(PU,PU)
(PU,PU)
3V_S5
(PU,PU)
3V_S0
CZ ONLY
(PU,PU)
(PU,)
(PU,PU)
(PU,PU)
3V_S5
(PU,PU)
(,PU)
(PU,PU)
(PU,PU)
(,PU)
3V_S5
(,PD)
(,PD)
(,PD)
S5
CZ:1.8V_S0 CZL:1.8V_S5
CZ:1.8V_S0 CZL:1.8V_S5
3V_S0
(PU,)
(PU,PU)
(PU,PU)
(PU,PU)
(PU,PU)
4 REV 0.93
FP
SP@FP4
+3
(,PU)
(,PU)
CZ:3V_S5 CZL:3V_S0
1.8V_S0
1.8V_S0
1.8V_S0
V_S5
3
2
1
5
(PD,PU)
3V_S0
3V_S0
3.3V_S0
3.3V_S5
(PD,PU)
(PD,PU)
SD0_PWR_CTRL/AGPIO102
SC
SD
SD
(PU,PU)
(PD,)
CZ:3V_S5 CZL:3V_S0
(PD,PU)
(PD,PU)
(PD,PU)
(PD,PU)
(PD,PU)
(PD,)
(PU,)
(PU,)
(PU,)
(PU,)
(PD,PU)
(PD,PU)
3.3V_S0
3.3V_S0
(PD,PU)
PIO71/ SGPI O_DATAOUT
AG
AG
(PD,PU)
(PD,PU)
(PD,PU)
(PD,)
(PD,)
(PU,PU)
(PU,PU)
(PU,)
(PU,)
1.8V_S0
UA
RT1_CT S_L/ BT_I 2S_ BCLK /EGPI O14 0
UA
RT1_RX D/BT _I2S _SDI /EGP IO14 1
UART1_TX D/BT_ I2S _SDO /EGPI O14 3
RT1_I NTR/BT_ I2S _LRC LK/ AGPIO1 44
UA
R2
06
100K_4
3
2
Q2
2
1
2N7002K
0_WP/EGPIO101
SD
S
D0_CD/AGPIO25
SD
0_CLK/EGPIO95
0_CMD/EGPIO96
SD
SD0_DATA0/EGPIO97
SD
0_DATA1/EGPIO98
SD
0_DATA2/EGPIO99
0_DATA3/EGPIO100
SD
SD
0_LED/EGPIO93
L0/I2C2_SCL/EGPIO113
A0/I2C2_SDA/EGPIO114
SC
L1/I2C3_SCL/AGPIO19
A1/I2C3_SDA/AGPIO20
PIO6/L DT_RS T
AG
AG
PIO7/L DT_PW ROK
DGFX_P D/AGPI O39
VD
PIO66/ SHUTDOW N_L
AG
PIO68/ SGPI O_CLK
AG
AGPIO69 /SGPI O_LOAD
PIO72/ SGPI O_DATAIN
SPKR
/AGPIO91
LINK/USB_OC7_L/AGPIO11
B
GE
NINT1_L/AGPIO89
GE
NINT2_L/AGPIO90
FA
NIN0/AGPIO84
NOUT0/AGPIO85
FA
UA
RT0_CT S_L/ EGPI O135
UA
RT0_RX D/EG PIO1 36
UA
RT0_RT S_L/ EGPI O137
RT0_TX D/EGP IO1 38
UA
UA
RT0_I NTR/AGP IO13 9
RT1_RT S_L/ EGPI O142
UA
V
+3
R1
89
CZ@4.7K_4
C3
39
0.22u/10V_4
1
Q2
2N7002K
AG
AG
AGPIO5
AGPIO8
AG
AG
AGPIO64
AGPIO65
PIO3
PIO4
PIO9
PIO40
VD
BB2
BB5
2
BC
BB4
AY
5
3
BC
BA3
BC5
BA5
BB6
BA15
17
AY
5
AG
AG
4
5
AL
AL
6
1
AJ
AJ
3
1
AH
AJ
4
AK5
8
AD
AG
8
15
AW
AU
15
AT
15
12
AU
AT
14
AR
14
BC
13
BA1
7
5
AN
4
BB1
9
BA1
18
BC
BB1
9
AY
9
8
AW
AV5
AV8
9
AW
1
AV1
7
AU
AT
11
AR
11
AP9
D_18
R1
88
CZL@4.7K_4
87 *short_4
R1
TP
TP
BOARD_ID0
BO
ARD_ID1
BO
ARD_ID2
ARD_ID3
BO
SC
L1
A1
SD
GEVENT2#
AG
PIO4
_resume
S3
AG
PIO8
AG
PIO40
PIO64
AG
AGPIO66
DGPU_PWREN_A
AG
PIO69
6
34
35
R8
4 10 K_4
TP
6
PWRGD
SYS_
DG
PU_RST_L [11]
BOARD_ID4 [1 7]
CL
K_SCLK [9,10,23]
K_SDATA [9,10,23]
CL
VENT2# [6]
GE
DGFX_PD [29]
VD
H_ODD_EN [24]
PC
OD
D_PLUGIN# [24]
SPKR
[22]
PIO11 [6]
AG
PE_
PWRGD [38]
APU
_TP_INT# [17]
_I2C_INT# [27]
APU
V
+3
R1
16
*EV@100K/F_6
CZ : mount R659
CZL: mount D2
R6
59 EV_SP@0_4
PU_PWREN[38]
DG
BO
+3
V
ARD ID
ZYV
BOARD_ID4 Depend on cable => always PU, PD DNI
Touch cable PIN2 => NC
non-Touch cable PIN2 => GND
R1
09 SP@10K_4
R1
04 SP@10K_4
R1
06 SP@10K_4
07 IOAC@10K_4
R1
R4
10K_4
BO
BO
BO
BO
BO
GPIO
BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3
BOARD_ID4
Si
Si
Si
ze Document Number Rev
ze Document Number Rev
ze Document Number Rev
4 GPIO/AZ/I2C/SD/UARTS(4/7)
4 GPIO/AZ/I2C/SD/UARTS(4/7)
4 GPIO/AZ/I2C/SD/UARTS(4/7)
FP
FP
FP
Date: Sheet
Date: Sheet
Date: Sheet
7
dTPM
dGPU
non-G sensor
IOAC non-IOAC
Touch
Qu
Qu
Qu
PROJECT :
PROJECT :
PROJECT :
D2
SP@RB500V-40
EV_
93
C1
EV@0.1u/16V_4
ARD_ID0
ARD_ID1
ARD_ID2
ARD_ID3
ARD_ID4
High
anta Computer Inc.
anta Computer Inc.
anta Computer Inc.
DG
R1
10 SP@10K_4
R1
03 SP@10K_4
R1
02 SP@10K_4
9 NIOAC@10K_4
R9
*10K_4
R5
Low
iTPM
UMA
G sensor
non-Touch
ZRZ
ZRZ
ZRZ
54
54
54
8
PU_PWREN_A
44
R6
*EV@1M_4
1Wednesday, March 18, 2015
1Wednesday, March 18, 2015
1Wednesday, March 18, 2015
of
of
of
1A
1A
1A
1
PU)
(C
SAT
A_TXP0[24]
SAT
HDD
OD
H:SSD
L:ODD
CL
CL
CLK_PCIE_LANP[20]
CLK_PCIE_LANN[20]
CL
CL
K_PCIE_VGAP[11]
K_PCIE_VGAN[11]
K_PCIE_WLANP[21]
K_PCIE_WLANN[21]
C5
30 6p/50V_4
C5
29 6p/50V_4
D
DE
48M
A A
B B
C5
74 *15P/50V_4
C5
75 *15P/50V_4
76 *15P/50V_4
C5
EMI reserve
C C
ST
RAPS PINS
A_TXN0[24]
SATA_RXN0[24]
SAT
A_RXP0[24]
A_TXP1[24]
SAT
SAT
A_TXN1[24]
SATA_RXN1[24]
SAT
A_RXP1[24]
VD
DP_0.95V
VSLP_HDD[24]
+3V
DE
VSLP_ODD[24]
DEVSLP_ODD PU in ODD connector side
R4
R405 *shortEV@0_4
R3
R3
R3
R3
2
13
Y2
Hz
4
CL
K_PCI_775[29]
PC
LK_TPM[23]
K_LPC_DEBUG[21]
CL
C_LAD0[21,23,29]
LP
C_LAD1[21,23,29]
LP
LP
C_LAD2[21,23,29]
LP
C_LAD3[21,23,29]
LP
C_LFRAME#[21,23,29]
IRQ[23,29]
SER
C_CLKRUN#[23,29]
LP
CPD#[23]
LP
CL
K_LPC_DEBUG
LK_TPM
PC
K_PCI_775
CL
V_S5
+3
+3
2
R4
13 1K/F_4
R412 1K/F_4
R1
14 CZ@10K/F_4
15 *CZ@10K/F_4
R1
R507 10K/F_4
04 *shortEV@0_4
94 *short_4
95 *short_4
98 *short_4
97 *short_4
88
R3
1M_4
62 22_4
R4
56 22_4
R4
51 22_4
R4
R4
42 *short_4
R1
12 CZ@10K/F_4
17 CZ@10K/F_4
R1
V
V_S5
+3
SATA_ZVSS
SAT
A_ZVDD
DE
VSLP_HDD
VSLP_ODD
DE
CLK_PCIE_VGAP_C
CLK_PCIE_VGAN_C
K_PCIE_LANP_R
CL
K_PCIE_LANN_R
CL
CL
K_PCIE_WLANP_C
CLK_PCIE_WLANN_C
3
TP
48M
48M
CCLK0
LP
CCLK1
LP
33
TP
LP
C_CLKRUN#_R
_CLK
SPI
SPI
_CS#
SPI
_SO
_SI
SPI
_WP
SPI
_HOLD#
SPI
V
+3
_X1
_X2
AU3
4
AU
AV1
AV2
2
AY
1
AY
AW4
3
AW
1
AW
AW
2
AT17
12
AT
BB1
5
AU2
AU
1
U4
U3
U1
U2
W4
W3
W1
W2
Y2
Y1
BC
10
T2
T1
AW
14
13
AY
BB1
1
BA1
1
11
AY
3
BA1
4
AV1
BA1
14
BC
11
BC
AE9
BC
6
BB8
AW
7
BA9
7
AY
11
AW
BA7
12
AW
V_S5
+3
3
SATA_TX0P
SATA_TX0N
TA_RX0N
SA
TA_RX0P
SA
TA_TX1P
SA
SA
TA_TX1N
SA
TA_RX1N
TA_RX1P
SA
SATA_ZVSS
SA
TA_ZVDDP
DE
VSLP[0]/EGPIO67
VSLP[1]/EGPIO70
DE
SA
TA_ACT_L/AGPIO130
1.8V_S0
SA
TA_X1
1.8V_S0
TA_X2
SA
GF
X_CLKP
GF
X_CLKN
GPP_CLK0P
P_CLK0N
GP
GPP_CLK1P
GP
P_CLK1N
P_CLK2P
GP
GPP_CLK2N
GP
P_CLK3P
P_CLK3N
GP
CZ:3V_S0 CZL:3V_S5
X25M_48M_OSC
8M_X1
X4
X48M_X2
CZ:3V_S0 CZL:3V_S5
CCLK0/EGPIO74
LP
CZ:3V_S0 CZL:3V_S5
LP
CCLK1/EGPIO75
LA
D0
LA
D1
LA
D2
CZ:3V_S0 CZL:3V_S5
LA
D3
RAME_L
LF
ESPI
_ALERT_L/LDRQ0_L
SERIRQ/AGPIO87
LP
C_CLKRUN_L/AGPIO88
LP
C_PD_L/AGPIO21
_CLK/ESPI_CLK/EGPIO117
SPI
SPI
_CS1_L/EGPIO118
SPI_CS2_L/ESPI_CS_L/EGPIO119
SPI
_DI/ESPI_DATA/EGPIO120
_DO/EGPIO121
SPI
_WP_L/EGPIO122
SPI
_HOLD_L/EGPIO133
SPI
SPI
_TPM_CS_L/AGPIO76
V
+3
U28E
CLK/SATA/USB/SPI/LPC
3V_S0
3V_S0
3V_S0
(PD,)
(PD,)
(PD,)
(PD,)
(PD,)
(PD,)
3V_S0
(PU,PU)
3V_S0
(,PU)
3V_S5
(PD,)
CZ:1.8V_S0 CZL:1.8V_S5
(PD,)
(PD,)
(PD,)
CZ:3V_S0 CZL:3V_S5
FP
4 REV 0.93
SP@FP4
V_S5
+3
4
(PD,)
USBCLK /25 M_48 M_OSC
(PD,)
V_S5
+3
US
US
USB_HSD 0N
US
US
US
US
US
US
US
US
US
US
US
US
US
US
B_SS_ ZVSS
US
US
B_SS_ ZVDDP
US
B_SS_ 0TXP
B_SS_ 0TXN
US
USB_SS _0RX P
US
B_SS_ 0RXN
B_SS_ 1TXP
US
US
B_SS_ 1TXN
US
B_SS_ 1RXP
US
B_SS_ 1RXN
US
B_SS_ 2TXP
B_SS_ 2TXN
US
USB_SS _2RX P
US
B_SS_ 2RXN
B_SS_ 3TXP
US
USB_SS _3TX N
US
B_SS_ 3RXP
USB_SS _3RX N
V_S5
+3
B_ZVSS
B_HSD0 P
B_HSD1 P
B_HSD1 N
B_HSD2 P
B_HSD2 N
B_HSD3 P
B_HSD3 N
B_HSD4 P
B_HSD4 N
B_HSD5 P
B_HSD5 N
B_HSD6 P
B_HSD6 N
B_HSD7 P
B_HSD7 N
AP8
AP5
US
AR
2
AR1
3
AR
AR
4
2
AN
AN
1
AN
3
AN4
AM
1
AM
2
2
AL
AL
1
AL
3
AL4
AK2
2
AJ
AD
2
US
AD
1
US
AA3
AA4
W9
W8
AA2
AA1
W5
W6
1
AC
2
AC
Y6
Y7
AC
4
AC
3
AB5
AB6
V_S5
+3
TP
2
R4
14 11.8K/F_4
B_ZVSS
BSS_CALP
BSS_CALN
Port0 & Port1 : CZ ONLY
US
BP0+ [25]
BP0- [25]
US
US
BP1+ [27]
US
BP1- [27]
US
BP2+ [17]
US
BP2- [17]
BP3+ [25]
US
US
BP3- [25]
USBP4+ [21]
US
BP4- [21]
BP5+ [17]
US
US
BP5- [17]
USBP6+ [25]
USBP6- [25]
BP7+ [25]
US
BP7- [25]
US
R4
08 1K/F_4
R4
07 1K/F_4
US
B30_TX2+ [25]
US
B30_TX2- [25]
B30_RX2+ [25]
US
B30_RX2- [25]
US
US
B30_TX3+ [25]
US
B30_TX3- [25]
B30_RX3+ [25]
US
B30_RX3- [25]
US
5
DB
Touch Pad
Touch Panel
Ca
rd reader
WLAN/BT
CCD
USB3 (Charger)
USB3
VD
DP_0.95V_S5
6
route SPI bus as daisy chain
SPI IMPEDANCE 50-55R, <4''
SPI
_CS[29]
SPI_SCK[29]
SPI
_SDI[29]
SPI
_SDO[29]
SPI
_CS#
_CLK
SPI
70 *22P/50V_4
C5
SPI_SI
SPI
_SO
33S
SPI
_WP
5_18S0
SPI EMI
R4
86 CZL@0_4
22 CZL@0_4
R4
23 CZL@0_4
R4
R4
87 CZL@0_4
R4
84 33_4
R4
18 33_4
R424 33_4
R485 33_4
R4
54 10K/F_4
63 *short_4
R4
SP@ socket P/N: DFHS08FS023 only for A-TEST
SPI ROM
CARRIZO-L
3.3V
CARRIZO
1.8V
7
R4
16 CZ@0_4
VD
D_18
R4
11 CZL@0_4
+3V_S5
33S5_18S0
15
R4
10K/F_4
U27
8M
8M
8M
8M
8M
8M
1
CE
6
SC
5
SI
2
SO
3
WP
SP@W25Q64FW SSIG
AKE3
AKE2
AKE3EZN0Q01
AKE5EZN0N00
AKE5
SPI
_CS_A
_SCK_A
SPI
SPI_SDI_A
SPI
_SDO_A
SPI
_WP_R
nder Size Quanta P/N
Ve
EO
N
WN
D
EON
VD
#
K
HO
#
VSS
EFP0N07
EZN0Q00
EG-0Q00 GD25LQ 64CSIGRGGD
D
LD#
33S5_18S0
33S5_18S0
8
7
4
Vender P/N
5Q64FVSSIQWND
W2
GD
25B64CSIGRGGD
25QH64-104HIP
EN
5Q64FWSSIG
W2
R4
10K/F_4
8
71
C5
0.1u/16V_4
17
SPI
_HOLD#
R9
R9
*CZL@10K_4
CCLK0
LP
LP
CCLK1
LP
C_LFRAME#
RT
C_CLK[5]
GE
VENT2#[5]
RST#[5]
SYS_
AG
PIO11[5]
D D
1
R1
5
08
*CZ@10K_4
R9
7
2k_4
2
R9
6
CZL@10K_4
R1
01
CZ@10K_4
R1
00
*2k_4
R5
31
CZL@10K_4
R4
CZ@10K_4
R4
*2k_4
3
R8
10K_4
R7
*2k_4
2
*CZ@10K_4
R9
6
2k_4
75
68
R3
10K_4
R3
*2k_4
4
R9
87
4
10K_4
LP
C_CLK0 LFRAME#
LP
C_CLK1
RT
C_CLK
CZ-L
ABLE
FAULT
5
Int
DEFAULT
Ext
ernal CLKGEN
SPI ROM
FAULT
DE
LPC ROM
Co
in battery
is on board.
DEFAULT
Coin battery
is not on board.
BOOT Fail Timer
PU
EN
BOOT Fail Timer
PD
DISABLE
DE
R9
8
85
*2k_4
ernal C LKGEN
1.8V SPI
3.3V SPI
DEFAULT
6
I
nt pull-up
GE
VENT2# (AGPIO3)
Enhanced Reset logic
ROM
(faster resume from S5)
Default to
ROM
Traditional Reset logic
DEFAULT
CZ
Si
Si
Size Document Number Rev
ze Document Number Rev
ze Document Number Rev
4 SATA/USB/LPC/SPI(5/7)
4 SATA/USB/LPC/SPI(5/7)
4 SATA/USB/LPC/SPI(5/7)
FP
FP
FP
Date: Sheet
Date: Sheet
Date: Sheet
7
I
nt pull-upInt pull-up
SYS_RST#
normal reset mode
DEFAULT DEFAULT
short reset mode
anta Computer Inc.
anta Computer Inc.
anta Computer Inc.
Qu
Qu
Qu
PROJECT :
PROJECT :
PROJECT :
I
nt pull-up
AG
PIO11(BLINK)
LDT_RST#/LDT_PWRGD
output to APU
LDT_RST#/LDT_PWRGD
output to Pads
ZRZ
ZRZ
ZRZ
1Friday, March 06, 2015
1Friday, March 06, 2015
1Friday, March 06, 2015
64
64
64
of
of
of
8
1A
1A
1A
2
1
1
(CPU)
C2
15
22u/6.3V_6
A A
VD
B B
C C
D_18
C2
07
10u/6.3V_6
VD
D_18_S5
+1
D D
1
+1
C1
95
0.22u/10V_4
C1
10u/6.3V_6
.5VSUS
VD
DCR_NB
C2
19
0.22u/10V_4
VDDP_0.95V
83
C5
10u/6.3V_6
R4
99 *short_4
.5V
C1
60
62
0.22u/10V_4
COUPLING BETWEEN PROCESSOR AND DIMMs
DE
ACROSS VDDIO AND VSS SPLI T
36
C2
0.22u/10V_4
C2
0.22u/10V_4
48
C1
0.22u/10V_4
ROSS VDDNB AND VSS SPLIT
AC
2
C2
C2
09
22u/6.3V_6
C2
0.22u/10V_4
C5
10u/6.3V_6
10
22u/6.3V_6
C2
37
16
0.22u/10V_4
87
88
C5
10u/6.3V_6
+V
96
95
C5
C5
1u/10V_4
1u/10V_4
V_S5
+3
C1
C1
92
0.22u/10V_4
10u/6.3V_6
35
20
C2
0.22u/10V_4
4x0.22UF (0402)+2x180PF(0402)
41
C1
0.22u/10V_4
49
C1
0.22u/10V_4
2
DDIO_AZ
VD
91
C2
11
22u/6.3V_6
C2
33
0.22u/10V_4
90
C5
10u/6.3V_6
17
C2
1u/10V_4
DP_0.95V_S5
C1
10u/6.3V_6
C1
180P/50V_4
34
C2
0.22u/10V_4
52
C1
0.22u/10V_4
3
C2
13
22u/6.3V_6
C2
25
0.22u/10V_4
86
C5
0.22u/10V_4
DP_0.95V
VD
R6
47
C1
0.22u/10V_4
C1
99
0.22u/10V_4
21
C2
180P/50V_4
3
C2
24
22u/6.3V_6
C2
80
180P/50V_4
14
C2
0.22u/10V_4
9 SP@0_8
200mA
74
C2
10u/6.3V_6
VD
DCR_FCH_ALW
C1
CZ@22u/6.3V_6
06
C1
22U/6.3V_6
C2
06
0.22u/10V_4
C2
32
22u/6.3V_6
C2
75
180P/50V_4
79
C5
0.22u/10V_4
CZL UMA tied to VSS.
CZ UMA&DIS and CZL DIS tied to VDDP
R70
SP@0_4
C1
81
75
CZ@22u/6.3V_6
15
C1
22U/6.3V_6
C2
08
0.22u/10V_4
C2
12
22u/6.3V_6
C2
27
0.22u/10V_4
26
C2
0.22u/10V_4
R1
47 *short_4
+3
V
VD
DCR_FCH_S5
13 *CZ@0_4
R1
C1
67
68
0.22u/10V_4
14
C1
0.22u/10V_4
C1
85
94
0.22u/10V_4
06
C3
180P/50V_4
51
C1
0.22u/10V_4
C3
C2
04
180P/50V_4
180P/50V_4
80
C5
C5
0.22u/10V_4
0.22u/10V_4
VD
DP_GFX
C133
SP@10u/6.3V_6
VD
D33
C1
80
CZ@0.22u/10V_4
Place under APU
50
C1
22U/6.3V_6
C2
22
0.22u/10V_4
4
18
81
1.5A
C153
SP@0.22u/10V_4
1.5A
500mA
200mA
800mA
VD
VD
DCR_NB
09
C1
22U/6.3V_6
C2
28
0.22u/10V_4
4
C3
37
180P/50V_4
82
C5
180P/50V_4
DP_0.95V
7A
.5VSUS
+1
DDIO_AZ
+V
200mA
.5V_RTC_R
+1
20M
AW
AW
C1
84
0.22u/10V_4
IL
P2
5
VD
P28
VDDIO_ME M_S3 _2
4
T2
VDDIO_ME M_S3 _3
T2
7
VD
5
U2
VD
U2
8
VD
V30
VDDIO_ME M_S3 _7
3
V3
VD
4
W2
VD
W2
7
VD
Y25
VD
8
Y2
VD
Y3
0
VD
4
AB2
VDDIO_ME M_S3 _14
AB2
7
VD
AB30
VD
3
AB3
VD
AD
25
VD
AD
28
VD
AD30
VD
4
AE2
VD
AE2
7
VD
30
AF
VD
AF
33
VD
AG25
VD
28
AG
VDDIO_ME M_S3 _26
AH
24
VD
27
AH
VD
AH
30
VD
5
AK2
VDDIO_ME M_S3 _30
AK2
8
VD
0
AK3
VD
AK3
3
VDDIO_ME M_S3 _33
AL27
VD
30
AM
VD
19
AR
VDDIO_AUDI O
AE6
VD
AE5
VD
AP1
9
VDD_33 _1
AP2
1
VD
AP1
6
VD
AP1
8
VD
0
AP1
VD
9
AR
VDD_18 _S5_ 2
5
AP1
VD
AR
15
VD
AN
12
VD
AP1
2
VD
3
AP1
VD
12
AR
VD
19
VD
17
AU
VDDP_1
19
AU
VD
7
AV1
VD
AV1
9
VD
17
VDDP_5
12
AL
VD
AL
13
VDDCR_NB_ 2
15
AL
VD
18
AL
VD
21
AL
VD
13
AN
VD
16
AN
VD
19
AN
VD
AN
22
VD
AR
17
VD
54 1K/F_4
R5
C6
36
1u/10V_4
DIO_MEM _S3_ 1
DIO_MEM _S3_ 4
DIO_MEM _S3_ 5
DIO_MEM _S3_ 6
DIO_MEM _S3_ 8
DIO_MEM _S3_ 9
DIO_MEM _S3_ 10
DIO_MEM _S3_ 11
DIO_MEM _S3_ 12
DIO_MEM _S3_ 13
DIO_MEM _S3_ 15
DIO_MEM _S3_ 16
DIO_MEM _S3_ 17
DIO_MEM _S3_ 18
DIO_MEM _S3_ 19
DIO_MEM _S3_ 20
DIO_MEM _S3_ 21
DIO_MEM _S3_ 22
DIO_MEM _S3_ 23
DIO_MEM _S3_ 24
DIO_MEM _S3_ 25
DIO_MEM _S3_ 27
DIO_MEM _S3_ 28
DIO_MEM _S3_ 29
DIO_MEM _S3_ 31
DIO_MEM _S3_ 32
DIO_MEM _S3_ 34
DIO_MEM _S3_ 35
DP_GFX _2
DP_GFX _1
D_33_ 2
D_18_ 1
D_18_ 2
D_18_ S5_1
D_33_ S5_1
D_33_ S5_2
DP_S5_ 1
DP_S5_ 2
DCR_FC H_S5_ 1
DCR_FC H_S5_ 2
DP_6
DP_2
DP_3
DP_4
DCR_NB_ 1
DCR_NB_ 3
DCR_NB_ 4
DCR_NB_ 5
DCR_NB_ 6
DCR_NB_ 7
DCR_NB_ 8
DCR_NB_ 9
DBT_RTC_ G
G1
*S
HORT_ PAD
RT
C (RTC)
5
U28F
POWER
4 REV 0.93
FP
SP@FP4
.5V_RTC
+1
12
5
DCR_CP U_1
VD
VDDCR_CP U_2
VDDCR_CP U_3
VD
DCR_CP U_4
DCR_CP U_5
VD
DCR_CP U_6
VD
VDDCR_CP U_7
DCR_CP U_8
VD
VD
DCR_CP U_9
DCR_CP U_10
VD
VD
DCR_CP U_11
DCR_CP U_12
VD
DCR_CP U_13
VD
VDDCR_CP U_14
VD
DCR_CP U_15
VD
DCR_CP U_16
DCR_CP U_17
VD
VD
DCR_CP U_18
DCR_CP U_19
VD
VD
DCR_CP U_20
VD
DCR_CP U_21
VD
DCR_CP U_22
VD
DCR_CP U_23
DCR_CP U_24
VD
VD
DCR_CP U_25
VDDCR_CP U_26
VD
DCR_CP U_42
VD
DCR_CP U_31
DCR_CP U_43
VD
VDDCR_CP U_32
DCR_CP U_44
VD
VD
DCR_CP U_33
VDDCR_CP U_45
VD
DCR_CP U_34
DCR_CP U_46
VD
DCR_CP U_35
VD
VDDCR_CP U_47
VDDCR_CP U_36
VD
DCR_CP U_28
DCR_CP U_29
VD
DCR_CP U_40
VD
VDDCR_CP U_30
DCR_CP U_37
VD
VD
DCR_CP U_49
DCR_CP U_38
VD
VD
DCR_CP U_39
DCR_CP U_48
VD
DCR_CP U_41
VD
VDDCR_CP U_27
DCR_GF X_14
VD
VD
DCR_GF X_15
DCR_GF X_16
VD
VD
DCR_GF X_17
VD
DCR_GF X_18
VD
DCR_GF X_19
VD
DCR_GF X_20
DCR_GF X_21
VD
VD
DCR_GF X_22
VDDCR_GF X_23
VD
DCR_GF X_24
VD
DCR_GF X_25
DCR_GF X_26
VD
VDDCR_GF X_27
DCR_GF X_28
VD
VD
DCR_GF X_29
VDDCR_GF X_1
VD
DCR_GF X_2
DCR_GF X_3
VD
DCR_GF X_4
VD
DCR_GF X_5
VD
VD
DCR_GF X_6
DCR_GF X_7
VD
DCR_GF X_8
VD
VD
DCR_GF X_9
VD
DCR_GF X_10
VD
DCR_GF X_11
VD
DCR_GF X_12
VD
DCR_GF X_30
VD
DCR_GF X_31
VD
DCR_GF X_32
DCR_GF X_33
VD
DCR_GF X_34
VD
VD
DCR_GF X_35
DCR_GF X_36
VD
DCR_GF X_37
VD
DCR_GF X_13
VD
Q4
7
AP2138N-1.5TRG1
1
2
3
6
DCR_CPU
VD
U8
W7
2
W1
W1
5
8
W1
W2
1
Y8
0
Y1
3
Y1
Y1
6
Y19
2
Y2
AB7
AB9
AB1
2
AB15
8
AB1
AB2
1
AD
6
AD10
13
AD
AD
16
19
AD
AD
22
AE7
2
AE1
AK9
10
AG
AK1
0
13
AG
AK1
3
16
AG
AK1
6
AG19
9
AK1
AG
22
2
AK2
AH
7
8
AE1
AE2
1
21
AH
AG
6
AH
12
AN
6
AH
15
AH
18
7
AL
AK6
5
AE1
L8
L13
L16
L19
L22
N7
2
N1
5
N1
8
N1
1
N2
P8
3
P1
P1
6
P1
9
P2
2
T7
F1
2
5
F1
1
G1
4
G1
J8
J9
1
J1
K7
K1
2
K1
3
K1
5
K1
6
2
T1
5
T1
8
T1
1
T2
3
U1
U1
6
U1
9
U2
2
K1
9
+3
20MIL20MIL
RTC CR2032 Coin Battery
DBV: AHL03003057
VDE: AHL03003003
VRTC
6
DCR_GFX
VD
C6
39
1u/10V_4
C2
01
22U/6.3V_6
C1
88
22U/6.3V_6
C169
0.22u/10V_4
63
C1
0.22u/10V_4
C2
05
CZ@22U/6.3V_6
C1
90
CZ@22U/6.3V_6
55
C1
CZ@0.22u/10V_4
C1
73
CZ@0.22u/10V_4
+3
+V
9
D3
BAT54CW
C2
02
22U/6.3V_6
C1
77
22U/6.3V_6
C171
0.22u/10V_4
64
C1
0.22u/10V_4
Place under APU
C1
CZ@22U/6.3V_6
C1
CZ@22U/6.3V_6
C1
CZ@0.22u/10V_4
C1
CZ@0.22u/10V_4
VPCU_R
CCRTC_2
7
C1
C2
03
22U/6.3V_6
C1
78
22U/6.3V_6
C170
0.22u/10V_4
61
C1
0.22u/10V_4
C1
82
96
56
74
R5
76
CZ@22U/6.3V_6
C2
04
CZ@22U/6.3V_6
57
C1
CZ@0.22u/10V_4
C1
72
CZ@0.22u/10V_4
62 *short_4
20M
IL
R5
63
1K/F_4
+BAT
20MIL
12
1
CN1
RTC_2032
Si
Si
Size Document Number Rev
ze Document Number Rev
ze Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
7
C1
86
22U/6.3V_6
22U/6.3V_6
C1
79
22U/6.3V_6
C165
C166
0.22u/10V_4
0.22u/10V_4
83
C1
180P/50V_4
C1
CZ@22U/6.3V_6
C2
CZ@22U/6.3V_6
C1
CZ@0.22u/10V_4
C1
CZ@0.22u/10V_4
+3
VPCU
4 POWER(6/7)
4 POWER(6/7)
4 POWER(6/7)
FP
FP
FP
87
C1
54
89
CZ@22U/6.3V_6
00
58
97
59
C1
CZ@0.22u/10V_4
C1
98
CZ@180P/50V_4
anta Computer Inc.
anta Computer Inc.
anta Computer Inc.
Qu
Qu
Qu
PROJECT :
PROJECT :
PROJECT :
ZRZ
ZRZ
ZRZ
8
1A
1A
1A
1Wednesday, March 18, 2015
1Wednesday, March 18, 2015
1Wednesday, March 18, 2015
74
74
74
of
of
of
8
(C
PU)
1
2
3
4
5
6
7
8
U28G
VS
VS
VS
VS
VSS_5
VS
VSS_7
VS
VS
VS
VS
VSS_12
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VSS_29
VS
VS
VS
VS
VSS_34
VS
VSS_36
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
GND
S_1
S_2
S_3
S_4
S_6
S_8
S_9
S_10
S_11
S_13
S_14
S_15
S_16
S_17
S_18
S_19
S_20
S_21
S_22
S_23
S_24
S_25
S_26
S_27
S_28
S_30
S_31
S_32
S_33
S_35
S_37
S_38
S_39
S_40
S_41
S_42
S_43
S_44
S_45
S_46
S_47
S_48
S_49
S_50
S_51
S_52
S_53
S_54
S_55
S_56
S_57
S_58
S_59
S_60
S_61
S_62
FP
4 REV 0.93
SP@FP4
VS
VS
VS
VS
VSS_67
VS
VSS_69
VS
VS
VS
VS
VSS_74
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VSS_91
VS
VS
VS
VS
VSS_96
VS
VSS_98
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
S_100
S_101
S_102
S_103
S_104
S_105
S_106
S_107
S_108
S_109
S_110
S_111
S_112
S_113
S_114
S_115
S_116
S_117
S_118
S_119
S_120
S_121
S_122
S_123
S_124
L28
S_63
M4
S_64
0
M3
S_65
N1
0
S_66
3
N1
N1
6
S_68
N1
9
N22
S_70
N2
7
S_71
P1
S_72
P2
S_73
P4
P5
S_75
2
P1
S_76
P1
5
S_77
8
P1
S_78
1
P2
S_79
P3
0
S_80
P3
3
S_81
T4
S_82
0
T1
S_83
3
T1
S_84
6
T1
S_85
T1
9
S_86
T2
2
S_87
0
T3
S_88
U5
S_89
U1
2
S_90
U1
5
U1
8
S_92
1
U2
S_93
4
U2
S_94
V1
S_95
V2
V4
S_97
0
W1
3
W1
S_99
W1
6
W1
9
W2
2
Y4
Y5
Y1
2
Y1
5
Y1
8
1
Y2
4
Y2
AB1
AB2
AB4
0
AB1
3
AB1
AB1
6
AB1
9
AB2
2
4
AD
9
AD
AD
12
AD
15
AD
18
21
AD
24
AD
AE10
AE1
AE1
AE1
AE2
AF
AF
AG9
AG
AG
AG
AG
AH
AH
AH
AH
AH
AH
AK1
AK4
AK1
AK1
AK1
AL
AL
AL
AM
AN
AN
AN
AN
AN
AN
AN
AP1
AP2
AP4
AP7
AP2
AP2
AP3
AP3
AR
AR
AR
AT
AT
AT
AT
AU
AU
AU
AU
AU
AU
AU
AV4
AV7
AV9
AV1
AV1
AV2
3
6
9
2
1
4
12
15
18
21
4
10
13
16
19
22
2
5
8
16
19
22
4
9
10
15
18
21
25
28
2
7
0
3
6
25
28
4
19
22
30
5
8
11
14
20
23
27
2
5
5
A A
B B
C C
A8
A1
2
6
A1
A2
0
4
A2
A2
8
A3
2
B2
B8
B1
2
3
B3
C3
D4
D6
D8
0
D1
2
D1
D1
4
D1
6
D1
8
0
D2
2
D2
4
D2
D2
6
D2
8
0
D3
F1
F2
F4
F9
9
F1
2
F2
F2
5
F3
0
F3
3
G7
7
G1
G2
0
G2
3
G2
6
H4
0
H3
J5
J1
5
J1
9
2
J2
5
J2
J2
8
K1
K2
K4
0
K1
K2
2
K2
7
K3
0
3
K3
L5
L12
L15
L18
L21
L25
S_125
VS
VS
S_126
S_127
VS
VS
S_128
VSS_129
VS
S_130
VSS_131
S_132
VS
S_133
VS
S_134
VS
VS
S_135
VSS_136
VS
S_137
S_138
VS
S_139
VS
S_140
VS
S_141
VS
VS
S_142
VS
S_143
VS
S_144
S_145
VS
VS
S_146
S_147
VS
VS
S_148
S_149
VS
VS
S_150
VS
S_151
S_152
VS
VSS_153
S_154
VS
VS
S_155
S_156
VS
VS
S_157
VSS_158
VS
S_159
VSS_160
S_161
VS
S_162
VS
S_163
VS
VS
S_164
S_165
VS
S_166
VS
VS
S_167
VS
S_168
S_169
VS
VS
S_170
VS
S_171
S_172
VS
VS
S_173
VS
S_174
S_175
VS
S_176
VS
VS
S_177
S_178
VS
S_179
VS
VS
S_180
S_181
VS
S_182
VS
VS
S_183
VS
S_184
S_185
VS
S_186
VS
FP
U28H
GND
4 REV 0.93
SP@FP4
S_187
VS
VS
S_188
S_189
VS
VS
S_190
VSS_191
VS
S_192
VSS_193
S_194
VS
S_195
VS
S_196
VS
VS
S_197
VSS_198
VS
S_199
S_200
VS
S_201
VS
S_202
VS
S_203
VS
VS
S_204
VS
S_205
VS
S_206
S_207
VS
VS
S_208
S_209
VS
VS
S_210
S_211
VS
VS
S_212
VSS_
VSS_
VSS_
AV30
AV3
3
22
AW
AY
4
6
AY
AY
8
AY
10
AY12
AY
14
AY
16
20
AY
22
AY
AY
24
26
AY
AY
28
30
AY
BB1
BB3
3
BC
4
BC
8
12
BC
16
BC
20
BC
BC
24
BC
28
32
BC
L24
213
10
AL
215
1
AK2
214
U3
0
1
U3
AN
30
RS
RS
RSVD_4
U28J
VD_2
VD_3
FP
4 REV 0.93
SP@FP4
D D
anta Computer Inc.
anta Computer Inc.
anta Computer Inc.
Qu
Qu
Qu
PROJECT :
PROJECT :
ze Documen t Number Rev
ze Documen t Number Rev
ze Documen t Number Rev
Si
Si
Si
Date: Sheet
Date: Sheet
1
2
3
4
5
6
Date: Sheet
4 GND(7/7)
4 GND(7/7)
4 GND(7/7)
FP
FP
FP
PROJECT :
7
ZRZ
ZRZ
ZRZ
1Friday, March 06, 2015
1Friday, March 06, 2015
1Friday, March 06, 2015
of
of
of
84
84
84
8
1A
1A
1A
5
SOD
IMM (SDM)
M_A_A[15:0][3]
D D
M_
A_BS#0[3]
M_
A_BS#1[3]
M_
A_BS#2[3]
M_
A_CS#0[3]
M_
A_CS#1[3]
M_
A_CLK0[3]
M_
A_CLK0#[3]
M_
A_CLK1[3]
M_
A_CLK1#[3]
M_
A_CKE0[3]
M_
A_CKE1[3]
M_
A_CAS#[3]
M_
A_RAS#[3]
M_
A_WE#[3]
CL
K_SCLK[5,10,23]
CL
C C
B B
+1
.5VSUS
K_SDATA[5,10,23]
M_
A_ODT0[3]
M_
A_ODT1[3]
M_
A_DM[7..0][3]
M_
A_DQS[7:0][3]
M_
A_DQS#[7:0][3]
ace these Caps near So-Dimm1.
Pl
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
A_DQS0
M_
A_DQS1
M_
A_DQS2
M_
A_DQS3
M_
A_DQS4
M_
A_DQS5
M_
A_DQS6
M_
A_DQS7
M_
A_DQS#0
M_
A_DQS#1
M_
A_DQS#2
M_
A_DQS#3
M_
A_DQS#4
M_
A_DQS#5
M_
A_DQS#6
M_
A_DQS#7
A_A15
A_DM0
A_DM1
A_DM2
A_DM3
A_DM4
A_DM5
A_DM6
A_DM7
107
119
109
108
114
121
101
103
102
104
115
110
113
197
201
202
200
116
120
136
153
170
187
137
154
171
188
135
152
169
186
98
97
96
95
92
91
90
86
89
85
84
83
80
78
79
73
74
11
28
46
63
12
29
47
64
10
27
45
62
4
JDIM1A
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A1
0/AP
A11
2/BC#
A1
A1
3
4
A1
A1
5
BA0
BA1
BA2
S0
#
#
S1
CK
0
0#
CK
CK
1
1#
CK
E0
CK
E1
CK
S#
CA
RA
S#
#
WE
SA0
SA1
SC
L
A
SD
OD
T0
T1
OD
0
DM
DM
1
2
DM
DM
3
4
DM
5
DM
DM
6
7
DM
S0
DQ
DQ
S1
S2
DQ
DQ
S3
DQ
S4
S5
DQ
DQ
S6
S7
DQ
DQ
S#0
S#1
DQ
DQ
S#2
S#3
DQ
DQS#4
DQ
S#5
S#6
DQ
DQ
S#7
CZ@DDR3-DIMM1_H=4_REV
2100 DDR3 SDRAM SO-DIMM
PC
DQ
DQ11
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ19
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
(204P)
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ60
DQ
DQ
DQ
3
5
DQ
0
7
1
DQ
15
DQ
2
17
3
DQ
4
DQ
4
6
5
DQ
16
DQ
6
18
7
DQ
21
DQ
8
23
9
DQ
33
10
35
22
12
24
13
34
14
36
15
39
16
41
17
51
18
53
40
20
42
21
50
22
52
23
57
24
59
25
67
26
69
27
56
28
58
29
68
30
70
31
129
32
131
33
141
34
143
35
130
36
132
37
140
38
142
39
147
40
149
41
157
42
159
43
146
44
148
45
158
46
160
47
163
48
165
49
175
50
177
51
164
52
166
53
174
54
176
55
181
56
183
57
191
58
193
59
180
182
61
192
62
194
63
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ3
M_A_DQ1
M_A_DQ0
M_A_DQ7
M_A_DQ2
M_A_DQ8
M_A_DQ9
M_A_DQ11
M_A_DQ10
M_A_DQ12
M_A_DQ13
M_A_DQ15
M_
A_DQ14
M_
A_DQ16
M_
A_DQ17
M_
A_DQ18
M_
A_DQ19
M_
A_DQ20
M_
A_DQ21
M_
A_DQ22
M_
A_DQ23
M_
A_DQ24
M_
A_DQ25
M_
A_DQ26
M_
A_DQ27
M_
A_DQ28
M_
A_DQ29
M_
A_DQ30
M_
A_DQ31
M_
A_DQ32
M_
A_DQ33
M_
A_DQ34
M_
A_DQ35
M_
A_DQ36
M_
A_DQ37
M_
A_DQ38
M_
A_DQ39
M_
A_DQ40
M_
A_DQ41
M_
A_DQ42
M_
A_DQ43
M_
A_DQ44
M_
A_DQ45
M_
A_DQ46
M_
A_DQ47
M_
A_DQ48
M_
A_DQ49
M_
A_DQ50
M_
A_DQ51
M_
A_DQ52
M_
A_DQ53
M_
A_DQ54
M_
A_DQ55
M_
A_DQ56
M_
A_DQ57
M_
A_DQ58
M_
A_DQ59
M_
A_DQ60
M_
A_DQ61
M_
A_DQ62
M_
A_DQ63
M_A_DQ[63:0] [3]
+3V
+1.5VSUS
R1
97
CZ@1K_4
M_
A_EVENT#[3]
M_
A_RESET#[3]
2
C3
22
CZ@1U/10V_4
C3
21 CZ@1000p/50V_4
C3
20 CZ@0.1u/16V_4
+V
REF_DQ0
+V
REF_CA0
C3
48 CZ@0.1u/16V_4
C3
47 CZ@1000p/50V_4
+1.5VSUS
2.48A
MDDR_VREF
+S
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
199
77
122
125
198
30
126
13
14
19
20
25
26
31
32
37
38
43
R2
10 *CZ@0_6
3mA
JDIM1B
VD
D1
D2
VD
VD
D3
D4
VD
VD
D5
D6
VD
VD
D7
D8
VD
VD
D9
D10
VD
VD
D11
VDD12
D13
VD
VD
D14
D15
VD
VD
D16
D17
VD
VD
D18
VDDSPD
NC1
NC2
EST
NCT
T#
EVEN
SET#
RE
1
VR
EF_DQ
EF_CA
VR
2
VSS1
3
VSS2
8
VSS3
9
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS1
VSS1
VSS1
VSS1
VSS1
VSS1
CZ@DDR3-DIMM1_H=4_REV
0
1
2
3
4
5
+1
+1
.5VSUS
.5VSUS
100 DDR3 SDRAM SO-DIMM
PC2
R2
09
CZ@1K/F_4
R1
99
CZ@1K/F_4
(204P)
VSS1
VSS1
VSS1
VSS1
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS27
VSS2
VSS2
VSS3
VSS3
VSS3
VSS3
VSS3
VSS35
VSS3
VSS3
VSS3
VSS3
VSS4
VSS4
VSS4
VSS4
VSS4
VSS4
VSS4
VSS4
VSS4
VSS4
VSS5
VSS5
VSS5
VT
VT
GN
GN
T1
T2
1
44
6
48
7
49
8
54
9
55
0
60
1
61
2
65
3
66
4
71
5
72
6
127
128
8
133
9
134
0
138
1
139
2
144
3
145
4
150
151
6
155
7
156
8
161
9
162
0
167
1
168
2
172
3
173
4
178
5
179
6
184
7
185
8
189
9
190
0
195
1
196
2
203
204
205
D
206
D
+V
REF_CA0
C3
49
CZ@0.1u/16V_4
+S
MDDR_VTT
0.25A
C3
13
CZ@0.1u/16V_4
+1
.5VSUS
A A
C3
41
CZ@0.1u/16V_4
C3
14
CZ@0.1u/16V_4
C3
42
CZ@0.1u/16V_4
5
C3
17
CZ@0.1u/16V_4
C3
43
CZ@0.1u/16V_4
C3
18
CZ@0.1u/16V_4
C3
44
CZ@0.1u/16V_4
C3
15
CZ@0.1u/16V_4
C3
45
CZ@0.1u/16V_4
C3
CZ@0.1u/16V_4
C3
CZ@0.1u/16V_4
4
C3
16
46
32
CZ@180P/50V_4
+S
MDDR_VTT
C3
35
CZ@4.7U/6.3V_6
C3
33
CZ@0.1u/16V_4
3
R1
76
CZ@1K/F_4
R1
M_
A_VRFDQ[3]
2
75 *CZ@0_6
3
mA
Si
Si
Si
ze Document Number Rev
ze Document Number Rev
ze Document Number Rev
DDR3
DDR3
DDR3
Date: Sheet
Date: Sheet
Date: Sheet
R1
CZ@1K/F_4
DIMM 1
DIMM 1
DIMM 1
77
Qu
Qu
Qu
PROJECT :
PROJECT :
PROJECT :
+V
REF_DQ0
C3
19
CZ@0.1u/16V_4
anta Computer Inc.
anta Computer Inc.
anta Computer Inc.
ZRZ
ZRZ
ZRZ
of
94
of
94
of
94
1
1Wednesday, March 18, 2015
1Wednesday, March 18, 2015
1Wednesday, March 18, 2015
1A
1A
1A
5
SOD
IMM (SDM)
M_B_A[15:0][3]
D D
M_
B_BS#0[3]
M_
B_BS#1[3]
M_
B_BS#2[3]
M_
B_CS#0[3]
M_
B_CS#1[3]
M_
B_CLK0[3]
M_
B_CLK0#[3]
M_
B_CLK1[3]
M_
B_CLK1#[3]
M_
B_CKE0[3]
M_
B_CKE1[3]
M_
B_CAS#[3]
M_
B_RAS#[3]
M_
R2
11 4.7K_4
+3
V
C C
B B
B_WE#[3]
CL
K_SCLK[5,9,23]
CL
K_SDATA[5,9,23]
M_
B_ODT0[3]
M_
B_ODT1[3]
M_
B_DM[7..0][3]
M_
B_DQS[7:0][3]
M_
B_DQS#[7:0][3]
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_
B_A15
M_
B_DM0
M_
B_DM1
M_
B_DM2
M_
B_DM3
M_
B_DM4
M_
B_DM5
M_
B_DM6
M_
B_DM7
M_
B_DQS0
M_
B_DQS1
M_
B_DQS2
M_
B_DQS3
M_
B_DQS4
M_
B_DQS5
M_
B_DQS6
M_
B_DQS7
M_
B_DQS#0
M_
B_DQS#1
M_
B_DQS#2
M_
B_DQS#3
M_
B_DQS#4
M_
B_DQS#5
M_
B_DQS#6
M_
B_DQS#7
107
119
109
108
114
121
101
103
102
104
115
110
113
197
201
202
200
116
120
136
153
170
187
137
154
171
188
135
152
169
186
98
97
96
95
92
91
90
86
89
85
84
83
80
78
79
73
74
11
28
46
63
12
29
47
64
10
27
45
62
4
JDIM2A
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A1
0/AP
A11
2/BC#
A1
A1
3
4
A1
A1
5
BA0
BA1
BA2
S0
#
#
S1
CK
0
0#
CK
CK
1
1#
CK
E0
CK
E1
CK
S#
CA
RA
S#
#
WE
SA0
SA1
SC
L
A
SD
OD
T0
T1
OD
0
DM
DM
1
2
DM
DM
3
4
DM
2100 DDR3 SDRAM SO-DIMM
5
DM
DM
6
7
DM
S0
DQ
DQ
S1
S2
DQ
DQ
S3
DQ
S4
S5
DQ
DQ
S6
S7
DQ
DQ
S#0
S#1
DQ
DQ
S#2
S#3
DQ
DQS#4
DQ
S#5
S#6
DQ
DQ
S#7
DDR3-DIMM2_H=4_STD
PC
(204P)
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ11
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ19
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ60
DQ
DQ
DQ
3
5
0
7
1
15
2
17
3
4
4
6
5
16
6
18
7
21
8
23
9
33
10
35
22
12
24
13
34
14
36
15
39
16
41
17
51
18
53
40
20
42
21
50
22
52
23
57
24
59
25
67
26
69
27
56
28
58
29
68
30
70
31
129
32
131
33
141
34
143
35
130
36
132
37
140
38
142
39
147
40
149
41
157
42
159
43
146
44
148
45
158
46
160
47
163
48
165
49
175
50
177
51
164
52
166
53
174
54
176
55
181
56
183
57
191
58
193
59
180
182
61
192
62
194
63
M_B_DQ5
M_B_DQ0
M_B_DQ6
M_B_DQ7
M_B_DQ4
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_
B_DQ15
M_
B_DQ16
M_
B_DQ17
M_
B_DQ18
M_
B_DQ19
M_
B_DQ20
M_
B_DQ21
M_
B_DQ22
M_
B_DQ23
M_
B_DQ24
M_
B_DQ25
M_
B_DQ26
M_
B_DQ27
M_
B_DQ28
M_
B_DQ29
M_
B_DQ30
M_
B_DQ31
M_
B_DQ32
M_
B_DQ33
M_
B_DQ34
M_
B_DQ35
M_
B_DQ36
M_
B_DQ37
M_
B_DQ38
M_
B_DQ39
M_
B_DQ40
M_
B_DQ41
M_
B_DQ42
M_
B_DQ43
M_
B_DQ44
M_
B_DQ45
M_
B_DQ46
M_
B_DQ47
M_
B_DQ48
M_
B_DQ49
M_
B_DQ50
M_
B_DQ51
M_
B_DQ52
M_
B_DQ53
M_
B_DQ54
M_
B_DQ55
M_
B_DQ56
M_
B_DQ57
M_
B_DQ58
M_
B_DQ59
M_
B_DQ60
M_
B_DQ61
M_
B_DQ62
M_
B_DQ63
M_B_DQ[63:0] [3]
+3V
+1.5VSUS
M_
B_EVENT#[3]
M_
B_RESET#[3]
R2
1K_4
C3
62
1U/10V_4
25
2
C3
63 1000p/50V_4
C3
64 0.1u/16V_4
+V
REF_DQ1
+V
REF_CA1
C3
83 0.1u/16V_4
C3
94 1000p/50V_4
2.48A
+1.5VSUS
MDDR_VREF
+S
100
105
106
111
112
117
118
123
124
199
122
125
198
126
R2
35 *0_6
3mA
JDIM2B
75
VD
D1
76
D2
VD
81
VD
D3
82
D4
VD
87
VD
D5
88
D6
VD
93
VD
D7
94
D8
VD
99
VD
D9
D10
VD
VD
D11
VDD12
D13
VD
VD
D14
D15
VD
VD
D16
D17
VD
VD
D18
VDDSPD
77
NC1
NC2
EST
NCT
T#
EVEN
30
SET#
RE
1
VR
EF_DQ
EF_CA
VR
2
VSS1
3
VSS2
8
VSS3
9
VSS4
13
VSS5
14
VSS6
19
VSS7
20
VSS8
25
VSS9
26
VSS1
0
31
1
VSS1
32
2
VSS1
37
VSS1
3
38
4
VSS1
43
VSS1
5
DDR3-DIMM2_H=4_STD
+1
.5VSUS
100 DDR3 SDRAM SO-DIMM
PC2
R2
34
1K/F_4
R2
30
1K/F_4
(204P)
VSS1
VSS1
VSS1
VSS1
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS27
VSS2
VSS2
VSS3
VSS3
VSS3
VSS3
VSS3
VSS35
VSS3
VSS3
VSS3
VSS3
VSS4
VSS4
VSS4
VSS4
VSS4
VSS4
VSS4
VSS4
VSS4
VSS4
VSS5
VSS5
VSS5
VT
VT
GN
GN
6
7
8
9
0
1
2
3
4
5
6
8
9
0
1
2
3
4
6
7
8
9
0
1
2
3
4
5
6
7
8
9
0
1
2
T1
T2
D
D
+V
C3
0.1u/16V_4
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
203
204
205
206
REF_CA1
97
1
+S
MDDR_VTT
25A
0.
+1
.5VSUS
C3
56
0.1u/16V_4
+1
.5VSUS
A A
C3
86
0.1u/16V_4
ace these Caps near So-Dimm2.
Pl
C3
57
0.1u/16V_4
C3
87
0.1u/16V_4
C3
58
0.1u/16V_4
C3
90
0.1u/16V_4
5
C3
59
0.1u/16V_4
C3
91
0.1u/16V_4
C3
0.1u/16V_4
C3
0.1u/16V_4
+1
.5VSUS
60
92
C3
0.1u/16V_4
C3
0.1u/16V_4
C3
61
93
98
180P/50V_4
C3
67
*22u/6.3V_6
4
C3
74
*22u/6.3V_6
C3
84
*22u/6.3V_6
+S
MDDR_VTT
C3
89
4.7U/6.3V_6
C3
88
0.1u/16V_4
R2
M_
B_VRFDQ[3]
3
2
04 *0_6
3mA
Si
Si
Si
ze Document Number Rev
ze Document Number Rev
ze Document Number Rev
DDR3
DDR3
DDR3
Date: Sheet
Date: Sheet
Date: Sheet
R2
1K/F_4
R2
1K/F_4
DIMM 2
DIMM 2
DIMM 2
08
+V
REF_DQ1
12
C3
53
0.1u/16V_4
Qu
Qu
Qu
anta Computer Inc.
anta Computer Inc.
anta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
ZRZ
ZRZ
ZRZ
10
10
10
1
1A
1A
1A
of
of
of
41Wednesday, March 18, 2015
41Wednesday, March 18, 2015
41Wednesday, March 18, 2015
(
VGA)
5
U24A
4
3
2
1
TE
ST_PG
ST#_BUF
AF30
AE31
AE29
AD28
AD30
AC31
AC29
AB28
AB30
AA31
AA29
Y28
Y30
W31
W29
V28
V30
U31
U29
T28
T30
R31
R29
P28
P30
N31
N29
M28
M30
K30
AK30
AK32
N10
AL27
L31
L29
PC
IE_RX0P
PC
IE_RX0N
PCIE_RX1P
PC
IE_RX1N
IE_RX2P
PC
PC
IE_RX2N
IE_RX3P
PC
PC
IE_RX3N
PC
IE_RX4P
IE_RX4N
PC
IE_RX5P
PC
IE_RX5N
PC
IE_RX6P
PC
PC
IE_RX6N
PCIE_RX7P
PC
IE_RX7N
NC#
V30
U31
NC#
NC#
U29
T28
NC#
T30
NC#
R31
NC#
NC#
R29
NC#
P28
NC#
P30
N31
NC#
NC#
N29
M28
NC#
NC#
M30
L31
NC#
NC#
L29
K30
NC#
CLOCK
PC
IE_REFCLKP
IE_REFCLKN
PC
ST_PG
TE
PER
STB
EV_
SP@Meso/Exo_S3
PC
PC
PCIE_TX1P
PC
PC
PC
PC
PC
PC
PC
PCI EXPRESS INTERFACE
PC
PC
PC
PC
PCIE_TX7P
PC
CALIBRATION
IE_CALR_TX
PC
IE_CALR_RX
PC
4
_TXP0[2]
D D
C C
B B
A A
X8 : CARRIZO ( GEN3)
PEG
X4 : CARRIZO-L (GEN2)
PEG
_TXN0[2]
PEG_TXP1[2]
PEG
_TXN1[2]
PEG
_TXP2[2]
PEG_TXN2[2]
PEG
_TXP3[2]
_TXN3[2]
PEG
PEG
_TXP4[2]
PEG
_TXN4[2]
PEG
_TXP5[2]
_TXN5[2]
PEG
_TXP6[2]
PEG
PEG
_TXN6[2]
PEG
_TXP7[2]
PEG
_TXN7[2]
CL
K_PCIE_VGAP[6]
K_PCIE_VGAN[6]
CL
R3
9 EV@1K_4
PER
5
IE_TX0P
IE_TX0N
IE_TX1N
IE_TX2P
IE_TX2N
IE_TX3P
IE_TX3N
IE_TX4P
IE_TX4N
IE_TX5P
IE_TX5N
IE_TX6P
IE_TX6N
IE_TX7N
NC#
W24
W23
NC#
NC#
V27
U26
NC#
U24
NC#
U23
NC#
NC#
NC#
NC#
NC#
NC#
P27
P26
NC#
NC#
P24
P23
NC#
NC#
M27
N26
NC#
T26
T27
T24
T23
AH30
AG31
AG29
AF28
AF27
AF26
AD27
AD26
AC25
AB25
Y23
Y24
AB27
AB26
Y27
Y26
W24
W23
V27
U26
U24
U23
T26
T27
T24
T23
P27
P26
P24
P23
M27
N26
Y22
AA22
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PC
IE_CALR_TX
PC
IE_CALR_RX
_RXP0_C
_RXN0_C
_RXP1_C
_RXN1_C
_RXP2_C
_RXN2_C
_RXP3_C
_RXN3_C
_RXP4_C
_RXN4_C
_RXP5_C
_RXN5_C
_RXP6_C
_RXN6_C
_RXP7_C
_RXN7_C
C5
56 EV_SP@0.22u/10 V_4
C553 EV_SP@0.22u/1 0V_4
35 EV_SP@0.22u/10 V_4
C5
33 EV_SP@0.22u/10 V_4
C5
C5
42 EV_SP@0.22u/10 V_4
37 EV_SP@0.22u/10 V_4
C5
C5
25 EV_SP@0.22u/10 V_4
27 EV_SP@0.22u/10 V_4
C5
31 EV_SP@0.22u/10 V_4
C5
28 EV_SP@0.22u/10 V_4
C5
C5
24 EV_SP@0.22u/10 V_4
22 EV_SP@0.22u/10 V_4
C5
21 EV_SP@0.22u/10 V_4
C5
C5
20 EV_SP@0.22u/10 V_4
19 EV_SP@0.22u/10 V_4
C5
18 EV_SP@0.22u/10 V_4
C5
AC-coupling capactior
CZ-8Lane :Gen3(220nF) CH4222K9B04
CZL-4Lane:Gen1/2(100nF) CH4103K1B08
GPU RESET
PU_RST_L[5]
DG
PC
IERST#[5,17,20,21]
7 EV@1.69K/F_4
R4
R5
3 EV@1K/F_4
3
_RXP0 [ 2]
PEG
PEG
_RXN0 [2]
PEG_RXP1 [2]
PEG
_RXN1 [2]
PEG
_RXP2 [ 2]
PEG_RXN2 [2]
PEG
_RXP3 [ 2]
_RXN3 [2]
PEG
PEG
_RXP4 [ 2]
PEG
_RXN4 [2]
PEG
_RXP5 [ 2]
_RXN5 [2]
PEG
_RXP6 [ 2]
PEG
PEG
_RXN6 [2]
PEG
_RXP7 [ 2]
PEG
_RXN7 [2]
+3
V_GFX
EV@0.1u/16V_4
C1
03
U5
2
1
EV@
3 5
CIE_VDDC_GFX
+P
4
TC7SH08FU
PER
ST#_BUF
R8
9
*EV@100K_4
X4
X8 : CARRIZO ( GEN3)
: CARRIZO-L (GEN2)
ST#_BUF [12]
PER
Qu
Qu
Qu
anta Computer Inc.
anta Computer Inc.
anta Computer Inc.
PROJECT :
PROJECT :
ze Document Num ber Rev
ze Document Num ber Rev
ze Document Num ber Rev
Si
Si
Si
Date: Sheet
Date: Sheet
2
Date: Sheet
Me
Me
Me
PROJECT :
so/Exo_S3_PCIE(1/6)
so/Exo_S3_PCIE(1/6)
so/Exo_S3_PCIE(1/6)
ZRZ
ZRZ
ZRZ
1A
1A
1A
11
11
11
1
41Friday, March 06, 2015
41Friday, March 06, 2015
41Friday, March 06, 2015
of
of
of
5
(
VGA)
The SMBus slave ID is default 0x41
Meso SCL/SDA PU : 47k ohm (CS34702JB21)
Exo SCL/SDA PU: 45.3kohm (CS34532FB18)
R5
ST#_BUF[11]
PER
2N
D_MBDATA[4,29]
D D
2N
D_MBCLK[4,29 ]
V_GFX
+3
R5
1 EV@10K_4
R5
0 *EV@10K_4
R353 *EV@10K_4
55 *EV@10K_4
R3
R3
57 *EV@10K_4
R3
56 *EV@10K_4
R36 *EV@10K_4
R3
64 EV@10K_4
1 *EV@5.1K/F_4
R3
52
R3
R3
54 *EV@10K_4
C C
Peak Current Control (PCC) GPIO_6.
FOR MESO ONLY
AMD GAE:GPIO_6 keep as unconnected, don’t stuff
the components on this relative circuitry
SY
S_SHDN#[31 ,36]
to power IC
PC
IE_REQ_GPU#[5]
GPIO_11, 12, and 13 FOR MESO ONLY,
EXO become NC
B B
A A
C5
55 EV@8.2P/50V_4C
54 EV@8.2P/50V_4C
C5
EXO MLPS setting PD
MEXO no mount
EXO ONLY: stuff Ra=> disable MLPS
stuff Rb=> enable MLPS
+3
V_GFX
5 *shortEV@0_4
EV@2N7002KDW
3 4
EV@2N7002KDW
DG
PU_OPP#
GP
U_PWM_PROCHOT#
DGPU_TDI
PU_TMS
DG
PU_TDO
DG
DG
PU_TRSTB
PEX_CLKREQ#
VG
A_ALERT
STEN
TE
EV@10K_4
MP_FAIL
TE
DG
PU_TCK
AMD GAE:CLKRFQ keep this pin as floating.
EVG
23
Y3
EV@
4 1
EVG
L4
+1
.8V_GFX
8V(5mA TSVDD)
1.
5
+3
V_GFX
R57
*EV@4.7K_4
8
R5
EV_SP@47K_4
126
PUT_DATA
DG
Q1
1A
+3V_GFX
R54
EV_SP@47K_4
5
DG
PUT_CLK
Q11B
R4
8 *EV@10K_4
PU/PD
U_THROTTING#[30 ]
GP
DG
AMD GAE:Debug port TDO left as floating.
ZYV not PU PEX_CLKREQ#
4
R3
EV@1K_4
ZYV not PD TEMP_FAIL
GP
U_PWM_PROCHOT#[37]
to power IC
3
Q3
2
*EV@ME2N7002DS-G_300MA
2
V_GFX
1
A-XTALI
27MHZ_10
A-XTALO
EV@BLM15AG121SN1D(120,500MA)_4
+3
2
3
Q5
V@ME2N7002DS-G_300MA
*E
91
R3
EV@1M/F_4
+3
C1
29
Exo@10U/6.3V_6X
1
V_GFX
Ra
65 *Exo@10K/F_4
R3
Rb
62 Exo@10K/F_4
R3
C1
31
EV@1U/10V_4X
R650 *EV@0_4
PU_AC_DC#[29]
+1.8V_GFX
+3V_GFX
R4
9 *EV@1K/F_4
C1
*EV@0.1u/16V_4
PEX_
C1
32
Exo@0.1U/16V_4X
DG
PU_OPP
EV@
2N7002K
R370 Meso@10K_4
R3
71 Meso@10K_4
R3
R3
02
CLKREQ#
R5
9 EV@10K_4
6 EV@10K_4
R5
68 *EV@10K_4
69 *EV@10K_4
DG
PU_OPP#
Q8
2
DG
DG
DG
GP
U_GPIO15
GP
VG
A_ALERT
TE
MP_FAIL
GPU_GPIO20
DG
DG
DG
DG
DG
TE
1
TP
GP
U_D+
U_D-
GP
U_GPIO28
GP
.8V_TSVDD
+1
PUT_DATA
PUT_CLK
PU_OPP#
U_GPIO6
PU_TRSTB
PU_TDI
PU_TCK
PU_TMS
PU_TDO
STEN
EVG
EVG
3
1
A-XTALO
A-XTALI
4
N9
L9
AE9
Y11
AE8
AD9
AC10
AD7
AC8
AC7
AB9
AB8
AB7
AB4
AB2
Y8
Y7
W6
V6
AC5
AC6
AA5
AA6
U1
U3
Y6
R1
R3
U6
U8
U7
T9
T8
T7
P10
P4
P2
N6
N5
N3
N1
M4
R6
M2
P8
P7
N8
AK10
AM10
N7
L6
L5
L3
L1
K4
K7
AF24
W8
W7
AD10
AJ9
AL9
AB16
AC16
AM28
AK28
AC22
AB22
T4
T2
R5
AD17
AC17
4
U24B
DVO
DB
G_DATA16
DBG_DATA15
DB
G_DATA14
DB
G_DATA13
DB
G_DATA12
G_DATA11
DB
G_DATA10
DB
DBG_DATA9
G_DATA8
DB
G_DATA7
DB
DB
G_DATA6
DB
G_DATA5
DB
G_DATA4
DB
G_DATA3
DBG_DATA2
DBG_DATA1
G_DATA0
DB
W6
NC#
NC#
V6
AC5
NC#
N#CAC6
NC#
AA5
NC#
AA6
U1/BP_0
NC#
U3/BP_1
NC#
Y6
NC#
SC
L
I2C
SD
A
GENERAL PURPOSE I/O
IO_0
GP
SM
BDATA
SM
BCLK
GP
IO_5_AC_BATT
PCC/GPIO_6
NC_GPIO_7
GP
IO_8_ROMSO
IO_9_ROMSI
GP
IO_10_ROMSCK
GP
NC_
GPIO_11
NC_
GPIO_12
GPIO_13
NC_
GP
IO_15_PWRCNTL_0
GP
IO_16
IO_17_THERMAL_INT
GP
GPIO_19_CTF
IO_20_PWRCNTL_1
GP
IO_21
GP
IO_22_ROMCSB
GP
IO_29
GP
GP
IO_30
CL
KREQB
JTAG_TRSTB
JT
AG_TDI
AG_TCK
JT
AG_TMS
JT
JT
AG_TDO
TE
STEN
AF24
NC#
GENERICB
NC_
GENERICD
NC_
NC_
GENERICE_HPD4
AJ9
NC#
G_CNTL0
DB
PX_
EN
NC_
DBG_VREFG
PLL/CLOCK
ALIN
XT
ALOUT
XT
_IN
XO
XO
_IN2
LUS
DP
THERMAL
DM
INUS
GP
IO28_FDO
VDD
TS
TS
VSS
SP@Meso/Exo_S3
EV_
DPA
DPB
DPC
NC#
AA1/PLL_ANALOG_IN
AA3/PLL_ANALOG_OUT
NC#
NC_AVSSN#AK26
NC_
NC_
DAC1
NC_
SVI2#1/GPIO_SVD
NC_
NC_
SVI2#2/GPIO_SVT
NC_
SVI2#3/GPIO_SVC
NC_
NC_GENLK_VSYNC
DAC2
NC_
NC_
DDC/AUX
NC_
NC_
NC_
NC#
NC#
NC#
NC#AG5
NC#
NC#
NC#
NC#AK1
NC#
NC#
NC#
NC#
NC#AJ7
NC#
NC#
NC#
NC#
NC#
NC#V2
NC#
NC#
NC#Y2
NC#J8
DCM/NC_R
NC_
AVSSN#AJ25
NC_
AVSSN#AG25
NC_HSYNC
VSYNC/WAKEb
NC_
AVDD
NC_
AVSSQ
NC_
NC_
VDD1DI
VSS1DI
NC_
GENLK_CLK
SWAPLOCKA
SWAPLOCKB
NC_
DDC1CLK
DDC1DATA
AUX1P
NC_
AUX1N
NC_
NC_
AUX2P
AUX2N
NC_
NC#
NC#
DDCVGACLK
DDCVGADATA
AF2
AF4
AG3
AH3
AH1
AK3
AK5
AM3
AK6
AM5
AH6
AK8
AL7
V4
U5
Y4
W5
G
B
RSET
NC
PS_
0
PS_
1
2
PS_
PS_
3
TS
_A
AE16
AD16
AF2
AF4
AG3
AG5
AH3
AH1
AK3
AK1
AK5
AM3
AK6
AM5
AJ7
AH6
AK8
AL7
V4
U5
V2
Y4
W5
Y2
J8
AA1
AA3
AM26
Debug port for the die
AK26
AL25
R403
AJ25
*MESO@10k_4
AH24
AG25
AH26
AJ27
PC
IE_WAKE#_GPU
AD22
AG24
AE22
AE23
AD23
12
AM
AK12
76 Meso@0_4
R3
AL11
AJ11
R3
72 Meso@0_4
AL13
AJ
13
AG13
AH12
AC19
0
PS_
AD19
1
PS_
AE17
PS_
2
AE20
3
PS_
AE19
R6
5
*EV@0_4
AE6
AE5
AD2
AD4
AD13
AD11
AE16
AD16
AC1
TP
AC3
TP
3
.8V_GFX
+1
C1
23
EV@10U/6.3V_6X
CIE_VDDC_G FX
+P
C9
3
Exo@10U/6.3V_8X
DP_VDDC
EXO MESO
10u X1
1u X1
0.1u X1
TP29
R5
2
*Meso@16.2K/F_4
PLL_ANALOG_OUT: Provide a pull-down
resistor on the PCB (DNI).FOR TOPAZ ONLY
+3
1u X1
0.1u X1
V_GFX
PCIeR Optimized Buffer Flush/Fill (OBFF)
on WAKEB FOR TOPAZ ONLY
R4
06
EV@4.7K_4
1
02
R4
*EV@10K_4
U_SVD_R
GP
U_SVT
GP
GP
U_SVC_R
PS0[5:1]
PS1[5:1]
PS2[5:1]
PS3[5:1]
+1
.8V_GFX
31
30
.8V_GFX
+1
3
C1
27
EV@1U/10V_4X
C8
9
EV@1U/10V_4X
2
Q12
3
PC
IE_LAN_WAKE#
*EV@ME2N7002DS-G_300MA
+1.8V_GFX
C72
Exo@0.1U/16V_4X
+3V_GFX
7
C8
Exo@0.1U/16V_4X
EXO
11001
11000
11000
11xxx
R7
3
EV@8.45K/F_4
PS_
0
4
R6
EV@2K/F_4
R7
2
EV_SP@6.98K/F_4
PS_
3
R6
3
EV_SP@4.99K/F_4
C1
26
Exo@0.1U/16V_4X
C8
8
EV@0.1u/16V_4
U24G
AG15
NC_DP_VDDR#1
AG16
NC_
AF16
NC_
AG17
NC_
AG18
NC_
AG19
NC_
AF14
DP_PVDD
AG20
NC_DP_VDDC#1
AG21
NC_
AF22
NC_
AG22
NC_
AD14
DP
AG14
NC_DP_VSSR#1
AH14
NC_
AM14
NC_
AM16
NC_
AM18
NC_
AF23
NC_
AG23
NC_
AM20
NC_
AM22
NC_
AM24
NC_
AF19
NC_
AF20
NC_
AE14
DP_VSSR
AF17
NC_
EV_SP@Meso/Exo_S3
DP_VDDR#2
DP_VDDR#3
DP_VDDR#4
DP_VDDR#5
DP_VDDR#6
DP_VDDC#2
DP_VDDC#3
DP_VDDC#4
_VDDC
DP_VSSR#2
DP_VSSR#3
DP_VSSR#4
DP_VSSR#5
DP_VSSR#6
DP_VSSR#7
DP_VSSR#8
DP_VSSR#9
DP_VSSR#10
DP_VSSR#11
DP_VSSR#12
UPHYAB_DP_CALR
NC/DP POWERDP POWER
SVDSVC
NC#AE11
NC#
NC#
NC#
NC#
NC#
NC#AF6
NC#
NC#
NC#
NC#AE1
NC#
NC#
NC#
NC#
NC#
NC#
NC#
NC#
NC#
NC#
NC#
NC#
Output Voltage
00
0
110
1
10
PCIE_LAN_WAKE# [5,2 0,21]
GP
GP
U_SVD_R
U_SVC_R
EXO Level Shift
+1.8V_GFX
U_SVD_R
GP
GP
U_SVC_R
Hynix 2G
Samsung 2G
Micro 2G
+1.8V_GFX
77
R3
*Meso@10K_4
78
R3
Meso@10K_4
MESO
11001
11001
11000
73
R3
Meso@10K_4
74
R3
*Meso@10K_4
PS_3[3:1]
000
001
010
011 6.98K
11xxx
+1
.8V_GFX
R7
5
EV_SP@8.45K/F_4
PS_
1
35
C1
*EV@0.01U/50V_4X
1
R7
EV_SP@2K/F_4
GEN2(CZL):R75 NC
R71 4.75K(CS24752FB12)
GEN3(CZ) :R75 8.45K(CS28452FB12)
R71 2K(CS22002FB19)
PS_3 [5,4] should be 11 due to this is no output/audio design
C1
34
*EV@680n/6.3V_4
38
C1
*EV_SP@0.01U/50V_4X
2
AE11
EXTERNAL THERMAL SENSOR
AF11
AF11
AE13
AE13
AF13
AF13
AG8
AG8
AG10
AG10
AF6
AF7
AF7
AF8
AF8
AF9
AF9
AE1
AE3
AE3
AG1
AG1
AG6
AG6
AH5
AH5
AF10
AF10
AG9
AG9
AH8
AH8
AM6
AM6
AM8
AM8
AG7
AG7
AG11
AG11
AE10
AE10
DGPUT_CLK GPU_D+
PUT_DATA
DG
A_ALERT
VG
1.1 Volts
1.0 Volts
0.9 Volts
Exo Boot
.8 Volts
+3
V_GFX
U2
1
CA
VC
3
A
2
GND
Exo@G2129TL1U
1
VC
CA
3
A
2
D
GN
Ex
anta P/N====>
Qu
4.53K: CS24532FB08 4.99K: CS24992FB26
6.98K: CS26982FB01 3.24K: CS23242FB17
5.62K: CS25622FB18 8.45K: CS28452FB12
4.75K: CS24752FB12 2K: CS22002FB19
2
3
6
CB
VC
4
B
5
OE
U4
6
VC
CB
4
B
5
OE
o@G2129TL1U
256Mx16 *4,1000Mhz
256Mx16 *4,1000Mhz
256Mx16 *4,1000Mhz
.8V_GFX
+1
R7
*EV@0_4
PS_
R6
EV@4.75K/F_4
GP
R4
0 Exo@10K_4
+3V_GFX+1.8V_GFX
GP
4
2
8
U_GPIO15
U_GPIO20
+1
GP
U_SVT
Vendor P/NTypeVendor
H5TC4G63AFR-11C
K4W4G1646D-BC1A
MT41J256M16HA-093G:E
36
C1
*EV@0.01U/50V_4X
5
U2
8
LK
SC
7
SD
A
6
AL
ERT#
4
OVERT#
*EV@G781P8
.8V_GFX
75 Meso@0_4
R3
1
V_GFX
+3
C5
17
*EV@0.1u/16V_4
1
C
VC
2
DX
P
3
DX
N
5
GND
+3
V_GFX
GP
U_GPIO15
U_GPIO20
GP
U_SVD_R
GP
GP
U_SVC_R
BIT[3:1]
000
001
010
011
100
101
110
111
Si
Si
Si
Date: Sheet
Date: Sheet
Date: Sheet
16
C5
*EV@2200p/50V_4
GPU_D-
R359
R43
*Exo@10K_4
Exo@10K_4
58
4
R3
R4
Exo@10K_4
*Exo@10K_4
GP
U_SVT_R [37]
U_SVD_R [37]
GP
GP
U_SVC_R [37]
to power IC
R3pdR3pu
4.75K
NC
8.45K
2K
2K4.53K
4.99KH5TC4G63CFR-N0CHynix 2G 256Mx16 *4,1000Mhz
BIT[5:4]
C ( nF)
00
680
01
82
10
10
11
NC
Rpu Rpd
4750NC
8450
2000
20004530
49906980
49904530
56203240
100003400
NC4750
Qu
Qu
Qu
PROJECT :
PROJECT :
ze D ocument Number Rev
ze D ocument Number Rev
ze D ocument Number Rev
PROJECT :
so/Exo_S3_Main(2/6)
so/Exo_S3_Main(2/6)
so/Exo_S3_Main(2/6)
Me
Me
Me
1
anta Computer Inc.
anta Computer Inc.
anta Computer Inc.
ZRZ
ZRZ
ZRZ
of
of
of
12
12
12
1A
1A
1A
41Wednesday, March 18, 2015
41Wednesday, March 18, 2015
41Wednesday, March 18, 2015
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