PTC AV100 Service Manual AT24C02
Features
• Low-voltage and Standard-voltage Operation
– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
– 2.5 (VCC = 2.5V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
• Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),
1024 x 8 (8K) or 2048 x 8 (16K)
• 2-wire Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• Bi-directional Data Transfer Protocol
• 100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Compatibility
• Write Protect Pin for Hardware Data Protection
• 8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes
• Partial Page Writes are Allowed
• Self-timed Write Cycle (10 ms max)
• High-reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• Automotive Grade and Extended Temperature Devices Available
• 8-lead JEDEC SOIC, 8-pin PDIP and 8-lead TSSOP Packages
Description
The AT24C01A/02/04/08/16 provides 1024/2048/4096/8192/16384 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as
128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many
industrial and commercial applications where low-power and low-voltage operation
are essential. The AT24C01A/02/04/08/16 is available in space-saving 8-pin PDIP,
(AT24C01A/02/04/08/16), 8-lead TSSOP (AT24C01A/02/04/08/16) and 8-lead
JEDEC SOIC (AT24C01A/02/04/08/16) packages and is accessed via a 2-wire serial
interface. In addition, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to
5.5V), 2.5V (2.5V to 5.5V) and 1.8V (1.8V to 5.5V) versions.
2-wire
Serial EEPROM
1K (128 x 8)
2K (256 x 8)
4K (512 x 8)
8K (1024 x 8)
16K (2048 x 8)
AT24C01A
AT24C02
AT24C04
Pin Configurations
Pin Name Function
A0 - A2 Address Inputs
SDA Serial Data
SCL Serial Clock Input
WP Write Protect
NC No Connect
8-pin PDIP
8
A0
A1
A2
GND
1
2
3
4
VCC
7
WP
6
SCL
5
SDA
A0
A1
A2
GND
A0
A1
A2
GND
8-lead TSSOP
1
2
3
4
8-lead SOIC
1
2
3
4
8
7
6
5
8
7
6
5
AT24C08
AT24C16
VCC
WP
SCL
SDA
VCC
WP
SCL
SDA
Rev. 0180E–09/00
1
Absolute Maximum Ratings
Operating Temperature.................................. -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground.....................................-1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Block Diagram
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive
edge clock data into each EEPROM device and negative
edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bi-directional for
serial data transfer. This pin is open-drain driven and may
be wire-ORed with any number of other open-drain or
open-collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1
and A0 pins are device address inputs that are hard wired
for the AT24C01A and the AT24C02. As many as eight
1K/2K devices may be addressed on a single bus system
(device addressing is discussed in detail under the Device
Addressing section).
The AT24C04 uses the A2 and A1 inputs for hard wire
addressing and a total of four 4K devices may be
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AT24C01A/02/04/08/16
addressed on a single bus system. The A0 pin is a
no connect.
The AT24C08 only uses the A2 input for hardwire addressing and a total of two 8K devices may be addressed on a
single bus system. The A0 and A1 pins are no connects.
The AT24C16 does not use the device address pins, which
limits the number of devices on a single bus to one. The
A0, A1 and A2 pins are no connects.
WRITE PROTECT (WP): The AT24C01A/02/04/16 has a
Write Protect pin that provides hardware data protection.
The Write Protect pin allows normal read/write operations
when connected to ground (GND). When the Write Protect
pin is connected to V
enabled and operates as shown in the following table.
, the write protection feature is
CC
WP Pin
Status
At V
At GND Normal Read/Write Operations
24C01A 24C02 24C04 24C08 24C16
Full (1K)
CC
Array
Part of the Array Protected
Full (2K)
Array
Full (4K)
Array
Normal
Read/
Write
Operation
Upper
Half
(8K)
Array
Memory Organization
AT24C01A, 1K SERIAL EEPROM: Internally organized
with 128 pages of 1 byte each, the 1K requires a 7-bit data
word address for random word addressing.
AT24C01A/02/04/08/16
AT24C02, 2K SERIAL EEPROM: Internally organized with
256 pages of 1-byte each, the 2K requires an 8-bit data
word address for random word addressing.
AT24C04, 4K SERIAL EEPROM: The 4K is internally
organized with 256 pages of 2 bytes each. Random word
addressing Chip Number requires a 9-bit data word
address.
AT24C08, 8K SERIAL EEPROM: The 8K is internally
organized with 4 blocks of 256 pages of 4 bytes each. Random word addressing requires a 10-bit data word address.
AT24C16, 16K SERIAL EEPROM: The 16K is internally
organized with 8 blocks of 256 pages of 8 bytes each. Random word addressing requires an 11-bit data word
address.
Pin Capacitance
(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V.
Symbol Test Condition Max Units Conditions
C
I/O
C
IN
Input/Output Capacitance (SDA) 8 pF V
I/O
= 0V
Input Capacitance (A0, A1, A2, SCL) 6 pF VIN = 0V
Note: 1. This parameter is characterized and is not 100% tested.
DC Characteristics
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C,
= +1.8V to +5.5V (unless otherwise noted).
V
CC
Symbol Parameter Test Condition Min Typ Max Units
V
CC1
V
CC2
V
CC3
V
CC4
I
CC
I
CC
I
SB1
I
SB2
I
SB3
I
SB4
I
LI
I
LO
V
IL
V
IH
V
OL2
V
OL1
Note: 1. VIL min and V
Supply Voltage 1.8 5.5 V
Supply Voltage 2.5 5.5 V
Supply Voltage 2.7 5.5 V
Supply Voltage 4.5 5.5 V
Supply Current VCC = 5.0V READ at 100 kHz 0.4 1.0 mA
Supply Current VCC = 5.0V WRITE at 100 kHz 2.0 3.0 mA
Standby Current VCC = 1.8V VIN = VCC or V
Standby Current VCC = 2.5V VIN = VCC or V
Standby Current VCC = 2.7V VIN = VCC or V
Standby Current VCC = 5.0V VIN = VCC or V
Input Leakage Current VIN = VCC or V
Output Leakage Current V
Input Low Level
Input High Level
(1)
(1)
OUT
= V
CC
or V
SS
SS
SS
SS
SS
SS
-0.6 VCC x 0.3 V
VCC x 0.7 VCC + 0.5 V
0.6 3.0 µA
1.4 4.0 µA
1.6 4.0 µA
8.0 18.0 µA
0.10 3.0 µA
0.05 3.0 µA
Output Low Level VCC = 3.0V IOL = 2.1 mA 0.4 V
Output Low Level VCC = 1.8V IOL = 0.15 mA 0.2 V
max are reference only and are not tested.
IH
3
AC Characteristics
Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and
100 pF (unless otherwise noted).
2.7-, 2.5-, 1.8-volt 5.0-volt
Symbol Parameter
UnitsMin Max Min Max
f
SCL
t
LOW
t
HIGH
t
I
t
AA
t
BUF
t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
R
t
F
t
SU.STO
t
DH
t
WR
Endurance
Clock Frequency, SCL 100 400 kHz
Clock Pulse Width Low 4.7 1.2 µs
Clock Pulse Width High 4.0 0.6 µs
Noise Suppression Time
(1)
Clock Low to Data Out Valid 0.1 4.5 0.1 0.9 µs
Time the bus must be free before
a new transmission can start
(1)
Start Hold Time 4.0 0.6 µs
Start Setup Time 4.7 0.6 µs
Data In Hold Time 0 0 µs
Data In Setup Time 200 100 ns
Inputs Rise Time
Inputs Fall Time
(1)
(1)
Stop Setup Time 4.7 0.6 µs
Data Out Hold Time 100 50 ns
Write Cycle Time 10 10 ms
(1)
5.0V, 25°C, Byte Mode 1M 1M Write
Note: 1. This parameter is characterized and is not 100% tested.
100 50 ns
4.7 1.2 µs
1.0 0.3 µs
300 300 ns
Cycles
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is nor-
mally pulled high with an external device. Data on the SDA
pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL
high periods will indicate a start or stop condition as
defined below.
START CONDITION: A high-to-low transition of SDA with
SCL high is a start condition which must precede any
other command (refer to Start and Stop Definition timing
diagram).
STOP CONDITION: A low-to-high transition of SDA with
SCL high is a stop condition. After a read sequence, the
stop command will place the EEPROM in a standby power
mode (refer to Start and Stop Definition timing diagram).
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AT24C01A/02/04/08/16
ACKNOWLEDGE: All addresses and data words are seri-
ally transmitted to and from the EEPROM in 8-bit words.
The EEPROM sends a zero to acknowledge that it has
received each word. This happens during the ninth clock
cycle.
STANDBY MODE: The AT24C01A/02/04/08/16 features a
low-power standby mode which is enabled: (a) upon
power-up and (b) after the receipt of the STOP bit and the
completion of any internal operations.
MEMORY RESET: After an interruption in protocol, power
loss or system reset, any 2-wire part can be reset by following these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition.
Bus Timing
SCL: Serial Clock, SDA: Serial Data I/O
Write Cycle Timing
SCL: Serial Clock, SDA: Serial Data I/O
AT24C01A/02/04/08/16
(1)
t
WR
Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write
cycle.
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