Polaroid IC-V8000 User Manual
SERVICE
MANUAL
VHF FM TRANSCEIVER
INTRODUCTION
DANGER
This service manual describes the latest service information
for the IC-V8000 VHF FM TRANSCEIVER at the time of pub-
lication.
ORDERING PARTS
Be sure to include the following four points when ordering
replacement parts:
1. 10-digit order numbers
2. Component part number and name
3. Equipment model name and unit name
4. Quantity required
<SAMPLE ORDER>
1110003200 S.IC TA31136FN IC-V8000 MAIN UNIT 5 pieces
8810006050 Screw Icom screw E7 IC-V8000 Chassis 10 pieces
Addresses are provided on the inside back cover for your
convenience.
NEVER connect the transceiver to an AC outlet or to a DC
power supply that uses more than 16 V. This will ruin the
transceiver.
DO NOT expose the transceiver to rain, snow or any liquids.
DO NOT reverse the polarities of the power supply when
connecting the transceiver.
DO NOT apply an RF signal of more than 20 dBm (100mW)
to the antenna connector. This could damage the transceiver's front end.
REPAIR NOTES
1. Make sure a problem is internal before disassembling
the transceiver.
2. DO NOT open the transceiver until the transceiver is dis-
connected from its power source.
3. DO NOT force any of the variable components. Turn
them slowly and smoothly.
4. DO NOT short any circuits or electronic parts. An insulat-
ed turning tool MUST be used for all adjustments.
5. DO NOT keep power ON for a long time when the transceiver is defective.
6. DO NOT transmit power into a signal generator or a
sweep generator.
7. ALWAYS connect a 50 dB to 60 dB attenuator between
the transceiver and a deviation meter or spectrum analyzer when using such test equipment.
8. READ the instructions of test equipment thoroughly
before connecting equipment to the transceiver.
To upgrade quality, any electrical or mechanical parts and
internal circuits are subject to change without notice or
obligation.
VERSION
Asia
C.S.America
U.S.A.
SYMBOL
SEA
CSA
CSA-1
USA-2
USA-3
SUPPLIED MICROPHONE
HM-118N
HM-118TN
HM-133V
HM-118TAN
SECTION 1 SPECIFICATIONS
SECTION 2 INSIDE VIEWS
SECTION 3 DISASSEMBLY AND OPTION INSTRUCTIONS
SECTION 4 CIRCUIT DESCRIPTION
4-1 RECEIVER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
4-2 TRANSMITTER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
4-3 PLL CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
4-4 POWER SUPPLY CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
4-5 PORT ALLOCATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
SECTION 5 PARTS LIST
SECTION 6 MECHANICAL PARTS AND DISASSEMBLY
6-1 IC-V8000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1
6-2 HM-133V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3
SECTION 7 SEMI-CONDUCTOR INFORMATION
SECTION 8 BOARD LAYOUTS
8-1 HM-133V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1
8-2 LOGIC BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-2
8-3 MAIN UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4
SECTION 9 BLOCK DIAGRAM
SECTION 10 VOLTAGE DIAGRAM
10-1 MAIN UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1
10-2 LOGIC BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-2
10-3 HM-133V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-3
TABLE OF CONTENTS
1 - 1
‘‘
GENERAL
• Frequency coverage :
*Specifications Guaranteed: 144–148 MHz only
• Type of emission : FM (F2D / F3E)
• Frequency stability : ± 10 ppm (–10˚C to +60˚C; +14˚F to +140˚F)
• Tuning steps : 5, 10, 12.5, 15, 20, 25, 30 or 50 kHz
• Antnna connector : SO-239 (50 Ω)
• Power supply requirement : 13.8 V DC (Operable voltage range: 11.7 to 15.9 V)
(negative ground)
• Number of memory channel : 207 channels (including 6 scan edges and 1 call channel)
• Call channel : 1 channel
• Scanning mode : Full, Program, Priority, Memory, Channel, Skip, Tone, DTCS, Bank and WX
• Current drain (approx.) :
• Usable temperature range : –10˚C to +60˚C; +14˚F to +140˚F
• Dimensions (projections not included) : 150(W)
× 50(H) × 150(D) mm; 5 29⁄32(W) × 1 31⁄32(H) × 5 29⁄32(D) in.
• Weight : 1.09 kg; 12.3 oz.; 38.4 oz
‘‘
TRANSMITTER
• RF output power (at 13.8 V DC) : 75 W / 25 W / 10 W / 5 W (High / Middle High / Middle Low / Low)
• Modulation system : Variable reactance frequency modulation
• Maximum frequency deviation : Narrow: ±2.5 kHz*; Wide: ±5.0 kHz
• Spurious emissions : Less than –60 dB
• Microphone connector : 8-pins modular (600 Ω)
‘‘
RECEIVER
• Receive system : Double conversion superheterodyne system
• Intermediate frequencies : 1st 21.7 MHz
2nd 450 kHz
• Sensitivity : 0.15 µV at 12 dB SINAD (typical)
• Squelch sensitivity : 0.08 µV at threshold (typical)
• Selectivity : Narrow; More than ±3.0 kHz at –6 dB, Less than ±9.0 kHz at –55 dB*
Wide; More than ±6.0 kHz at –6 dB, Less than ±14.0 kHz at –60 dB
• Spurious and image rejection : 60 dB (typical)
• Audio output power (at 7.2 V DC) : More than 2.0 W at 10% distortion with an 8 Ω load
• Ext. speaker connector : 3-conductor 3.5(d) mm (
1
⁄8”)/8 Ω
*[USA] version only
All stated specifications are subject to change without notice or obligation.
Transmit
Receiving
SECTION 1 SPECIFICATIONS
Version
[USA]
[SEA]
[CSA]
Receive
136.000–174.000 MHz*
Transmit
144.000–148.000 MHz
140.000–150.000 MHz*
136.000–174.000 MHz*
15 A
9.0 A
6.0 A
5.0 A
1.0 A
0.8 A
High (75 W)
Middle High (25 W)
Middle Low (10 W)
Low (5 W)
Max. audio
Stand-by
SECTION 2 INSIDE VIEWS
2 - 1
•
MAIN UNIT
•
LOGIC BOARD
Reference oscillator
(X1: CR-659)
VCO circuit
Antenna switching circuit
(D12, D27: XB15A407,
D19: XB15A308,
D16: HVU131TRF)
AF power amplifier
(Q23: RD70HVF1)
1st IF filter
(FI3, FI4: FL-310)
2nd IF filter
(FI1: CFWS450F,
FI2: CFWS450HT)
EEPROM
(IC5: HN58X2432TI)
CPU
(IC7: HD6433876B53H)
System clock
(X1: CR-663)
Speaker
Reset IC
(IC4: S-80942ANMP-DD6)
LOGIC board
SECTION 3 DISASSEMBLY AND OPTION INSTRUCTIONS
3 - 1
Cover
MP10
Front panel
Chassis
MP9
MP6
MP15
J5 (MF1)
J6 (SP7)
Chassis
Main unit
MP6
MP6
MP7
MP4
J1
A
• REMOVING THE COVER
1 Unscrew 4 screws, MP10.
2 Remove the cover in the direction of the arrow.
• REMOVING THE FRONT PANEL
1 Unscrew 3 screws, MP9.
2 Unplug J6 to separate front panel and chassis.
3 Remove the front panel in the direction of the arrow.
4 Unplug J5 to separate fan and chassis.
5 Unscrew 2 screws, MP6, to separate MP15 and chassis.
• REMOVING THE MAIN UNIT
1 Unscrew 11 screws, MP6, and 2 screws, MP7, and 2
screws, MP4.
2 Unsolder 3 points, A, to remove the antenna connector.
3 Remove the Main unit in the direction of the arrow.
• OPTIONAL UNIT INSTALLATION
1 Install the optional unit as illustrated below. Insert it tight-
ly to avoid bad contact.
4 - 1
SECTION 4 CIRCUIT DESCRIPTION
4-1 RECEIVER CIRCUITS
4-1-1 ANTENNA SWITCHING CIRCUIT
(MAIN UNIT)
Received signals passed through the low-pass filter (L44,
L47, L48, L51, C190, C197, C203, C208, C210, C217,
C218). The filtered signals are applied to the 1/4 λ type
antenna switching circuit (D16, D19).
The antenna swtiching circuit functions as a low-pass filter
while transmitting. However, its impedance becomes very
high while D16 and D19 are turn ON. Thus transmit signals
are blocked from entering the receiver circuits. The antenna
switching circuit employs a 1/4 λ type diode swtiching system. The passed signals are then applied to the RF amplifier circuit.
4-1-2 RF CIRCUIT (MAIN UNIT)
The RF circuit amplifies signals within the range of frequency coverage and filters out-of-band signals.
The signals from the antenna switching circuit are applied to
the limitter (D15), and are then passed through the bandpass filter (D13, L43, C183, C182). The filtered signals are
amplified at the RF amplifier (Q27), then applied to the 1st
mixer circuit after out-of-band signals are suppressed at the
bandpass filter (D9–D11).
D9–D11, D13 employ varactor diodes that track the bandpass filters and are controlled by the T1–T3 signals from the
D/A convertor (IC5, pins 10, 11, 23). These diodes tune the
center frequency of an RF passband for wide bandwidth
receiving and good image response rejection.
4-1-3 1ST MIXER AND 1ST IF CIRCUITS
(MAIN UNIT)
The 1st mixer circuit converts the received signal to a fixed
frequency of the 1st IF signal with a PLL output frequency.
By changing the PLL frequency, only the desired frequency
will pass through two crystal filters at the next stage of the
1st mixer.
The signals from the RF circuit are mixed at the 1st mixer
(Q19) with a 1st LO signal coming from the VCO circuit to
produce a 21.70 MHz 1st IF signal.
The 1st IF signal is applied to two crystal filters (FI3 and FI4)
to suppress out-of-band signals. The filtered 1st IF signal is
applied to the IF amplifier (Q16), then applied to the 2nd
mixer circuit (IC4, pin 16).
4-1-4 2ND IF AND DEMODULATOR CIRCUITS
(MAIN UNIT)
The 2nd mixer circuit converts the 1st IF signal to a 2nd IF
signal. Adouble conversion superheterodyne system (which
converts receive signal twice) improves the image rejection
ratio and obtain stable receiver gain.
The 1st IF signal from the IF amplifier is applied to the 2nd
mixer section of the FM IF IC (IC4, pin 16), and is mixed with
the 2nd LO signal to be converted to a 450 kHz 2nd IF signal.
The FM IF IC contains the 2nd mixer, limiter amplifier, quadrature detector and active filter circuits. A21.25 MHz 2nd LO
signal is produced at the PLL circuit.
The 2nd IF signal from the 2nd mixer (IC4, pin 3) passes
through a ceramic filter (FI1; When wide is selected, F2;
When Narrow is selected. (Narrow is [USA] version only.)) to
remove unwanted heterodyned frequencies. It is then amplified at the limiter amplifier (IC4, pin 5) and applied to the
quadrature detector (IC4, pins 10, 11) to demodulate the 2nd
IF signal into AF signals.
4-1-5 AF CIRCUIT (MAIN AND LOGIC UNITS)
The AF amplifier circuit amplifies the demodulated AF signals to drive a speaker.
AF signals from the FM IF IC (IC2, pin 9) are applied to the
analog swtich (LOGIC UNIT; IC6, pin 1) via the high pass filter (IC3c, pins 9, 8). The output signals from pin 11 are
applied to the volume adjustment pot (LOGIC UNIT; R31).
The signals are applied to the AF power amplifier (IC9, pin
1) after passing through the AFmute swtich (Q29).
Mixer
16
Limiter
amp.
2nd IF filter
450 kHz
PLL IC
IC1
X1
21.25 MHz
IC4 TA31136F
12
1st IF from the IF amplifier (Q16)
"SD" signal to the CPU pin 97
11109
87 5 3
AF signal "DETO"
R5V
X2
R55
C84
C85
R64R59
R71
"SQLIN" signal from the
D/A convertor (IC5, pin 214
R73
C105 C101
C116
2
16 1
Active
filter
FI2
Noise
detector
FM
detector
13
"NOIS" signal to the CPU pin 19
RSSI
Noise
comp.
R63
LPF
• 2ND IF AND DEMODULATOR CIRCUITS
4 - 2
The AF signals are applied to the AF power amplifier circuit
(IC9, pin 1) to obtain the specified audio level. The amplified
AF signals, output from pin 4, are applied to the internal
speaker (CHASSIS UNIT; SP1) via the speaker jack (J6)
when no plug is connected to the external speaker jack (J1).
4-1-6 SQUELCH CIRCUIT
(MAIN AND LOGIC UNITS)
Asquelch circuit cuts out AF signals when no RF signals are
received. By detecting noise components in the AF signals,
the squelch switches the analog swtich.
Aportion of the AF signals from the FM IF IC (IC4, pin 9) are
applied to the D/A converter (IC5, pin 13) as the DETO signal. The signals from the D/A converter (IC5, pin 14) are
applied to the FM IF IC active filter section (IC4, pin 8) where
noise components are amplified and detected with an internal noise detector via the SQLIN line.
The trigger circuit converts the detected signals to a HIGH
or LOW signal and applies this (from pin 13) to the CPU
(LOGIC UNIT; IC7, pin 19) as the NOIS signal.The CPU
controls the analog swtich IC (LOGIC UNIT; IC6) via the
expander IC (LOGIC UNIT; IC8). When the CPU receives a
HIGH level NOIS signal, the CPU controls the RMUT line to
cut the AF signals at the analog swtich IC (LOGIC UNIT;
IC6). At the same time, the AFON line controls the AF mute
circuit (Q29) to cut out the VOLOUT signal for the AF power
amplifier (IC9).
4-2 TRANSMITTER CIRCUITS
4-2-1 MICROPHONE AMPLIFIER CIRCUIT
(LOGIC AND MAIN UNITS)
The microphone amplifier circuit amplifies audio signals with
+6 dB/octave pre-emphasis from the microphone to a level
needed for the modulation circuit.
The AF signals from the microphone pass through the MIC
switch (IC2, D4) and high-pass filter (IC3a, pin 2), and are
then applied to the microphone amplifier circuit (IC3d, pin
12) via the R39 and C47 for +6 dB/octave pre-emphasis.
The amplified AF signals are applied to the analog swtich
(IC6, pin 4), and are then applied to the D/Aconverter (MAIN
UNIT; IC5, pin 1) via the MODIN signal. The AF signals are
applied to the modulator circuit via the MOD signal.
4-2-2 MODULATION CIRCUIT (MAIN UNIT)
The modulation circuit modulates the VCO oscillating signal
(RF signal) using the microphone audio signals.
The audio signals (SHIFT) change the reactance of D2 to
modulate an oscillated signal at the VCO (Q6, D4). The
oscillated signal is amplified at the LO (Q9) and buffer (Q11)
amplifiers, then applied to the TX/RX switch circuit (D6, D7).
4-2-3 DRIVE/POWER AMPLIFIER CIRCUITS
(MAIN UNIT)
The signal from the VCO circuit passes through the TX/RX
swtiching circuit (D6) and is amplified at the pre-drive (Q17),
drive (Q18, Q20) and power (Q23) amplifiers to obtain 75 W
of RF power (at 13.8 V DC/typical). The amplified signal
passes through the low-pass filter (L37, L39, C151, C156,
C159, C167, C176, C227–C229), and then applied to the
antenna swtiching circuit (D12). The signal is applied to the
antenna connector (CHASSIS UNIT; J1) after being passed
through the low-pass filter (L44, L47, L48, L51, C190, C197,
C203, C208, C210, C217, C218).
The bias current of the drive (Q18, Q20) and power (Q23)
amplifiers is controlled by the APC circuit to stabilize the output power.
4-2-4 APC CIRCUIT (MAIN UNIT)
The APC (Automatic Power Control) circuit (IC6a, Q26) protects drive and power amplifiers from excessive currents
and selects HIGH or LOW output power.
The output voltage from the power detector circuit (D14,
D17) is applied to the differential amplifier (IC6a, pin 2), and
the “T3” signal from the D/A converter (IC5, pin 23) is
applied to the other input for reference.
When the driving current increases, the input voltage of the
differential amplifier (IC6a, pin 2) will be increased. In such
cases, the differential amplifier output voltage (pin 1) is
decreased to reduce the drive current.
Q26 is controlled by the TXC signal from the expander IC
(IC2, pin 14) to select HIGH or LOW output power.
Q23
Power
amp.
Q20
Driver
amp.
Q18
Driver
amp.
IC6a
+
HV
RF signal from
PLL IC (IC1)
to antenna
T1
TXC
Q26
+5V
APC control circuit
Power detector
circuit (D12, D14)
D14 D12
L44, C190, C191,
C196, C197
LPF
ANT
SW
SWHV
2
3
1
• APC CIRCUIT
4 - 3
4-3 PLL CIRCUITS
4-3-1 PLL CIRCUIT (MAIN AND LOGIC UNITS)
A PLL circuit provides stable oscillation of the transmit frequency and receive 1st LO frequency. The PLL output compares the phase of the divided VCO frequency to the reference frequency. The PLL output frequency is controlled by
the divided ratio (N-data) of a programmable divider.
An oscillated signal from the TX and RX-VCO circuits passes through the LO and buffer amplifiers (Q9, Q12) is applied
to the PLL IC (IC1, pin 6) and is prescaled in the PLL IC
based on the divided ratio (N-data). The reference signal is
generated at the reference oscillator (X1) and is also applied
to the PLL IC. The PLL IC detects the out-of-step phase
using the reference frequency and outputs it from pin 15.
The output signal is passed through the loop filter(Q2) and
is then applied to the TX and RX-VCO circuits as lock voltage.
The lock voltage is also used for the receiver tunable bandpass filters to match the filter’s center frequency to the
desired receive frequency. The lock voltage is passed
through the loop filter (Q2), and then applied to the DC
amplifier (Q10). The amplified signal is applied to the CPU
(LOGIC unit; IC7, pin 98) via the “LVIN” signal. The signal is
analyzed at the CPU, and then applied to bandpass filters
(D9–D11, D13) as “T1”, “T2”, “T3” signals via the D/A converter.
4-3-2 VCO CIRCUIT (MAIN UNIT)
The VCO circuit contains a separate TX-VCO (Q6, D2, D4)
and RX-VCO (Q7, D5). The oscillated signal is amplified at
the LO (Q9) and buffer (Q11) amplifiers, and is then Tx/Rx
switching circuit (D6, D7). Then Tx and Rx signals are
applied to the pre-driver (Q17) and 1st mixer circuit (Q19)
respectively.
A portion of the signal from LO amplifier (Q9) is amplified at
the buffer amplifier (Q12) and is then fed back to the PLL IC
(IC1, pin 6) as the comparison signal.
Shift register
Prescaler
Phase
detector
Loop
filter
Programable
divider
Reference
divider
X1
25.25 MHz
Q6,
D2,
D4
TX VCO
RX VCO
LO
D7
D6
Q12
Q9
Q2
2
3
4
PLLCK
IC1 (PLL IC)
PLLDATA
PLLSTB
to transmitter circuit
to 1st mixer circuit (Q19)
1
9
6
Q7,
D5
Buff.
Q11
TX/RX
switch
Buff.
25.25 MHz 2nd LO signal
to the 2nd IF IC (IC4, pin 2)
• PLL CIRCUIT
LINE
HV
SWHV
C5V
+8V
+5V
T8
R5V
DESCRIPTION
The voltage from the power supply.
The same voltage as HV line which is controlled
by the HVSW circuit (Q28, Q30, Q31). When the
[POWER] switch is pushed, the CPU outputs the
“PWRON” control signal via the expander IC
(IC2). The signal is applied to the HVSW circuit
to turn the circuit ON.
The output voltage is applied to the drive amplifier (Q18), +8V regulator circuit (IC7), etc.
Common 5 V for the CPU converted from the HV
line by the C5V regulator circuit (IC8). The circuit
outputs the voltage regardless of the power
ON/OFF condition.
The output voltage is applied to the EEPROM
(LOGIC UNIT; IC5), CPU (LOGIC UNIT; IC7),
etc.
Common 8 V converted from the 13.8 V line by
the +8V regulator circuit (IC7).
The output voltage is applied to the LO (Q9) and
buffer (Q11) amplifiers, etc.
Common 5 V converted from the +8 V line by the
+5V regulator circuit (Q21, Q22).
Transmit 8 V controlled by the T8V regulator circuit (Q14, Q15) using the “TXC” signal from the
I/O expander IC (IC2).
Receive 5 V controlled by the R5V regulator circuit (Q25) using “RXC” signal from the I/O
expander IC (IC2).
The output voltage is applied to the FM IC IC
(IC4), IF (Q16) and RF (Q27) amplifiers, etc.
4-4 POWER SUPPLY CIRCUITS
VOLTAGE LINE
4 - 4
Pin Port
Description
number name
Pin Port
Description
number name
4-5 PORT ALLOCATIONS
4-5-1 CPU (LOGIC UNIT: IC7)
1
9
11
12
14
15
16
17
19
20
21
22
23
26
32–35
36–39
40
41
44
45
47
49–51
53
DETO
RESET
CSHIFT
SCK
SO
PTT
CLIN
CLOUT
NOIS
COLOR
DIM1
DIM0
REMO
UNLK
COM4–
COM1
KR3–
KR0
EXTMIC
OPV2
PLLSTB
PLLCK
EXSTB
OPV3
OPT1–
OPT3
DUSE
Input port for the weather alert signal
detection.
Input port for reset signal.
Outputs reference oscillator for the
CPU control signal.
Outputs serial clock signal to the
expander IC (MAIN unit; IC2, pin 3),
D/A convertor IC (MAIN unit, IC5, pin
7), etc.
Outputs serial signals to the D/A con-
vertor IC (MAIN unit; IC5, pin 8),etc.
Input port for the [PTT] switch.
High : While [PTT] switch is pushed.
Input port for the cloning signal.
Outputs the cloning signal.
Input port for noise signals (pulse
type).
Outputs LCD back light color control
signal.
Low : While choosing umber color.
Outputs LCD contrast control signal.
Input port for the remote signals from
a remote microphone (HM-133V) via
the [MIC] jack.
Input port for PLL unlock signal from
the PLL IC (MAIN unit; IC1, pin 14).
Outputs LCD common signals.
Input port for initial matrix.
Low : While keys are pushing.
Input port for the remote control micro-
phone (HM-133V) connecting detection.
Low : While HM-133V is connected.
Input port for the optional unit detec-
tion signal.
Outputs strobe signals to the PLL IC
(IC1, pin 4).
Outputs PLL IC (IC1, pin 2) clock sig-
nal.
• Outputs strobe signal to the
expander IC (IC2, pin 1).
• Input port for the optional unit detec-
tion signal.
I/O port for optional unit control signal.
Outputs low-pass filter cut-off frequen-
cy control signal when DTCS is activated.
54
55
56–88
90
91
95
96
97
98
99
100
Outputs EEPROM (LOGIC unit; IC5,
pin 6) clock signal.
I/O port for the data signals from/to the
EEPROM (LOGIC unit; IC5, pin 5).
Output LCD driver signals.
Outputs CTCSS and DTCS tone sig-
nal.
Outputs DTMF, BEEP and 1750 Hz
tone signal.
Input port for the squelch level detec-
tion.
Input port for the microphone up/down
signal while connecting the microphone.
Input port for the RSSI detection.
Input port for the PLL lock voltage.
Input port for the power detector volt-
age.
Input port for the transceiver’s internal
tempareture detection.
ESCK
ESDA
SEG1–
SEG32
CTCC
TONE
SQLV
MICUD
SD
LVIN
PDET
TEMP
4 - 5
Pin Port
Description
number name
2
3
10
11, 23
14
15
22
MOD
SQLATT
T1
T2, T3
SQLIN
DTC
FC
Outputs transmit devetion control signal.
Outputs attenuator control signal.
• Outputs tunable bandpass filter con-
trol signal while receiving.
• Outputs TX power control signal
while transmitting.
Output tunable bandpass filter control
signals.
Outputs squelch control signal.
Outputs DTCS’s gradient control sig-
nal.
Outputs reference frequency control
signal to X1.
4-5-2 D/A CONVERTOR IC (MAIN UNIT: IC5)
Pin Port
Description
number name
4
7
12
6
11
13
14
FANC1
FANC
FANC2
AFMUTE
SHIFT
RXC
TXC
Outputs cooling fan control signal.
The fan speed is depended as shown
below.
Outputs AF mute circuit control signal.
High : While AF mute is ON.
Outputs TX and RX VCO’s regulator
control signals.
High : While receiving.
Low : While transmitting.
Outputs R5 regulator control signal.
Low : While receiving.
Outputs TX power control signal.
High : While transmitting.
4-5-3 I/O EXPANDER IC (MAIN UNIT: IC2)
Fan speed
Hi
Middle
Low
FANC
H
H
H
FANC1
H
L
H
FANC2
H
H
L
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