Pioneer CX-3166 Service manual

Model Service Manual CD Mechanism Module DEH-1850/XN/ES CRT3552 CXK5701

CXK5701DEH-1800R/XN/EW

DEH-1820R/XN/EW

CRT3553

This service manual describes the operation of the CD mechanism module incorporated in models listed in the table below. When performing repairs use this manual together with the specific manual for model under repair.

ORDER NO.

CRT3582

CD MECHANISM MODULE(S10.5STD)

CX-3166

PIONEER CORPORATION 4-1, Meguro 1-chome, Meguro-ku, Tokyo 153-8654, Japan

PIONEER ELECTRONICS (USA) INC. P.O. Box 1760, Long Beach, CA 90801-1760, U.S.A. PIONEER EUROPE NV Haven 1087, Keetberglaan 1, 9120 Melsele, Belgium PIONEER ELECTRONICS ASIACENTRE PTE. LTD. 253 Alexandra Road, #04-01, Singapore 159936

PIONEER CORPORATION 2005

K-ZZA. OCT. 2005 Printed in Japan

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1. CIRCUIT DESCRIPTIONS ............................................................................................................................... 3

2. MECHANISM DESCRIPTIONS...................................................................................................................... 20

3. DISASSEMBLY...............................................................................................................................................22

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1. CIRCUIT DESCRIPTIONS

The recent mainstay of the CD LSI is the LSI integrating the core DSP with DAC or RF amplifier, which are generally employed as peripheral circuits, however, PE5497B, used in this product, is an LSI integrating the afore-mentioned LSI unit and microcomputer unit in one chip.

A-F Signal

RF-Amp

Converter

PWM

Output

Digital

Servo

CPU Interface

CPU

CPU for System Control

A/D

PE5497B

Data

Processor

Sub-Q,

CD-TEXT

RAM

1-bit Audio

DAC

Post

filter

(SCF)

Analog Output

Fig.1.0.1 Block diagram of PE5497B

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1.1 PREAMPLIFIER BLOCK (PE5497B: IC201)

In the preamplifier block, the pickup output signals are processed to generate signals that are used in the subsequent

blocks: servo, demodulator, and control blocks. Signals from the pickup are I/V converted in the pickup with the preamplifier with built-in photo detectors, and after added with the RF amplifier, they are used to produce such signals as RF, FE, TE, and TE zero-cross signals. The preamplifier block is built in CD LSI PE5497B (IC201), whose parts are described individually below. Incidentally, as this LSI employs a single power supply (+ 3.3 V) specification, the reference voltages of this LSI and the pickup are the REFO (1.65 V) for both. The REFO is an output obtained from REFOUT in the LSI via the buffer amplifier, and is output from the pin 93 of this LSI. All measurements will be performed with this REFO as the reference. Caution: Be careful not to short-circuit the REFO and GND when measuring.

1.1.1 APC (Automatic Power Control) circuit

Since laser diodes have extremely negative temperature characteristics in optical output when driven in constant current, it is necessary to control the current with the monitor diodes in order to keep the output constant. This is the feature of the APC circuit. The LD current is obtained by measuring the voltage between LD1 and VDD(+ 3.3 V), and divide the value by

7.5 (ohms), which becomes about 30 mA.

Pickup Unit

CD CORE UNIT

LD-

LD+

14 14

VDD(+ 3.3 V)

2R4× 2

2R7

100/16

2SA1577

PE5497B

REG 1.25V

LDS

110k

6.5k

Vref

APN

100k

6.5k

Fig.1.1.1 APC

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1.1.2 RF and RFAGC amplifiers

The output from the photo-detector (A + C) and (B + D) is provided from the RFO terminal as the RF signal (which can be used for eye-pattern check), after it is added, amplified, and equalized inside this LSI. The low frequency component of the voltage RFO is calculated as below. RFO = (A + B + C + D) x 2 The RFO is used for the FOK generation circuit and RF offset adjustment circuit. The RFO signal, output from the pin 82, is A/C-coupled externally, input to the pin 81, and amplified in the RFAGC amplifier to obtain the RFAGC signal. Also, this LSI is equipped with the RFAGC auto-adjustment function, explained below, which switches feedback gains of the RFAGC amplifier so that the RFO output will be 1.5 V. This RFO signal is also used for the EFM, DFCT, MIRR, and RFAGC auto-adjustment circuits.

CD CORE UNIT

Pickup Unit

VREF

A+C

B+C

PE5497B

15.2k

RFOFF setup

VREF

10k 8.8k

61.0k

RFO

35k 20k 11.2k

111k

AGCI

FEOFF setup

VREF

7.05k

To DEFECT/A3T detection

For RFOK generation

10k 10k

RF-

RF2-

EQ2

EQ1

AGCO

FEO

FE A/D

FE-

1.2k

22p

56p

4.7k

5.6k

Fig.1.1.2 RF/AGC/FE

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1.1.3 Focus error amplifier

The photo-detector outputs (A + C) and (B + D) are passed through the differential amplifier and the error amplifier, and (A + C - B - D) is provided from the pin 95 as the FE signal.The low frequency component of the voltage FE is calculated as

below. FE = (A + C - B - D) x 8.8k / 10k x 111k / 61k x 160k / 72k

= (A + C - B - D) x 3.5

For the FE outputs, an S-shaped curve of 1.5 Vp-p is obtained with the REFO as the reference. The cutoff frequency for the subsequent stage amplifiers is 14.6 kHz.

1.1.4 RFOK circuit

This circuit generates the RFOK signal, which indicates the timing to close the focus loop and focus-close status during

the play mode, from the pin 62. As for the signal, "H" is output in closing the focus loop and during the play mode. Additionally, the RFOK becomes "H" even in a non-pit area, since the DC level of the RFO signal is peak-held in the subsequent digital block and compared at a certain threshold level to generate the RFOK signal. Therefore, the focus is closed even on a mirror-surface area of a disc. This signal is also supplied to the microcomputer via the low-pass filer as the FOK signal, which is used for protection and gain switching of the RF amplifier.

1.1.5 Tracking error amplifier

The photo-detector outputs E and F are passed through the differential amplifier and the error amplifier to obtain (E - F), and then provided from the pin 98 as the TE signal. The low frequency component of the voltage TE is calculated as below.

TEO = (E - F) x 63k / 112k x 160k / 160k x 181k / 45.4k x 160k / 80k

= (E - F) x 4.48 For the TE output, TE waveform of about 1.3 Vp-p with the REFO as the reference. The cutoff frequency in the subsequent is 21.1 kHz.

Pickup Unit

P10

Fig.1.1.3 TE

CD CORE UNIT

VREF

PE5497B

TE A/D

VREF

60k20k

Inside TEC

TEOFF setup

112k

63k

160k 160k

63k

45.36k

80k 160k

161k

TEO

47p

TE-

TE2

10000p

TEC

100

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1.1.6 Tracking zero-cross amplifier

The tracking zero-cross signal (hereinafter referred to as TEC signal) is obtained by amplifying the TE signal by fourfold, and used to detect the tracking-error zero-cross point. As the purpose of detecting the zero-cross point, the following two points can be named:

1. To use for track-counting in the carriage move and track jump modes

2. To use for detecting the direction in which the lens moves in tracking close. (Used in the tracking brake circuit to be explained later.) The frequency range of the TEC signal is from 300 Hz to 20 kHz, and TEC voltage = TE level x 4 The TEC level can be calculated at 4.62V, which, at this level, exceeds the D range of the operational amplifier, and clips the signal, but, because the CD LSI only uses the signal at the zero-cross point, it poses no particular problem.

1.1.7 EFM circuit

The EFM circuit converts the RF signal into digital signals of 0 and 1. The AGCO signal output from the pin 79 is A/Ccoupled externally, input to the pin 78, and supplied to the EFM circuit. Missing RF signal due to scratches and stains on the disc, and asymmetry of the upper and lower parts of the RF, caused by variation in disc production, cannot be entirely eliminated in AC coupling process, the reference voltage ASY of the EFM comparator is controlled, using the probability that 0 and 1 occur at 50%. Thus, the comparator level will always stay around the center of the RFO signal. This reference voltage ASY is generated by passing the EFM comparator output through the low-pass filter. The EFM signal is output from the pin 73.

Vdd

ASY

EFM

RFI

PE5497B

EFM signal

Vdd

40k

1.5k 7.5k

Fig.1.1.4 EFM

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1.2 SERVO BLOCK (PE5497B: IC201)

The servo block performs servo control such as error signal equalizing, in-focus, track jump and carriage move. The DSP

block is the signal-processing unit, where data decoding, error correction, and compensation are performed. The FE and TE signals, generated in the preamplifier stage, are A/D-converted, and output drive signals for the focus, tracking, and carriage systems via the servo block. Also, the EFM signal is decoded in the signal-processing unit, and ends up in outputting D/A-converted audio signals through the D/A converter. Furthermore, in this decoding process, the spindle servo error signal is generated, supplied to the spindle servo block, and used to output the spindle drive signal. Each drive signal for focus, tracking, carriage, and spindle servos (FD, TD, SD, and MD) are output as PWM3 data, and then converted to analog data through the LPF. These drive signals, after changed to analog form, can be monitored with the FIN, TIN, CIN, and SIN signals, respectively. Subsequently, the signals are amplified and supplied to the actuator and motor for each signal.

1.2.1 Focus servo system

The main equalizer of the focus servo consists of the digital equalizer block. The figure 1.2.1 shows the block diagram of the focus servo system. In the focus servo system, it is necessary to move the lens within the in-focus range in order to close the focus loop. For that purpose, the in-focus point is looked for by moving the lens up and down with the focus search voltage of triangular signal. During this time, the rotation of the spindle motor is retained at a certain set speed by kicking the spindle motor. The servo LSI monitors the FE and RFOK signals and automatically performs the focus-close operations at an appropriate timing. The focus-close operation is performed when the following three conditions are satisfied at the same time:

1) The lens moves toward the disc surface.

2) RFOK = "H"

3) The FE signal is zero-crossed. Consequently, the FE converges to "0" (= REFO). When the above-mentioned conditions are met and the focus loop is closed, the FSS bit is shifted from "H" to "L," and then, in 10 ms, the CPU unit of the LSI starts monitoring the RFOK signal obtained through the low-pass filter. If the RFOK signal is determined to be "L," the CPU unit of the LSI takes several actions including protection. Fig.1.2.2 shows a series of actions concerning the focus close operations. (It shows a case where the focus loop cannot be closed.)

With the focus mode selector displaying 01 in the test mode, pressing the focus close button, allows to check the Sshaped curve, search voltage, and actual lens behavior.

IC201 PE5497B

A + C

B + D

AMP

FOCUS SEARCH

TRIANGULAR

WAVE GENERATOR

Fig.1.2.1 Block diagram of the focus servo system

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A/D

DIG.

CONTROL

CX-3166

PWM

IC301 BA5839FP

FOP

FOM

LENS

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Search start

Output from FD terminal

A blind period

FE controlling signals

You can ignore this for blind periods.

FSS bit of SRVSTS1 resistor

RFOK signals

The broken line in the figure is assumed in the case without focus servo.

The status of focus close is judged from the statuses of FSS and RFOK after about 10 mS.

Fig.1.2.2 Timing chart for focus close operations

1.2.2 Tracking servo system

The main equalizer of the tracking servo consists of the digital equalizer block. The figure 1.2.3 shows the block diagram of the focus servo system.

IC201 PE5497B

AMP

A/D

DIG.

JUMP

PARAMETERS

Fig.1.2.3 Block diagram of the tracking servo system

CONTROL

PWM

IC301 BA5839FP

TOP

TOM

LENS

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+ 18 hidden pages

Pioneer CX-3166 Service manual

CONTENTS

1. CIRCUIT DESCRIPTIONS