Philips UDA1360TS-N1 Datasheet

DATA SH EET

Preliminary speciﬁcation Supersedes data of 1998 Oct 02 File under Integrated Circuits, IC01

2000 Feb 08

INTEGRATED CIRCUITS

UDA1360TS

Low-voltage low-power stereo audio ADC

2000 Feb 08 2

Philips Semiconductors Preliminary speciﬁcation

Low-voltage low-power stereo audio ADC UDA1360TS

FEATURES General

• Low power consumption

• 2.4 to 3.6 V power supply

• Supports 256 and 384fs system clock

• Supports sampling frequency range of 5 to 55 kHz

• Small package size (SSOP16)

• Integrated high-pass filter to cancel DC offset

• Power-down mode

• Supports 2 V (RMS) input signals

• Easy application

• Non-inverting ADC plus decimation filter.

Multiple format output interface

• I2S-bus and MSB-justified format compatible

• Up to 20 significant bits serial output.

Advanced audio conﬁguration

• Stereo single-ended input configuration

• High linearity, dynamic range and low distortion.

GENERAL DESCRIPTION

The UDA1360TS is a single chip stereo Analog-to-Digital Converter (ADC) employing bitstream conversion techniques. The low power consumption and low voltage requirements make the device eminently suitable for use in low-voltage low-powerportable digital audio equipment which incorporates recording functions.

TheUDA1360TSsupportstheI2S-busdataformatandthe MSB-justified data format with word lengths of up to 20 bits.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

DDA

analog supply voltage 2.4 3.0 3.6 V

DDD

digital supply voltage 2.4 3.0 3.6 V

DDA

analog supply current − 9 − mA

DDD

digital supply current − 3.5 − mA

amb

operating ambient temperature −40 − +85 °C

ADC

i(rms)

input voltage (RMS value) see Table 1 − 1.0 − V

(THD + N)/S total harmonic distortion plus

noise-to-signal ratio

at 0 dB −−85 −80 dB at −60 dB; A-weighted −−37 −33 dB

S/N signal-to-noise ratio V

= 0 V; A-weighted − 97 − dB

channel separation − 100 − dB

TYPE

NUMBER

PACKAGE

NAME DESCRIPTION VERSION

UDA1360TS SSOP16 plastic shrink small outline package; 16 leads; body width 4.4 mm SOT369-1

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Philips Semiconductors Preliminary speciﬁcation

Low-voltage low-power stereo audio ADC UDA1360TS

BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

MGM967

ADC

(Σ∆)

DECIMATION

FILTER

CLOCK

CONTROL

DC-CANCELLATION

FILTER

DIGITAL

INTERFACE

ADC

(Σ∆)

15 5 4 2

11 12

UDA1360TS

VINL

ref

VINR

ref(n)

ref(p)

SFOR

PWON

SYSCLK

DDD

SSD

BCK

DATAO

FSEL

SSA

DDA

2000 Feb 08 4

Philips Semiconductors Preliminary speciﬁcation

Low-voltage low-power stereo audio ADC UDA1360TS

PINNING

SYMBOL PIN DESCRIPTION

VINL 1 left channel input V

ref

2 reference voltage VINR 3 right channel input V

ref(n)

4 ADC negative reference voltage V

ref(p)

5 ADC positive reference voltage SFOR 6 data format selection input PWON 7 power control input SYSCLK 8 system clock input 256 or 384f

DDD

9 digital supply voltage V

SSD

10 digital ground BCK 11 bit clock input WS 12 word selection input DATAO 13 data output FSEL 14 system clock frequency select V

SSA

15 analog ground V

DDA

16 analog supply voltage

Fig.2 Pin configuration.

handbook, halfpage

UDA1360TS

MGM968

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10

VINL

ref

VINR

ref(n)

ref(p)

SFOR

PWON

SYSCLK

DDD

SSD

BCK

DATAO

FSEL

SSA

DDA

FUNCTIONAL DESCRIPTION System clock

The UDA1360TS accommodates slave mode only, this means that in all applications the system devices must provide the system clock. The system frequency is selectable via the static FSEL pin, and the system clock must be locked in frequency to the digital interface input signals.

The options are 256fs (FSEL = LOW) and 384f

(FSEL = HIGH). The sampling frequency range is 5 to 55 kHz.

The BCK clock can be up to 128fs, or in other words the BCK frequency is 128 times the Word Select (WS) frequency or less: f

BCK

≤ 128 × fWS.

Notes:

1. The WS edge MUST fall on the negative edge of the BCK at all times for proper operation of the digital I/O data interface.

2. For MSB justified formats it is important to have a WS signal with 50% duty factor.

Analog-to-Digital Converter (ADC)

The stereo ADC of the UDA1360TS consists of two 3rd-order Sigma-Delta modulators. They have a modified

Ritchie-coder architecture in a differential switched capacitor implementation. The over-sampling ratio is 128.

Input level

The overall system gain is proportional to V

DDA

. The 0 dB inputlevel is defined as that which gives a −1 dB FS digital output(relativetothefull-scaleswing).Inaddition,an input gain switch is incorporated with the above definitions.

The UDA1360TS front-end is equipped with a selectable 0 or 6 dB gain, in order to supports 2 V (RMS) input using a series resistor of 12 kΩ.

For the definition of the pin settings for 1 or 2 V (RMS) mode given in Table 1, it is assumed that this resistor is present as a default component.

If the 2 V (RMS) signal input is not needed, the external resistor should not be used.

2000 Feb 08 5

Philips Semiconductors Preliminary speciﬁcation

Low-voltage low-power stereo audio ADC UDA1360TS

Table 1 Application modes using input gain stage

Multiple format output interface

The UDA1360TS supports the following data output formats;

• I2S-bus with data word length of up to 20 bits

• MSB-justifiedserial format with data word length of up to

20 bits.

Theoutput format can be set bythestatic SFOR pin. When SFOR is LOW, the I2S-bus is selected, when SFOR is set HIGH the MSB-justified format is selected.

Thedataformatsare illustrated in Fig.4. Left and right data channel words are time multiplexed.

Decimation ﬁlter

The decimation from 128fs is performed in two stages. The first stage realizes 3rd-order sin x/x characteristic. This filter decreases the sample rate by 16. The second stage (an FIR filter) consists of 3 half-band filters, each decimating by a factor of 2.

Table 2 DC cancellation ﬁlter characteristics

Mute

On recovery from power-down, the serial data output DATAO is held LOW until valid data is available from the decimation filter. This time tracks with the sampling frequency:

; where f

= 44.1 kHz.

Power-down mode

The PWON pin can control the power saving together with the optional gain switch for 2 V (RMS) or 1 V (RMS) input. When the PWON pin is set LOW, the ADC is set to power-down. When PWON is set to HIGH or to half the power supply, then either 6 dB gain or 0 dB gain in the analog front-end is selected.

Application modes

The UDA1360TS can be set to different modes using two 3-level pins and one 2-level pin. The selection of modes is given in Table 3.

Table 3 Mode selection summary

RESISTOR

(12 kΩ)

INPUT GAIN

SWITCH

MAXIMUM INPUT

VOLTAGE

Present 0 dB 2 V (RMS) Present 6 dB 1 V (RMS)

Absent 0 dB 1 V (RMS) Absent 6 dB 0.5 V (RMS)

ITEM CONDITION

VALUE

(dB)

Pass-band ripple none Pass-band gain 0 Stop band >0.55f

−60

Droop at 0.00045f

0.031

Attenuation at DC at 0.00000036f

>40

Dynamic range 0 to 0.45f

>110

PIN V

⁄2V

SFOR I2S-bus test mode MSB PWON power-down 0 dB gain 6 dB gain FSEL 256f

− 384f

12288

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279 ms==

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