Philips UDA1352HL Technical data

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UDA1352HL

48 kHz IEC 60958 audio DAC

Preliminary speciﬁcation Supersedes data of 2002 May 22

2003 Mar 25

Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352HL

CONTENTS

1 FEATURES

1.1 General

1.2 Control

1.3 IEC 60958 input

1.4 Digital sound processing and DAC 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 ORDERING INFORMATION 5 QUICK REFERENCE DATA 6 BLOCK DIAGRAM 7 PINNING 8 FUNCTIONAL DESCRIPTION

8.1 Operating modes

8.2 Clock regeneration and lock detection

8.3 Crystal oscillator

8.4 Mute

8.5 Auto mute

8.6 Data path

8.7 Control 9 L3-BUS DESCRIPTION

9.1 General

9.2 Device addressing

9.3 Register addressing

9.4 Data write mode

9.5 Data read mode

9.6 Initialization string 10 I2C-BUS DESCRIPTION

10.1 Characteristics of the I2C-bus

10.2 Bit transfer

10.3 Byte transfer

10.4 Data transfer

10.5 Start and stop conditions

10.6 Acknowledgment

10.7 Device address

10.8 Register address

10.9 Write and read data

10.10 Write cycle

10.11 Read cycle 11 SPDIF SIGNAL FORMAT

11.1 SPDIF channel encoding

11.2 SPDIF hierarchical layers for audio data

11.3 SPDIF hierarchical layers for digital data

11.4 Timing characteristics

12 REGISTER MAPPING

12.1 Clock settings (write)

12.2 I2S-bus output settings (write)

12.3 I2S-bus input settings (write)

12.4 Power-down settings (write)

12.5 Volume control left and right (write)

12.6 Sound feature mode, treble and bass boost settings (write)

12.7 De-emphasis and mute (write)

12.8 DAC source and clock settings (write)

12.9 SPDIF input settings (write)

12.10 Supplemental settings (write)

12.11 PLL coarse ratio (write)

12.12 Interpolator status (read-out)

12.13 SPDIF status (read-out)

12.14 Channel status (read-out)

12.15 PLL status (read-out)

13 LIMITING VALUES 14 THERMAL CHARACTERISTICS 15 CHARACTERISTICS 16 TIMING CHARACTERISTICS 17 APPLICATION INFORMATION 18 PACKAGE OUTLINE 19 SOLDERING

19.1 Introduction to soldering surface mount packages

19.2 Reflow soldering

19.3 Wave soldering

19.4 Manual soldering

19.5 Suitability of surface mount IC packages for wave and reflow soldering methods

20 DATA SHEET STATUS 21 DEFINITIONS 22 DISCLAIMERS 23 PURCHASE OF PHILIPS I2C COMPONENTS

2003 Mar 25 2

Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352HL

1 FEATURES

1.1 General

• 2.7 to 3.6 V power supply

• Integrated digital filter and Digital-to-Analog

Converter (DAC)

• 256fs system clock output

• 20-bit data path in interpolator

• High performance

• No analog post filtering required for DAC

• Supported sampling frequencies of 28 up to 55 kHz.

1.2 Control

• Controlled by either static pins, I2C-bus or L3-bus microcontroller interfaces.

• Bass boost and treble control in L3-bus or I2C-bus modes

• Interpolating filter (fsto 64fs or 128fs) using cascaded recursive and FIR filters

• Fifth-order noise shaper (operating either at 64f or 128fs) generates the bitstream for the DAC

• Filter Stream DAC (FSDAC).

1.3 IEC 60958 input

• On-chip amplifier converts IEC 60958 input to CMOS levels

• Lock status indication at pin LOCK

• Pulse Code Modulation (PCM) input signal status

indication at pin PCMDET

• Right and left channels each have 40 key channel-status bits available via L3-bus or I2C-bus interfaces.

1.4 Digital sound processing and DAC

• Automatic de-emphasis when using IEC 60958 input with audio sample frequencies (fs) of 32.0, 44.1 and

48.0 kHz

• Soft mute using a cosine roll-off circuit selectable via pin MUTE, L3-bus or I2C-bus interfaces

• Left and right independent dB linear volume control having 0.25 dB steps from 0 to −50 dB, 1 dB steps to

−60, −66 and −∞ dB

4 ORDERING INFORMATION

TYPE

NUMBER

UDA1352HL LQFP48 plastic low proﬁle quad ﬂat package; 48 leads; body 7 × 7 × 1.4 mm SOT313-2

NAME DESCRIPTION VERSION

2 APPLICATIONS

• Digital audio systems.

3 GENERAL DESCRIPTION

The UDA1352HL is a single-chip IEC 60958 audio decoder with an integrated stereo DAC employing bitstream conversion techniques.

A lock status signal is available on pin LOCK, to indicate when the IEC 60958 decoder is locked. A PCM detection status signalis available on pin PCMDET to indicate when PCM data is present at the input.

By default, the DAC output and the data output interface are muted when the decoder is out-of-lock. However, this setting can be overridden in the L3-bus or I2C-bus modes.

The UDA1352HL in package LQFP48 is the full featured version. Also available is the UDA1352TS in package SSOP28 which has the IEC 60958 input only to the DAC.

PACKAGE

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Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352HL

5 QUICK REFERENCE DATA

DDD=VDDA

ground; unless otherwise speciﬁed.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

DDD

DDA

DDA(DAC)

DDA(PLL)

DDD(C)

DDD

General

rst

amb

Digital-to-analog converter

o(rms)

∆V

(THD+N)/S total harmonic

S/N

= 3.0 V; IEC 60958 input with fs= 48 kHz; T

=25°C; RL=5kΩ; all voltages measured with respect to

amb

digital supply voltage 2.7 3.0 3.6 V analog supply voltage 2.7 3.0 3.6 V analog supply current of DAC power-on − 3.3 − mA

power-down; clock off − 35 −µA analog supply current of PLL at fs= 48 kHz − 0.5 − mA digital supply current of core at fs= 48 kHz − 9 − mA digital supply current at fs= 48 kHz − 0.6 − mA power consumption at

fs=48kHz

DAC in Playback mode − 40 − mW

DAC in Power-down mode − tbf − mW

reset active time − 250 −µs ambient temperature −40 − +85 °C

output voltage (RMS value) fi= 1.0 kHz tone at 0 dBFS; note 1 850 900 950 mV unbalance of output voltages fi= 1.0 kHz tone − 0.1 0.4 dB

= 1.0 kHz tone at fs=48kHz

distortion-plus-noise to signal ratio

signal-to-noise ratio at

at 0 dBFS −−82 −77 dB at −40 dBFS; A-weighted −−60 −52 dB

fi= 1.0 kHz tone; code = 0; A-weighted 95 100 − dB fs=48kHz

channel separation fi= 1.0 kHz tone − 110 − dB

Note

1. The output voltage of the DAC is proportional to the DAC power supply voltage.

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Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352HL

6 BLOCK DIAGRAM

handbook, full pagewidth

DDA(PLL)

SSA(PLL)

DDD(C)

SSD(C)

DA0 DA1

L3MODE

L3CLOCK

L3DATA

SELSTATIC

SELIIC

SPDIF0 SPDIF1

SELCHAN

DDD

SSD

35 34

42 37

10 6 5

38 47

16 17

14 46

TIMING CIRCUIT

OR I INTERFACE

SLICER

11, 29, 30, 41, 48

n.c.

XTALOUT

CLKOUTXTALIN

1215

CLOCK

AND

L3-BUS

C-BUS

PCMDET

OSCOUT

IEC 60958

DECODER

LOCK

PREEM1

TEST

NON-PCM DATA

SYNC

DETECTOR

45 31

PREEM0

USERBIT

SSA(DACO)

UDA1352HL

DATA

OUTPUT

INTERFACE

BCKO

WSO

DDA(DACA)

DDA(DACO)

DATAO

DATAI

VOUTL

DAC

AUDIO FEATURE PROCESSOR

BCKI

WSI

SSA(DACA)

NOISE SHAPER

INTERPOLATOR

SELCLK

SELSPDIF

ref

DATA

INPUT

INTERFACE

VOUTR

DAC

MGU597

MUTE

RESET

Fig.1 Block diagram.

2003 Mar 25 5

Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352HL

7 PINNING

SYMBOL PIN TYPE

(1)

DESCRIPTION

RESET 1 DID reset input V

DDD(C)

SSD

SSD(C)

L3DATA 5 IIC L3-bus or I L3CLOCK 6 DIS L3-bus or I DATAI 7 DISD I BCKI 8 DISD I WSI 9 DISD I

2 DS digital supply voltage for core 3 DGND digital ground 4 DGND digital ground for core

C-bus interface data input and output

C-bus interface clock input

S-bus data input

S-bus bit clock input

S-bus word select input L3MODE 10 DIS L3-bus interface mode input n.c. 11 − not connected XTALOUT 12 AIO crystal oscillator output MUTE 13 DID mute control input SELCHAN 14 DID IEC 60958 channel selection input XTALIN 15 AIO crystal oscillator input SPDIF0 16 AIO IEC 60958 channel 0 input SPDIF1 17 AIO IEC 60958 channel 1 input V

DDA(DACA)

DDA(DACO)

18 AS analog supply voltage for DAC

19 AS analog supply voltage for DAC VOUTL 20 AIO DAC left channel analog output SELCLK 21 DID clock source for PLL selection input SELSPDIF 22 DIU IEC 60958 data selection input LOCK 23 DO SPDIF and PLL lock indicator output VOUTR 24 AIO DAC right channel analog output TEST 25 DID test pin; must be connected to digital ground (V V

ref

SSA(DACA)

SSA(DACO)

26 AIO DAC reference voltage

27 AGND analog ground for DAC

28 AGND analog ground for DAC n.c. 29 − not connected n.c. 30 − not connected USERBIT 31 DO user data bit output CLKOUT 32 DO clock output (256f

)

PREEM1 33 DO IEC 60958 input pre-emphasis output 1 V

SSA(PLL)

DDA(PLL)

BCKO 36 DO I

34 AGND analog ground for PLL

35 AS analog supply voltage for PLL

S-bus bit clock output DA1 37 DISU A1 device address selection input SELSTATIC 38 DIU static pin control selection input DATAO 39 DO I WSO 40 DO I

S-bus data output

S-bus word select output

) in application

SSD

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Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352HL

SYMBOL PIN TYPE

(1)

DESCRIPTION

n.c. 41 − not connected DA0 42 DISD A0 device address selection input PCMDET 43 DO PCM detection indicator output OSCOUT 44 DO internal oscillator output PREEM0 45 DO IEC 60958 input pre-emphasis output 0 V

DDD

SELIIC 47 DID I

46 DS digital supply voltage

C-bus or L3-bus mode selection input n.c. 48 − not connected

Note

1. See Table 1.

Table 1 Pin types

TYPE DESCRIPTION

DS digital supply DGND digital ground AS analog supply AGND analog ground DI digital input DIS digital Schmitt-triggered input DID digital input with internal pull-down resistor DISD digital Schmitt-triggered input with internal pull-down resistor DIU digital input with internal pull-up resistor DISU digital Schmitt-triggered input with internal pull-up resistor DO digital output DIO digital input and output DIOS digital Schmitt-triggered input and output IIC input and open-drain output for I

C-bus

AIO analog input or output

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Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352HL

handbook, full pagewidth

RESET

DDD(C)

SSD

SSD(C)

L3DATA

L3CLOCK

DATAI

BCKI

WSI

L3MODE

n.c.

XTALOUT

n.c. 48

1 2 3 4 5 6 7 8

9 10 11 12

MUTE

DDD

SELIIC

XTALIN

SELCHAN

PREEM0

OSCOUT

UDA1352HL

SPDIF0

SPDIF1

PCMDET

DA0

DDA(DACA)

DDA(DACO)

n.c. 41

VOUTL

WSO

DATAO

SELCLK

SELSPDIF

SELSTATIC

DA1

LOCK

VOUTR

36 35 34 33 32 31 30 29 28 27 26 25

MGU596

BCKO V

DDA(PLL)

SSA(PLL)

PREEM1 CLKOUT USERBIT n.c. n.c. V

SSA(DACO)

SSA(DACA)

ref

TEST

Fig.2 Pin configuration.

2003 Mar 25 8

Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352HL

8 FUNCTIONAL DESCRIPTION

8.1 Operating modes

The UDA1352HL is a low-cost multi-purpose IEC 60958 decoder DAC with a variety of operating modes.

In operating modes 1, 2, 3, 4, 6, 7 and 8,the UDA1352HL is the master clock generator for both the outgoing and

providing data for the UDA1352HL via the data input interface in mode 4 will be a slave to the clock generated by the UDA1352HL.

In mode 5 the UDA1352HL locks to signal WSI from the digital data input interface. To conform to IEC 60958, the audiosample frequencyofthe datainput interface mustbe between 28 and 55 kHz.

incoming digital data streams. Consequently, any device

Table 2 Mode survey

MODE FUNCTION SCHEMATIC

1 IEC 60958 input

DAC output

SPDIF IN DAC

The system locks onto the SPDIF signal.

PLL

I2S-BUS

OUTPUT

EXTERNAL DSP

S-BUS

INPUT

XTAL

MGU598

2 IEC 60958 input

S-bus digital interface output The system locks onto the SPDIF signal Digital output with BCKO and WSO as

master.

SPDIF IN DAC

PLL

I2S-BUS

OUTPUT

EXTERNAL DSP

S-BUS

INPUT

XTAL

MGU599

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Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352HL

MODE FUNCTION SCHEMATIC

3 IEC 60958 input

I2S-bus digital interface output DAC output The system locks onto the SPDIF signal Digital output with BCKO and WSO as

master.

4 IEC 60958 input

I2S-bus digital interface output I2S-bus digital interface input DAC output The system locks onto the SPDIF signal Digital output with BCKO and WSO as master Digital input with BCKI and WSI as slave

(must be synchronized with the PLL output clock).

SPDIF IN DAC

PLL XTAL

I2S-BUS OUTPUT

EXTERNAL DSP

SPDIF IN DAC

PLL

I2S-BUS

OUTPUT

EXTERNAL DSP

S-BUS

INPUT

S-BUS

INPUT

MGU600

XTAL

MGU601

5I2S-bus digital interface input

DAC output The system locks onto the WSI signal Digital input with BCKI and WSI as slave.

2003 Mar 25 10

SPDIF IN DAC

PLL

I2S-BUS

OUTPUT

EXTERNAL DSP

S-BUS

INPUT

XTAL

MGU602

Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352HL

MODE FUNCTION SCHEMATIC

6I2S-bus digital interface input

DAC output The crystal oscillator generates the system

clock and master clock output Digital input with BCKI and WSI as slave.

7 IEC 60958 input

I2S-bus digital interface output I2S-bus digital interface input DAC output SPDIF input to digital interface output locks

onto the SPDIF signal DAC locks onto the crystal oscillator Digital output with BCKO and WSO as master Digital input with BCKI and WSI as slave

(must be synchronized with the PLL output clock).

8 Crystal oscillator output applied to IEC 60958

input

S-bus digital interface output

SPDIF IN DAC

PLL XTAL

I2S-BUS

OUTPUT

EXTERNAL DSP

SPDIF IN DAC

PLL XTAL

I2S-BUS

OUTPUT

EXTERNAL DSP

SPDIF IN DAC

S-BUS

INPUT

S-BUS

INPUT

MGU603

MGU604

The crystal oscillator generates the master clock

PLL regenerates BCKO and WSO from input clock by setting the pre-scaler ratio

Digital outputwith BCKOand WSO as master (invalid DATA)

Digital input with BCKI and WSI as slave.

2003 Mar 25 11

PLL XTAL

I2S-BUS OUTPUT

S-BUS

INPUT

MGU605

Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352HL

8.2 Clock regeneration and lock detection

The UDA1352HL has an on-board PLL for regenerating a system clock from the IEC 60958 input bitstream.

Remark: If there is no input signal, the PLL generates a minimum frequency and the output spectrum shifts accordingly. Since the analog output does not have an analog mute, this means noise that is out of band under normal conditions can move into the audio band.

When theon-board clocklocks to theincoming frequency, the PLL lock indicator bit is set and can be read via the L3-bus or I2C-bus interfaces.

By default, PLL lock status and PCM detection status indicator signals are internally combined. Pin LOCK goes HIGH when the IEC 60958 decoder and the on-board clock are both locked to the incoming bitstream and if the incoming bitstream data is PCM. However, if the IC is locked but the incoming signal is not PCM data, or it is burst preamble,pin LOCK goes LOW. Thecombined lock andPCM detectionstatuscan beoverriddenby the L3-bus or I2C-bus register bit settings.

Thelock indicationoutputsignal canbe used, forexample, for muting purposes. It can be used to drive an external analog muting circuit to prevent out of band noise from becoming audible when the PLL runs at its minimum frequency (e.g. when there is no SPDIF input signal).

Muting in these modes can only be disabled by setting bit MT in the device register to logic 0.

A logic 1 on pin MUTE will always mute the audio output signal in either the L3-bus or I2C-bus mode, or static pin mode. This is in contrast to the UDA1350 and the UDA1351 in which pin MUTE has no effect in the L3-bus mode.

MGU119

t (ms)

handbook, halfpage

mute

factor

0.8

0.6

0.4

0.2

01051525

When valid PCM data is detected in the incoming bitstream, pin PCMDET goes HIGH.

8.3 Crystal oscillator

The UDA1352HL uses an on-board crystal oscillator to generate a clock signal. The clock signal can be used as the internal clock, and is used directly by the DAC in modes 6 and 7. This clock signal can also be output at pin OSCOUT and can be applied to the SPDIF inputs.

By setting the UDA1352HL as a frequency synthesizer (mode 8), a setof frequencies can be obtained, as shown in Table 53.

8.4 Mute

The UDA1352HL uses a cosine roll-off mute in the DSP data path part of the DAC. Muting the DAC (by pin MUTE or via bit MT in L3-bus or I2C-bus modes), results in a soft mute,as showninFig.3. Thecosineroll-off softmutetakes 23 ms corresponding to 32 × 32 samples at a sampling frequency of 44.1 kHz.

When operating in either the L3-bus or I2C-bus mode, the device will mute the audio output on start-up by default.

Fig.3 Mute as a function of raised cosine roll-off.

2003 Mar 25 12

Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352HL

8.5 Auto mute

By default, the DAC outputs are muted until the UDA1352HL is locked, regardless of the level on pin MUTEor thestate of bit MT.This allowsonly valid data to be passed to the outputs. Thismute is performed in the SPDIF interface and is a hard mute, not a cosine roll-off mute.

The UDA1352HL can be prevented from muting in out-of-lock situations by setting bit MUTEBP in register address 01H to logic 1 via the L3-bus or I2C-bus interfaces.

8.6 Data path

The UDA1352HL data path consists of the IEC 60958 decoder, audio feature processor, digital interpolator, noise shaper and the DACs.

8.6.1 IEC 60958 INPUT The IEC 60958decoder features anon-chip amplifier with

hysteresis, which amplifies the SPDIF input signal to CMOS level (see Fig.4).

All 24 bits of data for left and right channels are extracted from theinput bitstreamplus 40 channel-status bitsfor left and right channels. These bits can be read via the L3-bus or I2C-bus interfaces.

The UDA1352HL supports the following sample frequencies and data rates:

• fs= 32.0 kHz, resulting in a data rate of 2.048 Mbits/s

• fs= 44.1 kHz, resulting in a data rate of 2.8224 Mbits/s

• fs= 48.0 kHz, resulting in a data rate of 3.072 Mbits/s.

The UDA1352HL supports timing levels I, II and III, as specified by theIEC 60958 standard. The accuracy ofthe above sampling frequencies depends on the timing levels used. Timing levels I, II and III are described in Section 11.4.1.

8.6.2 AUDIO FEATURE PROCESSOR The audio feature processor automatically provides

de-emphasis for the IEC 60958 data stream in the static pin control mode and default mute at start-up in either the L3-bus or I2C-bus mode.

When usedin L3-bus or I2C-bus modes,the audio feature processor provides the following additional features:

• Independent left and right channel volume control

• Bass boost control

• Treble control

• Selection of sound processing modes for bass boost

and treble filters: flat, minimum and maximum

• Soft mute control with raised cosine roll-off

• De-emphasis of the incoming data stream selectable at

a sampling frequency of either 32.0, 44.1 or 48.0 kHz.

handbook, halfpage

16, 17

UDA1352HL

MGU611

75 Ω

SPDIF0,

SPDIF1

10 nF

180 pF

Fig.4 IEC 60958 input circuit and typical

application.

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Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352HL

8.6.3 INTERPOLATOR The UDA1352HL has an on-board interpolating filter that

convertsthe incoming datastreamfrom 1fsto 64fsor 128f by cascading a recursive filter and a Finite Impulse Response (FIR) filter.

Table 3 Interpolator characteristics

PARAMETER CONDITIONS VALUE (dB)

Pass-band ripple 0 to 0.45f Stop band >0.55f Dynamic range 0 to 0.45f

±0.03

−50

114

DC gain −−5.67

8.6.4 NOISE SHAPER The fifth-order noise shaper operates either at

64fsor 128fs. It shifts in-band quantization noise to frequencieswell abovetheaudio band.Thisnoise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted to an analog signal using a filter stream DAC.

8.6.5 FILTER STREAM DAC

8.7 Control

The UDA1352HL can be controlled by static pins (when pin SELSTATIC is HIGH), via the I2C-bus (when

pin SELSTATIC is LOW and pin SELIIC is HIGH) or via the L3-bus (when pins SELSTATIC and SELIIC are both LOW). For optimum use ofthe UDA1352HLfeatures, theL3-bus orI2C-busmodes arerecommended since only basic functionsare available in the static pin controlmode.

Notethat thestaticpin controlmode and L3-busor I2C-bus modes are mutually exclusive. In the static pin control mode, pins L3MODE and L3DATA are used to select the format for the data output and input interface (see Fig.5).

The Filter Stream DAC (FSDAC) is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage.

The filter coefficients are implemented as current sources andare summedatvirtual groundof the outputoperational amplifier. In this way, very high signal-to-noise performance and low clock jitter sensitivity is achieved. A post filter is notneeded dueto theinherent filterfunction of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output.

The output voltage of the FSDAC is scaled proportionally to the power supply voltage.

2003 Mar 25 14

Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352HL

MGS752

B15 LSB

B19 LSB

B23 LSB

handbook, full pagewidth

RIGHT

> = 8

21> = 812 3

RIGHT

1518 1720 19 2 1

MSB B2 B3 B4 B5 B6

LSB

B19

LSB-JUSTIFIED FORMAT 20 BITS

1518 1720 19 2 1

15 2 1

MSB B2

RIGHT

LSB

B15

LSB-JUSTIFIED FORMAT 16 BITS

15 2 1

MSB

MSB MSBB2

RIGHT

1518 1720 1922 212324 21

1518 1720 1922 212324 2 1

B5 B6 B7 B8 B9 B10

B3 B4

MSB

LSB

B23

LSB-JUSTIFIED FORMAT 24 BITS

Fig.5 Digital data interface formats.

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2003 Mar 25 15

LEFT

BCK

MSB B2

DATA

S-BUS FORMAT

LEFT

BCK

DATA

LEFT

BCK

MSB B2 B3 B4 B5 B6

DATA

LEFT

BCK

B5 B6 B7 B8 B9 B10

B3 B4

MSB

DATA

Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352HL

8.7.1 STATIC PIN CONTROL MODE The functions of the static pins in static pin control mode are described in Table 4.

Table 4 Pin descriptions in static pin control mode

PIN NAME VALUE FUNCTION

Mode selection pin

38 SELSTATIC 1 select static pin control mode; must be connected to V

Input pins

1 RESET 0 normal operation

1 reset

6 L3CLOCK 0 must be connected to V

10 and 5 L3MODEand

L3DATA

00 select I2S-bus format for digital data interface 01 select LSB-justiﬁed format 16 bits for digital data interface

SSD

10 select LSB-justiﬁed format 20 bits for digital data interface 11 select LSB-justiﬁed format 24 bits for digital data interface

13 MUTE 0 no mute

1 mute active

14 SELCHAN 0 select input SPDIF 0 (channel 0)

1 select input SPDIF 1 (channel 1)

21 SELCLK 0 slave to fs from IEC 60958; master on data output and input interfaces

1 slave to f

from digital data input interface

22 SELSPDIF 0 select data from digital data interface to DAC output

1 select data from IEC 60958 decoder to DAC output

Status pins

43 PCMDET 0 non-PCM data or burst preamble detected

1 PCM data detected

23 LOCK 0 clock regeneration and IEC 60958 decoder out-of-lock or non-PCM

data detected

1 clock regeneration and IEC 60958 decoder locked and PCM data

detected

33 and 45 PREEM1and

PREEM0

00 IEC 60958 input; no pre-emphasis 01 IEC 60958 input; fs= 32.0 kHz with pre-emphasis 10 IEC 60958 input; f 11 IEC 60958 input; f

= 44.1 kHz with pre-emphasis

= 48.0 kHz with pre-emphasis

Test pin

25 TEST 0 must be connected to V

SSD

DDD

2003 Mar 25 16

Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352HL

8.7.2 L3-BUS OR I2C-BUS MODES The L3-bus or I2C-bus modes allow maximum flexibility for controlling the UDA1352HL. The default values forall nonpin-controlled settingsare identical tothe defaultvalues atstart-up in the L3-bus orI2C-bus

modes. The default values are given in Section 12. It should be noted that in either L3-bus or I2C-bus mode, several base-line functions are still controlled by static pins

(see Table 5). However, in L3-bus or I2C-bus modes, on start-up, the output is muted only by bit MT in register address 13H via the L3-bus or I2C-bus interfaces.

Table 5 Pin descriptions in L3-bus or I

PIN NAME VALUE FUNCTION

Mode selection pins

38 SELSTATIC 0 select L3-bus mode or I 47 SELIIC 0 select L3-bus mode; must be connected to V

Input pins

1 RESET 0 normal operation

5 L3DATA − must be connected to the L3-bus

6 L3CLOCK − must be connected to the L3-bus

10 L3MODE − must be connected to the L3-bus 13 MUTE 0 no mute

Status pins

43 PCMDET 0 non-PCM data or burst preamble detected

23 LOCK 0 clock regeneration and IEC 60958 decoder out-of-lock or non-PCM

33 and 45 PREEM1and

PREEM0

Test pins

25 TEST 0 must be connected to V

C-bus modes

C-bus mode; must be connected to V

SSD

1 select I2C-bus mode; must be connected to V

DDD

1 reset

− must be connected to the SDA line of the I2C-bus

− must be connected to the SCL line of the I

C-bus

1 mute active

1 PCM data detected

data detected

1 clock regeneration and IEC 60958 decoder locked and PCM data

detected 00 IEC 60958 input; no pre-emphasis 01 IEC 60958 input; f 10 IEC 60958 input; f 11 IEC 60958 input; f

= 32.0 kHz with pre-emphasis

= 44.1 kHz with pre-emphasis

= 48.0 kHz with pre-emphasis

SSD

2003 Mar 25 17

Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352HL

9 L3-BUS DESCRIPTION

9.1 General

The UDA1352HL has an L3-bus microcontroller interface allowing all the digital sound processing features and various system settings to be controlled by a microcontroller.

The controllable settings are:

• Restoring of L3-bus default values

• Power-on

• Selection offilter mode, and settings fortreble and bass

boost

• Volume settings for left and right channels

• Selection of soft mute via cosine roll-off and bypass of

auto mute

• Selection of de-emphasis (mode 4 to mode 8 only). The readable settings are:

• Mute status of interpolator

• PLL locked

• SPDIF input signal locked

• Audio sample frequency

• Valid PCM data detected

• Pre-emphasis of the IEC 60958 input signal

• Clock accuracy.

Theexchange ofdata andcontrol informationbetween the microcontroller and the UDA1352HL is LSB first and is accomplished through the serial hardware L3-bus interface comprising the following pins:

• L3DATA: data line

• L3MODE: mode line

• L3CLOCK: clock line.

The L3-bus format has two modes of operation:

• Address mode

• Data transfer mode.

The address mode is used to select a device for a subsequent data transfer. The address mode is characterized by L3MODE being LOW and a burst of 8 pulseson L3CLOCK,accompanied by8 bits (seeFig.6). The data transfer mode is characterized by L3MODE being HIGH and is used to transfer one or more bytes representing a register address, instruction or data.

Remark: when the device is powered-up, the L3-bus interfacemust receiveat leastone L3CLOCKpulse before data can be sent to the device (see Fig.6). This is only required once after the device is powered-up.

9.2 Device addressing

The device address is one byte comprising:

• DataOperating Mode (DOM)bits 0 and 1 specifyingthe type of data transfer (see Table 6)

• Address bits 2 to 7 specifying a 6-bit device address. Bits 2 and 3 of the address are selected via external pins DA0 and DA1, allowing up to four UDA1352HL devices to be independently controlled in a single application.

The primary address of the UDA1352HL is ‘001000’ (LSB to MSB) and the default address is ‘011000’.

Table 6 Selection of data transfer

DOM

TRANSFER

BIT 0 BIT 1

0 0 not used 1 0 not used 0 1 write data or prepare read 1 1 read data

9.3 Register addressing

The device register address is one byte comprising:

• Bit 0 specifying that data is to be either read or written

• Address bits 1 to 7 specifying the 7-bit register address.

There are three types of register addressing:

• To write data: bit 0 is logic 0 specifying that data will be written to the device register, followed by bits 1 to 7 specifying the device register address (see Fig.6)

• To prepareread: bit 0 islogic 1, specifying that data will be read from the device register (see Fig.7)

• To read data: the device returns the device register address prior to sending data from that register. When bit 0 is logic 0, the register address is valid;when bit 0is logic 1, the register address is invalid.

There are two types of data transfers:

• Write action: data transfer to the device

• Read action: data transfer from the device.

2003 Mar 25 18

Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352HL

MBL565

MGS753

data byte 1 data byte 2

device address

10 0

L3 wake-up pulse after power-up

L3CLOCK

L3MODE

L3DATA

write

DOM bits

Fig.6 Data write mode (for L3-bus version 2).

requesting

0/1

valid/invalid

Fig.7 Data read mode.

read

prepare read sent by the device

device address

111 0

DOM bits

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2003 Mar 25 19

L3CLOCK

L3MODE

L3DATA

Philips Semiconductors Preliminary speciﬁcation

48 kHz IEC 60958 audio DAC UDA1352HL

9.4 Data write mode

The data write mode is explained in the signal diagram of Fig.6. To write data to a device requires four bytes to be sent (see Table 7):

1. One byte starting with ‘01’ specifying a write action, followed by the device address (‘011000’ for the UDA1352HL default)

2. One byte starting with ‘0’ specifying a write action, followed by seven bits specifying the device register address in binary format, with A6 being the MSB and A0 being the LSB

3. First of two data bytes with D15 being the MSB

4. Second of two data bytes with D0 being the LSB.

Note that to write data to a different register within the same devicerequires the device address to be sentagain.

9.5 Data read mode

The data read mode is explained in the signal diagram of Fig.7. To read data from a device requires a prepare read followed bya data read.Six bytes are used,(see Table 8):

Table 7 L3-bus write data

1. One byte starting with ‘01’ specifying a prepare read action to the device, followed by the device address

2. One byte starting with ‘1’ specifying a read action, followed by seven bits specifying the device register addressfrom whichdata needs tobe read,followed by seven bits specifying the source register address in binary format, with A6 being the MSB and A0 being the LSB

3. One byte starting with ‘11’ instructing the device to write data to the microcontroller, followed by the device address

4. One byte, sent by the device to the bus, starting with either a logic 0 to indicate that the requesting register is valid, or a logic 1 to indicate that the requesting register is invalid, followed by the requesting register address

5. First of two data bytes, sent by the device to the bus, with D15 being the MSB

6. Second of two bytes, sent by the device to the bus, with D0 being the LSB.

BYTE

1 address device address 0 1 DA0 DA1 1000 2 data transfer register address 0 A6 A5 A4 A3 A2 A1 A0 3 data transfer data byte 1 D15 D14 D13 D12 D11 D10 D9 D8 4 data transfer data byte 2 D7 D6 D5 D4 D3 D2 D1 D0

Table 8 L3-bus read data

BYTE

1 address device address 0 1 DA0 DA1 1000 2 data transfer register address 1 A6 A5 A4 A3 A2 A1 A0 3 address device address 1 1 DA0 DA1 1000 4 data transfer requesting register

5 data transfer data byte 1 D15 D14 D13 D12 D11 D10 D9 D8 6 data transfer data byte 2 D7 D6 D5 D4 D3 D2 D1 D0

L3-BUS

MODE

L3-BUS

MODE

ACTION

address

FIRST IN TIME LAST IN TIME

BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

FIRST IN TIME LAST IN TIME

BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

0 or 1 A6 A5 A4 A3 A2 A1 A0

2003 Mar 25 20

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