Philips UDA1351TS Datasheet

INTEGRATED CIRCUITS

DATA SH EET

UDA1351TS

96 kHz IEC 958 audio DAC

Preliminary speciﬁcation File under Integrated Circuits, IC01

2000 Mar 28

Philips Semiconductors Preliminary speciﬁcation

96 kHz IEC 958 audio DAC UDA1351TS

CONTENTS

1 FEATURES

1.1 General

1.2 Control

1.3 IEC 958 input

1.4 Digital sound processing and DAC 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 QUICK REFERENCE DATA 5 ORDERING INFORMATION 6 BLOCK DIAGRAM 7 PINNING 8 FUNCTIONAL DESCRIPTION

8.1 Clock regeneration and lock detection

8.2 Mute

8.3 Auto mute

8.4 Data path

8.4.1 IEC 958 input

8.4.2 Audio feature processor

8.4.3 Interpolator

8.4.4 Noise shaper

8.4.5 The Filter Stream DAC (FSDAC)

8.5 Control

8.5.1 Static pin control mode

8.5.2 L3 control mode

8.6 L3 interface

8.6.1 General

8.6.2 Device addressing

8.6.3 Register addressing

8.6.4 Data write mode

8.6.5 Data read mode

8.6.6 initialization string

8.6.7 Overview of L3 interface registers

8.6.8 Writable registers

8.6.9 Readable registers

9 LIMITING VALUES 10 THERMAL CHARACTERISTICS 11 CHARACTERISTICS 12 TIMING CHARACTERISTICS 13 APPLICATION INFORMATION 14 PACKAGE OUTLINE 15 SOLDERING

15.1 Introduction to soldering surface mount packages

15.2 Reflow soldering

15.3 Wave soldering

15.4 Manual soldering

15.5 Suitability of surface mount IC packages for wave and reflow soldering methods

16 DEFINITIONS 17 LIFE SUPPORT APPLICATIONS

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Philips Semiconductors Preliminary speciﬁcation

96 kHz IEC 958 audio DAC UDA1351TS

1 FEATURES

1.1 General

• 2.7 to 3.6 V power supply

• Integrated digital filter and Digital-to-Analog Converter

(DAC)

• Master-mode dataoutput and input interface for off-chip sound processing

• 256fssystem clock output

• 20-bit data path in interpolator

• High performance

• No analog post filtering required for DAC

• Support sampling frequencies from 28 kHz up

to 100 kHz

• The UDA1351TS is fully pin and function compatible with the UDA1350ATS.

1.2 Control

Controlled either by means of static pins or via the L3 microcontroller interface.

1.3 IEC 958 input

• On-chip amplifier for convertingIEC 958 inputto CMOS levels

• Lock indication signal available on pin LOCK

• Lock indication signal combined on-chip with the Pulse

Code Modulation (PCM) status bit; when non-PCM is detected, pin LOCK indicates out-of-lock

• Key channel-status bits available via L3 interface (lock, pre-emphasis, audio sample frequency, two channel PCM indication and clock accuracy).

2 APPLICATIONS

Digital audio systems.

3 GENERAL DESCRIPTION

Available in two versions:

• UDA1351TS: – only IEC 958 input to DAC in SSOP28 package.

• UDA1351H: – full featured version in QFP44 package.

The UDA1351TS is a single chip IEC 958 audio decoder with an integrated stereo DAC employing bitstream conversion techniques.

A lock indication signal is available on pin LOCK, indicating that the IEC 958 decoder is locked. This pin is also used to indicate whether PCM data is applied to the input or not. When non-PCM data is detected, the device indicates out-of-lock.

By default, the DAC output and the data output interface are muted when the decoder is out-of-lock. However, this setting can be overruled in the L3 control mode.

1.4 Digital sound processing and DAC

• Automatic de-emphasis when using IEC 958 input with

32.0, 44.1 and 48.0 kHz audio sample frequencies

• Soft mute by meansof acosine roll-offcircuit selectable via pin MUTE or the L3 interface

• dB linear volume control with 1 dB steps from 0 dB to

−60 dB and −∞ dB

• Bass boost and treble control in L3 control mode

• Interpolating filter (fsto 128fs) by means ofa cascade of

a recursive filter and a FIR filter

• Third order noise shaper operating at 128fsgenerates the bitstream for the DAC

• Filter Stream DAC (FSDAC).

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Philips Semiconductors Preliminary speciﬁcation

96 kHz IEC 958 audio DAC UDA1351TS

4 QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

DDD

DDA

DDA(DAC)

DDA(PLL)

DDD(C)

DDD

P power consumption at 48 kHz DAC in playback mode − 80 − mW

General

rst

amb

Digital-to-analog converter

o(rms)

(THD + N)/S total harmonic

S/N signal-to-noise ratio at 48 kHz f

∆V

digital supply voltage 2.7 3.0 3.6 V analog supply voltage 2.7 3.0 3.6 V analog supply current of DAC power-on − 8.0 − mA

power-down − 750 −µA

analog supply current of PLL at 48 kHz − 0.7 − mA

at 96 kHz − 1.0 − mA

digital supply current of core at 48 kHz − 16.0 − mA

at 96 kHz − 24.5 − mA

digital supply current at 48 kHz − 2.0 − mA

at 96 kHz − 3.0 − mA

DAC in Power-down mode − 58 − mW

power consumption at 96 kHz DAC in playback mode − 109 − mW

DAC in Power-down mode − 87 − mW

reset active time − 250 −µs ambient temperature −40 − +85 °C

output voltage (RMS value) note 1 − 900 − mV

= 1.0 kHz tone at 48 kHz

distortion-plus-noise to signal ratio

at 0 dB −−90 −85 dB at −40 dB; A-weighted −−60 −55 dB

= 1.0 kHz tone at 96 kHz

at 0 dB −−85 −80 dB at −40 dB; A-weighted −−57 −52 dB

= 1.0 kHz tone; code = 0; A-weighted 95 100 − dB

signal-to-noise ratio at 96 kHz f

= 1.0 kHz tone; code = 0; A-weighted 95 100 − dB

channel separation fi= 1.0 kHz tone − 96 − dB unbalance of output voltages fi= 1.0 kHz tone − 0.1 0.4 dB

Note

1. The output voltage of the DAC is proportional to the DAC power supply voltage.

5 ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

UDA1351TS SSOP28 plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1

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Philips Semiconductors Preliminary speciﬁcation

96 kHz IEC 958 audio DAC UDA1351TS

6 BLOCK DIAGRAM

handbook, full pagewidth

DDA(PLL)

SSA(PLL)

DDD(C)

L3MODE

L3CLOCK

L3DATA

SELSTATIC

SPDIF

DDD

SSD

SSD(C)

24 23

TIMING CIRCUIT

9 8

3 7 12

n.c.

TEST1 TEST3

CLOCK

AND

INTERFACE

SLICER

1, 2, 27

TEST2

IEC 958

DECODER

LOCK

TEST4

UDA1351TS

SSA

DDA

DDA(DAC)

VOUTL

DAC

AUDIO FEATURE PROCESSOR

SSA(DAC)

NOISE SHAPER

INTERPOLATOR

ref

VOUTR

DAC

MGU032

MUTE

RESET

Fig.1 Block diagram.

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Philips Semiconductors Preliminary speciﬁcation

96 kHz IEC 958 audio DAC UDA1351TS

7 PINNING

SYMBOL PIN TYPE

(1)

DESCRIPTION

n.c. 1 − not connected n.c. 2 − not connected V

DDD

TEST1 4 DID test pin 1; must be connected to digital ground (V

3 DS digital supply voltage

SSD

) RESET 5 DISD reset input V

DDD(C)

SSD

6 DS digital supply voltage for core

7 DGND digital ground L3DATA 8 DIOS L3 interface data input and output L3CLOCK 9 DIS L3 interface clock input L3MODE 10 DIS L3 interface mode input MUTE 11 DID mute control input V

SSD(C)

12 DGND digital ground SPDIF 13 AI IEC 958 channel input V

DDA(DAC)

14 AS analog supply voltage for DAC VOUTL 15 AO analog DAC left channel output LOCK 16 DO SPDIF and PLL lock indicator output VOUTR 17 AO analog DAC right channel output TEST2 18 DID test pin 2; must be connected to digital ground (V V

ref

SSA(DAC)

SSA

DDA

SSA(PLL)

DDA(PLL)

19 A DAC reference voltage

20 AGND analog ground for DAC

21 AGND analog ground

22 AS analog supply voltage

23 AGND analog ground for PLL

24 AS analog supply voltage for PLL

SSD

)

TEST4 25 DIU test pin 4; must be connected to the digital supply voltage (V SELSTATIC 26 DIU static pin control selection input n.c. 27 − not connected TEST3 28 DISD test pin 3; must be connected to digital ground (V

SSD

)

DDD

)

Note

1. See Table 1.

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Philips Semiconductors Preliminary speciﬁcation

96 kHz IEC 958 audio DAC UDA1351TS

Table 1 Pin type references

PIN TYPE DESCRIPTION

DS digital supply DGND digital ground AS analog supply AGND analog ground DI digital input DIS digital Schmitt-triggered input DID digital input with internal pull-down resistor DISD digital Schmitt-triggered input with internal pull-down resistor DIU digital input with internal pull-up resistor DO digital output DIO digital input and output DIOS digital Schmitt-triggered input and output A analog reference voltage AI analog input AO analog output

handbook, halfpage

DDA(DAC)

n.c.

2 3

DDD

TEST1

RESET

DDD(C)

L3DATA

L3CLOCK

L3MODE

SSD(C)

SSD

MUTE

SPDIF

5 6 7

UDA1351TS

9 10 11 12 13 14

Fig.2 Pin configuration.

MGU033

TEST3

n.c.

27 26

SELSTATIC

TEST4

V V

TEST2

VOUTR

LOCK

VOUTL

DDA(PLL) SSA(PLL) DDA SSA SSA(DAC) ref

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Philips Semiconductors Preliminary speciﬁcation

96 kHz IEC 958 audio DAC UDA1351TS

8 FUNCTIONAL DESCRIPTION

TheUDA1351TS isa low costaudio IEC 958decoder with an on-board DAC. The minimum audio input sampling frequency conforming to the IEC958 standard is 28.0 kHz and the maximum audio sampling frequency is 100.0 kHz.

8.1 Clock regeneration and lock detection

The UDA1351TS contains an on-board PLL for regenerating a system clock from the IEC 958 input bitstream.

Note: If there is no input signal, the PLL generates a minimum frequency and the output spectrum shifts accordingly. Since the analog output does not have an analog mute, this means noise that is out of band under normal conditions can move into the audio band.

When the on-board clocklocks tothe incoming frequency, the lock indicator bit is set and can be read via the L3 interface. Internally, the PLL lock indication is combined with thePCM statusbit ofthe input data stream. When both the IEC 958 decoder and the on-board clock have locked to the incoming signal and the input data stream is PCM data, pin LOCK will beasserted. However, when the IC is locked but the PCM status bit reports non-PCM data, pin LOCK is returned to LOW level.

The lock indication output can be used, for example, for muting purposes. The lock signal can be used to drive an external analog muting circuitto prevent out of bandnoise from becoming audible when the PLL runs at its minimum frequency (e.g. when there is no SPDIF input signal).

8.2 Mute

The UDA1351TS is equippedwith a cosine roll-off mutein the DSP data path of the DAC part. Muting the DAC, by pin MUTE (in static mode) or via bit MT (in L3 mode), will result in a soft mute, asshown in Fig.3. The cosine roll-off soft mute takes 32 x 32 samples = 24 ms at 44.1 kHz sampling frequency.

When operating in the L3 control mode, the device will mute on start-up. In L3 mode, it is necessary to explicitly switch off themute foraudio output bymeans ofthe MT bit in the L3 register.

Inthe L3 mode,pin MUTE does nothave anyfunction (the same holds for several other pins) and can either be left open circuit (since it has an internal pull-down resistor) or be connected to ground.

handbook, halfpage

mute

factor

0.8

0.6

0.4

0.2

01051525

MGU119

t (ms)

Fig.3 Mute as a function of raised cosine roll-off.

8.3 Auto mute

By default, the DAC outputs will be muted until the IC is locked, regardless of the level on pin MUTE (in static mode) or the state of bit MT of the sound feature register (in L3 mode). In this way, only valid data will be passed to the outputs. This mute is done in the SPDIF interface and is a hard mute, not a cosine roll-off mute.

If needed, this muting can be bypassed by setting bit AutoMT to logic 0 via the L3 interface. As a result, the IC will no longer mute during out-of-lock situations.

8.4 Data path

The UDA1351TS data path consists of the IEC 958 decoder, the audio feature processor, digital interpolator and noise shaper and the DACs.

8.4.1 IEC 958

INPUT

The UDA1351TS IEC 958 decoder features an on-chip amplifierwithhysteresis, which amplifiesthe IEC 958input signal to CMOS level (see Fig.4).

All 24 bits of data for left and right are extracted from the input bitstream as well as several of the IEC 958 key channel-status bits.

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Philips Semiconductors Preliminary speciﬁcation

96 kHz IEC 958 audio DAC UDA1351TS

When used in the L3 control mode, it provides the following additional features:

• Volume control, using 6 bits

• Bass boost control, using 4 bits

handbook, halfpage

75 Ω

10 nF

180 pF

13SPDIF

UDA1351TS

Fig.4 IEC 958 input circuit and typical application.

MGU034

• Treble control, using 2 bits

• Mode selection of thesound processingbass boost and

treble filters: flat, minimum and maximum

• Soft mute control with raised cosine roll-off

• De-emphasis selection of the incoming data stream for

fs= 32.0, 44.1 and 48.0 kHz.

8.4.3 INTERPOLATOR The UDA1351TS includes an on-board interpolating filter

which converts the incomingdata stream from 1fsto 128f by cascading a recursive filter and a FIR filter.

Table 2 Interpolator characteristics

The extracted key parameters are:

• Pre-emphasis

• Audio sample frequency

• Two-channel PCM indicator

• Clock accuracy.

Both the lock indicator and the key channel status bits are accessible via the L3 interface.

The UDA1351TS supports the following sample frequencies and data bit rates:

fs= 32.0 kHz, resulting in a data rate of 2.048 Mbits/s fs= 44.1 kHz, resulting in a data rate of 2.8224 Mbits/s fs= 48.0 kHz, resulting in a data rate of 3.072 Mbits/s fs= 64.0 kHz, resulting in a data rate of 4.096 Mbits/s fs= 88.2 kHz, resulting in a data rate of 5.6448 Mbits/s fs= 96.0 kHz, resulting in a data rate of 6.144 Mbits/s.

The UDA1351TS supports timing levels I, II and III, as specified by the IEC 958 standard.

8.4.2 AUDIO FEATURE PROCESSOR The audio feature processor automatically provides

de-emphasis for the IEC 958 data stream in the static pin control mode and defaultmute at start-up in theL3 control mode.

PARAMETER CONDITIONS VALUE (dB)

Pass-band ripple 0 to 0.45f Stop band >0.65f

Dynamic range 0 to 0.45f

±0.03

−50

115

DC gain −−3.5

8.4.4 NOISE SHAPER The third-order noise shaper operates at 128fs. It shifts

in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper outputis converted toananalog signal usinga filter stream DAC.

8.4.5 THE FILTER STREAM DAC (FSDAC) The FSDAC is a semi-digital reconstruction filter that

converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way, very high signal-to-noise performance and low clock jitter sensitivityis achieved. A post-filter is not needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output.

The output voltage of the FSDAC is scaled proportionally with the power supply voltage.

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