Philips UDA1350ATS Datasheet

INTEGRATED CIRCUITS

DATA SHEET

UDA1350ATS

IEC 60958 audio DAC

Product specification

2001 Mar 27

Supersedes data of 2000 Mar 29

File under Integrated Circuits, IC01

Philips Semiconductors	Product specification
IEC 60958 audio DAC	UDA1350ATS

CONTENTS

1 FEATURES

1.1General

1.2Control

1.3IEC 60958 input

1.4Digital sound processing and DAC

2APPLICATIONS

3GENERAL DESCRIPTION

4QUICK REFERENCE DATA

5ORDERING INFORMATION

6BLOCK DIAGRAM

7PINNING

8FUNCTIONAL DESCRIPTION

8.1Clock regeneration and lock detection

8.2Mute

8.3Auto mute

8.4Data path

8.4.1IEC 60958 input

8.4.2Audio feature processor

8.4.3Interpolator

8.4.4Noise shaper

8.4.5Filter stream DAC

8.5Control

8.5.1Static pin control mode

8.5.2L3 control mode

8.6L3 interface

8.6.1General

8.6.2Device addressing

8.6.3Register addressing

8.6.4Data write mode

8.6.5Data read mode

8.6.6Initialisation string

8.6.7Overview of L3 interface registers

8.6.8Writable registers

8.6.9Readable registers

9LIMITING VALUES

10THERMAL CHARACTERISTICS

11CHARACTERISTICS

12TIMING CHARACTERISTICS

13APPLICATION INFORMATION

14PACKAGE OUTLINE

15SOLDERING

15.1Introduction to soldering surface mount packages

15.2Reflow soldering

15.3Wave soldering

15.4Manual soldering

15.5Suitability of surface mount IC packages for wave and reflow soldering methods

16DATA SHEET STATUS

17DEFINITIONS

18DISCLAIMERS

2001 Mar 27

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Philips Semiconductors	Product specification
IEC 60958 audio DAC	UDA1350ATS

1 FEATURES

1.1General

∙2.7 to 3.6 V power supply

∙Integrated digital filter and Digital-to-Analog Converter (DAC)

∙256fs system clock output

∙20-bit data path in interpolator

∙High performance

∙No analog post filtering required for DAC.

1.2Control

∙Controlled either by means of static pins or via the L3 microcontroller interface.

1.3IEC 60958 input

∙On-chip amplifier for converting IEC 60958 input to CMOS levels

∙Lock indication signal available on pin LOCK

∙Lock indication signal combined on-chip with the Pulse Code Modulation (PCM) status bit; in case non-PCM has been detected pin LOCK indicates out-of-lock

∙Key channel-status bits available via L3 interface (lock, pre-emphasis, audio sample frequency, two channel PCM indication and clock accuracy).

1.4Digital sound processing and DAC

∙Automatic de-emphasis when using IEC 60958 input with 32.0, 44.1 and 48.0 kHz audio sample frequencies

∙Soft mute by means of a cosine roll-off circuit selectable via pin MUTE or the L3 interface

∙dB linear volume control with 1 dB steps from 0 dB to −60 dB and −∞ dB

∙Bass boost and treble control in L3 control mode

∙Interpolating filter (fs to 128fs) by means of a cascade of a recursive filter and a FIR filter

∙Third order noise shaper operating at 128fs generates the bitstream for the DAC

∙Filter stream digital-to-analog converter.

2 APPLICATIONS

∙ Digital audio systems.

3 GENERAL DESCRIPTION

Available in two versions:

∙UDA1350ATS:

–only IEC 60958 input to DAC in SSOP28 package.

∙UDA1350AH:

–full featured version in QFP44 package.

The UDA1350ATS is a single chip IEC 60958 audio decoder with an integrated stereo digital-to-analog converter employing bitstream conversion techniques.

A lock indication signal is available on pin LOCK indicating that the IEC 60958 decoder is locked. This pin is also used to indicate whether PCM data is applied to the input or not. In the event non-PCM data has been detected, the device indicates out-of-lock.

By default the DAC output and the data output interface are muted when the decoder is out-of-lock. However, this setting can be overruled in the L3 control mode.

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Philips Semiconductors				Product specification
IEC 60958 audio DAC				UDA1350ATS
4 QUICK REFERENCE DATA
SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
Supplies
VDDD	digital supply voltage		2.7	3.0	3.6	V
VDDA	analog supply voltage		2.7	3.0	3.6	V
IDDA(DAC)	analog supply current of DAC	power-on	−	8.0	−	mA
		power-down	−	750	−	μA
IDDA(PLL)	analog supply current of PLL		−	0.7	−	mA
IDDD	digital supply current		−	2.0	−	mA
IDDD(C)	digital supply current of core		−	16.0	−	mA
P	power consumption	DAC in playback mode	−	80	−	mW
		DAC in Power-down mode	−	58	−	mW
General
trst	reset active time		−	250	−	μs
Tamb	ambient temperature		−40	−	+85	°C
Digital-to-Analog Converter
Vo(rms)	output voltage (RMS value)	note 1	−	900	−	mV
(THD + N)/S	total harmonic	fi = 1.0 kHz tone
	distortion-plus-noise to signal	at 0 dB	−	−90	−85	dB
	ratio	at −40 dB; A-weighted	−	−60	−55	dB
S/N	signal-to-noise ratio	fi = 1.0 kHz tone;	95	100	−	dB
		code = 0; A-weighted
αcs	channel separation	fi = 1.0 kHz tone	−	96	−	dB
Vo	unbalance of output voltages	fi = 1.0 kHz tone	−	0.1	0.4	dB

Note

1. The output voltage of the DAC is proportional to the DAC power supply voltage.

5 ORDERING INFORMATION

TYPE		PACKAGE
NUMBER	NAME	DESCRIPTION	VERSION
UDA1350ATS	SSOP28	plastic shrink small outline package; 28 leads	SOT341-1

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Philips Semiconductors	Product specification
IEC 60958 audio DAC	UDA1350ATS
6 BLOCK DIAGRAM

TEST1

TEST3

VSSA

VDDA(DAC)

Vref

TEST2

TEST4

VDDA

VOUTL

VSSA(DAC)

VOUTR

24

4

18

28

25

21

22

15

14

20

19

17

VDDA(PLL)

23

VSSA(PLL)

CLOCK

DAC

DAC

AND

TIMING CIRCUIT

6

NOISE SHAPER

UDA1350ATS

VDDD(C)

12

INTERPOLATOR

VSSD(C)

10

L3MODE

L3

9

AUDIO FEATURE PROCESSOR

11

MUTE

L3CLOCK

INTERFACE

8

L3DATA

26

SELSTATIC

SLICER

13

IEC 60958

5

RESET

SPDIF

DECODER

3

VDDD

7

VSSD

1, 2, 27

16

MGL847

n.c.

LOCK

Fig.1 Block diagram.

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Philips Semiconductors					Product specification
	IEC 60958 audio DAC				UDA1350ATS
7	PINNING
	SYMBOL		PIN	TYPE(1)	DESCRIPTION
n.c.			1	−	not connected
n.c.			2	−	not connected
VDDD			3	DS	digital supply voltage
TEST1			4	DID	test pin 1; must be connected to digital ground (VSSD)
RESET			5	DISD	reset input
VDDD(C)			6	DS	digital supply voltage for core
VSSD			7	DGND	digital ground
L3DATA			8	DIOS	L3 interface data input and output
L3CLOCK			9	DIS	L3 interface clock input
L3MODE			10	DIS	L3 interface mode input
MUTE			11	DID	mute control input
VSSD(C)			12	DGND	digital ground for core
SPDIF			13	AI	IEC 60958 channel input
VDDA(DAC)			14	AS	analog supply voltage for DAC
VOUTL			15	AO	analog DAC left channel output
LOCK			16	DO	SPDIF and PLL lock indicator output
VOUTR			17	AO	analog DAC right channel output
TEST2			18	DID	test pin 2; must be connected to digital ground (VSSD)
Vref			19	A	DAC reference voltage
VSSA(DAC)			20	AGND	analog ground for DAC
VSSA			21	AGND	analog ground
VDDA			22	AS	analog supply voltage
VSSA(PLL)			23	AGND	analog ground for PLL
VDDA(PLL)			24	AS	analog supply voltage for PLL
TEST4			25	DIU	test pin 4; must be connected to the digital supply voltage (VDDD)
SELSTATIC			26	DIU	static pin control selection input
n.c.			27	−	not connected
TEST3			28	DISD	test pin 3; must be connected to digital ground (VSSD)
Note
1.	See Table 1.

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Philips Semiconductors		Product specification
IEC 60958 audio DAC		UDA1350ATS
Table 1 Pin type references
PIN TYPE	DESCRIPTION
DS	digital supply
DGND	digital ground
AS	analog supply
AGND	analog ground
DI	digital input
DIS	digital Schmitt-triggered input
DID	digital input with internal pull-down resistor
DISD	digital Schmitt-triggered input with internal pull-down resistor
DIU	digital input with internal pull-up resistor
DO	digital output
DIO	digital input and output
DIOS	digital Schmitt-triggered input and output
A	analog reference voltage
AI	analog input
AO	analog output

handbook, halfpage
n.c.	1		28	TEST3
n.c.	2		27	n.c.
VDDD	3		26	SELSTATIC
TEST1
	4		25	TEST4
RESET
	5		24	VDDA(PLL)
VDDD(C)				VSSA(PLL)
	6		23
VSSD				VDDA
	7		22
L3DATA		UDA1350ATS		VSSA
	8		21
L3CLOCK				VSSA(DAC)
	9		20
L3MODE				Vref
	10		19
MUTE				TEST2
	11		18
VSSD(C)				VOUTR
	12		17
SPDIF				LOCK
	13		16
				VOUTL
VDDA(DAC)	14		15
		MGL845

Fig.2 Pin configuration.

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Philips Semiconductors	Product specification
IEC 60958 audio DAC	UDA1350ATS

8 FUNCTIONAL DESCRIPTION

The UDA1350ATS is a low cost audio IEC 60958 decoder with an on-board DAC. The minimum audio input sampling frequency conforming to the IEC60958 standard is

28.0 kHz and the maximum audio sampling frequency is

54.0 kHz.

8.1Clock regeneration and lock detection

The UDA1350ATS contains an on-board PLL for regenerating a system clock from the IEC 60958 input bitstream.

Note: If there is no input signal, the PLL generates a minimum frequency and the output spectrum shifts accordingly. Since the analog output does not have an analog mute, this means noise that is out of band under normal conditions can move into the audio band.

When the on-board clock has locked to the incoming frequency, the lock indicator bit will be set and can be read via the L3 interface. Internally, the PLL lock indication is combined with the PCM status bit of the input data stream. When both the IEC 60958 decoder and the on-board clock have locked to the incoming signal and the input data stream is PCM data, pin LOCK will be asserted. However, when the IC is locked but the PCM status bit reports non-PCM data, pin LOCK is returned to LOW level.

The lock indication output can be used, for example, for muting purposes. The lock signal can be used to drive an external analog muting circuit to prevent out of band noise from becoming audible when the PLL runs at its minimum frequency (e.g. when there is no SPDIF input signal).

An example of the mute circuit is illustrated in Fig.3 where VDD is the positive power supply and VSS is the negative power supply.

8.2Mute

The UDA1350ATS is equipped with a cosine roll-off mute in the DSP data path of the DAC part. Muting the DAC, by pin MUTE (in static mode) or via bit MT (in L3 mode) will result in a soft mute as presented in Fig.4. The cosine roll-off soft mute takes 32 × 32 samples = 24 ms at

44.1 kHz sampling frequency.

When operating in the L3 control mode the device will mute on start-up. In L3 mode it is necessary to explicitly switch off the mute for audio output by means of the MT bit in the L3 register.

In the L3 mode pin MUTE does not have any function (the same holds for several other pins) and can either be left open-circuit (since it has an internal pull-down resistor) or be connected to ground.

handbook, halfpage				VDD				1	MGU119
								handbook, halfpage
								mute
								factor
16			LOCK					0.8

UDA1350ATS						0.6
			V
	DAC	15 VOUTL			SS
	LEFT						0.4

		0.2
	DAC	17 VOUTR
	RIGHT
					0
					0			5	10	15	20	25
			MGU352									t (ms)

Fig.3 Example of external analog mute circuit.

Fig.4 Mute as a function of raised cosine roll-off.

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Philips Semiconductors	Product specification
IEC 60958 audio DAC	UDA1350ATS

8.3Auto mute

By default the outputs of the digital data output interface and the DAC will be muted until the IC is locked, regardless the level on pin MUTE (in static mode) or the state of bit MT of the sound feature register (in L3 mode). In this way only valid data will be passed to the outputs. This mute is done in the SPDIF interface and is a hard mute, not a cosine roll-off mute.

If needed this muting can be bypassed by setting

bit AutoMT to logic 0 via the L3 interface. As a result the IC will no longer mute during out-of-lock situations.

Both the lock indicator and the key channel status bits are accessible via the L3 interface.

The UDA1350ATS supports the following sample frequencies and data bit rates:

fs = 32.0 kHz, resulting in a data rate of 2.048 Mbits/s

fs = 44.1 kHz, resulting in a data rate of 2.8224 Mbits/s

fs = 48.0 kHz, resulting in a data rate of 3.072 Mbits/s.

The UDA1350ATS supports timing level I, II and III as specified by the IEC 60958 standard.

8.4.2AUDIO FEATURE PROCESSOR

8.4Data path

The UDA1350ATS data path consists of the IEC 60958 decoder, the audio feature processor, digital interpolator and noise shaper and the digital-to-analog converters.

8.4.1IEC 60958 INPUT

The UDA1350ATS IEC 60958 decoder features an on-chip amplifier with hysteresis which amplifies the IEC 60958 input signal to CMOS level (see Fig.5).

handbook, halfpage

					10 nF
75 Ω
					180 pF

SPDIF 13

UDA1350ATS

MGS874

Fig.5 IEC 60958 input circuit and typical application.

All 24 bits of data for left and right are extracted from the input bitstream as well as several of the IEC 60958 key channel-status bits.

The extracted key parameters are:

∙Pre-emphasis

∙Audio sample frequency

∙Two-channel PCM indicator

∙Clock accuracy.

The audio feature processor automatically provides de-emphasis for the IEC 60958 data stream in the static pin control mode and default mute at start-up in the

L3 control mode.

When used in the L3 control mode it provides the following additional features:

∙Volume control using 6 bits

∙Bass boost control using 4 bits

∙Treble control using 2 bits

∙Mode selection of the sound processing bass boost and treble filters: flat, minimum and maximum

∙Soft mute control with raised cosine roll-off

∙De-emphasis selection of the incoming data stream for fs = 32.0, 44.1 and 48.0 kHz.

8.4.3INTERPOLATOR

The UDA1350ATS includes an on-board interpolating filter which converts the incoming data stream from 1fs to 128fs by cascading a recursive filter and a FIR filter.

Table 2 Interpolator characteristics

PARAMETER	CONDITIONS	VALUE (dB)
Pass-band ripple	0 to 0.45fs	±0.03
Stop band	>0.65fs	−50
Dynamic range	0 to 0.45fs	115
DC gain	−	−3.5

8.4.4NOISE SHAPER

The third-order noise shaper operates at 128fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog signal using a filter stream digital-to-analog converter.

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Philips Semiconductors	Product specification
IEC 60958 audio DAC	UDA1350ATS

8.4.5FILTER STREAM DAC

The Filter Stream DAC (FSDAC) is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. A post filter is not needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output.

8.5Control

The UDA1350ATS can be controlled by means of static pins or via the L3 interface. For optimum use of the features of the UDA1350ATS the L3 control mode is recommended since only basic functions are available in the static pin control mode.

It should be noted that the static pin control mode and L3 control mode are mutual exclusive. In the static pin control mode pins L3MODE and L3DATA are used to select the format for the data output and input interface.

8.5.1STATIC PIN CONTROL MODE

The output voltage of the FSDAC is scaled proportionally with the power supply voltage.

The default values for all non-pin controlled settings are identical to the default values at start-up in the L3 control mode.

Table 3 Pin description of static pin control mode

PIN	NAME	VALUE	FUNCTION
Mode selection pin
26	SELSTATIC	1	select static pin control mode; must be connected to VDDD
Input pins
5	RESET	0	normal operation
		1	reset
8	L3DATA	0	must be connected to VSSD
9	L3CLOCK	0	must be connected to VSSD
10	L3MODE	0	must be connected to VSSD
11	MUTE	0	normal operation
		1	mute active
Status pins
16	LOCK	0	clock regeneration and IEC 60958 decoder out-of-lock or non-PCM data
			detected
		1	clock regeneration and IEC 60958 decoder locked and PCM data detected
Test pins
4	TEST1	0	must be connected to digital ground (VSSD)
18	TEST2	0	must be connected to digital ground (VSSD)
25	TEST4	1	must be connected to digital supply voltage (VDDD)
28	TEST3	0	must be connected to digital ground (VSSD)

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