Philips UDA1344TS Datasheet
INTEGRATED CIRCUITS
DATA SH EET
UDA1344TS
Low-voltage low-power stereo
audio CODEC with DSP features
Preliminary specification
File under Integrated Circuits, IC01
1998 Jul 28
Philips Semiconductors Preliminary specification
Low-voltage low-power stereo audio
CODEC with DSP features
FEATURES
General
• Low power consumption
• 3.0 V power supply
• 256, 384 and 512f
• Support sampling frequencies from 16 to 48 kHz
• Non-inverting ADC plus integrated high pass filter to
cancel DC offset
• The ADC supports 2 V (RMS) input signals
• Overload detector for easy record level control
• Separate power control for ADC and DAC
• Integrated digital interpolation filter plus non-inverting
DAC
• Functions controllable either by L3 microcontroller
interface or via static pins
• The UDA1344TS is pin and function compatible with the
UDA1340M
• Small package size (SSOP28)
• Easy application.
Multiple format input interface
2
• I
S-bus, MSB-justified and LSB-justified
16, 18 and 20 bits format compatible
• Three combined data formats with MSB data output and
LSB 16, 18 and 20 bits data input
• 1fs input and output format data rate.
DAC digital sound processing
The sound processing features of the UDA1344TS can
only be used in L3 microcontroller mode.
• Digital tone control, bass boost and treble
• Digital dB-linear volume control (low microcontroller
load) via L3 microcontroller
• Digital de-emphasis for 32, 44.1 and 48 kHz f
• Soft mute.
system clock
s
s
UDA1344TS
Advanced audio configuration
• Stereo single-ended input configuration
• Stereo line output (under microcontroller volume
control), no post filter required
• Power-down click prevention circuitry
• High linearity, dynamic range and low distortion.
GENERAL DESCRIPTION
The UDA1344TS is a single-chip stereo Analog-to-Digital
Converter (ADC) and Digital-to-Analog Converter (DAC)
with signal processing features employing bitstream
conversion techniques. The low power consumption and
low voltage requirements make the device eminently
suitable for use in low-voltage low-power portable digital
audio equipment which incorporates recording and
playback functions.
The UDA1344TS supports the I2S-bus data format with
word lengths of up to 20 bits, the MSB-justified data format
with word lengths of up to 20 bits and the LSB justified
serial data format with word lengths of 16, 18 and 20 bits.
The UDA1344TS also supports three combined data
formats with MSB-justified data output and LSB
16, 18 and 20 bits data input.
The UDA1344TS can be used either with static pin control
or under L3 microcontroller interface. Under L3 control the
UDA1344TS has special sound processing features in
playback mode such as de-emphasis, volume control,
bass boost, treble and soft mute.
ORDERING INFORMATION
TYPE NUMBER
NAME DESCRIPTION VERSION
UDA1344TS SSOP28 plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1
1998 Jul 28 2
PACKAGE
Philips Semiconductors Preliminary specification
Low-voltage low-power stereo audio
UDA1344TS
CODEC with DSP features
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies
V
DDA(ADC)
V
DDA(DAC)
V
DDO
V
DDD
I
DDA(ADC)
I
DDA(DAC)
I
DDO
I
DDD
I
pd(ADC)
I
pd(DAC)
T
amb
Analog-to-digital converter
V
i(rms)
(THD + N)/S total harmonic distortion plus
S/N signal-to-noise ratio V
α
cs
Digital-to-analog converter
V
o(rms)
(THD + N)/S total harmonic distortion plus
S/N signal-to-noise ratio code = 0; A-weighted − 100 − dB
α
cs
Power performance
P
ADDA
P
DA
P
AD
P
PD
ADC analog supply voltage 2.7 3.0 3.6 V
DAC analog supply voltage 2.7 3.0 3.6 V
operational amplifiers supply voltage 2.7 3.0 3.6 V
digital supply voltage 2.7 3.0 3.6 V
ADC supply current operation mode − 9.0 11.0 mA
ADC power-down − 3.5 5.0 mA
DAC supply current operation mode − 4.0 6.0 mA
DAC power-down − 25 75 µA
operational amplifier supply current operation mode − 4.0 6.0 mA
DAC power-down − 250 350 µA
digital supply current operation mode − 6.0 9.0 mA
digital ADC power-down supply current − 2.5 4.0 mA
digital DAC power-down supply current − 3.5 5.0 mA
operating ambient temperature −20 − +85 °C
input voltage (RMS value) notes 1 and 2 − 1.0 − V
at 0 dB −−85 −80 dB
noise-to-signal ratio
at −60 dB; A-weighted −−35 −30 dB
= 0 V; A-weighted − 95 − dB
i
channel separation − 100 − dB
output voltage (RMS value) notes 3 and 4 − 900 − mV
at 0 dB −−90 −85 dB
noise-to-signal ratio
at −60 dB; A-weighted −−37 − dB
channel separation − 100 − dB
power consumption in record and
− 69 − mW
playback mode
power consumption in playback only
− 42 − mW
mode
power consumption in record only
− 37.5 − mW
mode
power consumption in power-down
− 17 − mW
mode
Notes
1. The input voltage can be up to 2 V (RMS) when the current through the ADC input pin is limited to about 1 mA by
using a series resistor.
2. The input voltage to the ADC scales inversely proportional with respect to the power supply.
3. The output voltage of the UDA1344TS differs from the output voltage of the UDA1340M.
4. The output of the DAC scales proportional with the power supply voltage.
1998 Jul 28 3
Philips Semiconductors Preliminary specification
Low-voltage low-power stereo audio
CODEC with DSP features
BLOCK DIAGRAM
handbook, full pagewidth
V
V
VINL
DDD
SSD
V
DDA(ADC)VSSA(ADC)
21
3 5
0 dB/6 dB
SWITCH
10
11
DC-CANCELLATION FILTER
V
ADCP
76 4
ADC
DECIMATION FILTER
ADC
V
ADCN
V
0 dB/6 dB
SWITCH
ref(A)
UDA1344TS
VINR
8
MC1
21
MC2
20
MP5
DATAO
BCK
WS
DATAI
MP1
VOUTL
18
16
17
19
9
UDA1344TS
26
DIGITAL INTERFACE
DSP FEATURES
INTERPOLATION FILTER
NOISE SHAPER
DAC
25 27 23 22
V
DDO
V
SSO
V
DAC
DDA(DAC)VSSA(DAC)
L3-BUS
INTERFACE
V
28
ref(D)
13
MP2
14
MP3
15
MP4
12
SYSCLK
24
VOUTR
MGL441
Fig.1 Block diagram.
1998 Jul 28 4
Philips Semiconductors Preliminary specification
Low-voltage low-power stereo audio
CODEC with DSP features
PINNING
SYMBOL PIN DESCRIPTION
V
SSA(ADC)
V
DDA(ADC)
VINL 3 ADC input left
V
ref(A)
VINR 5 ADC input right
V
ADCN
V
ADCP
MC1 8 mode control 1 (pull-down)
MP1 9 multi purpose pin 1
V
DDD
V
SSD
SYSCLK 12 system clock 256, 384 or 512f
MP2 13 multi purpose pin 2
MP3 14 multi purpose pin 3
MP4 15 multi purpose pin 4
BCK 16 bit clock input
WS 17 word select input
DATAO 18 data output
DATAI 19 data input
MP5 20 multi purpose pin 5 (pull down)
MC2 21 mode control 2 (pull-down)
V
SSA(DAC)
V
DDA(DAC)
VOUTR 24 DAC output right
V
DDO
VOUTL 26 DAC output left
V
SSO
V
ref(D)
1 ADC analog ground
2 ADC analog supply voltage
4 ADC reference voltage
6 ADC negative reference voltage
7 ADC positive reference voltage
10 digital supply voltage
11 digital ground
22 DAC analog ground
23 DAC analog supply voltage
25 operational amplifier supply voltage
27 operational amplifier ground
28 DAC reference voltage
UDA1344TS
handbook, halfpage
s
V
SSA(ADC)
V
DDA(ADC)
V
ref(A)
V
ADCN
V
ADCP
V
V
SYSCLK
VINL
VINR
MC1
MP1
DDD
SSD
MP2
MP3
1
2
3
4
5
6
7
UDA1344TS
8
9
10
11
12
13
MGL442
Fig.2 Pin configuration.
28
27
26
25
24
23
22
21
20
19
18
17
16
1514
V
ref(D)
V
SSO
VOUTL
V
DDO
VOUTR
V
DDA(DAC)
V
SSA(DAC)
MC2
MP5
DATAI
DATAO
WS
BCK
MP4
1998 Jul 28 5
Philips Semiconductors Preliminary specification
Low-voltage low-power stereo audio
CODEC with DSP features
FUNCTIONAL DESCRIPTION
The UDA1344TS accommodates slave mode only, this
means that in all applications the system devices must
provide the system clock.
The system clock must be locked in frequency to the audio
digital interface input signals.
Analog-to-Digital Converter (ADC)
The stereo ADC of the UDA1344TS consists of two
3rd-order Sigma-Delta modulators. They have a modified
Ritchie-coder architecture in a differential switched
capacitor implementation. The over-sampling ratio is 128.
In contrast to the UDA1340M, the UDA1344TS supports
1 V (RMS) input and can be set, via an external resistor,
to support 2 V (RMS) input.
Analog front-end
The analog front-end is equipped with a selectable 0 dB or
6 dB gain block (the pin to select this mode is given in
Section “L3 microcontroller mode”. This block can be used
in applications in which both 1 V (RMS) and 2 V (RMS)
input signals can be input to the UDA1344TS.
In applications in which 2 V (RMS) is used as input signal,
a 12 kΩ must be used in series with the input of the ADC.
This makes a voltage divider with the internal ADC resistor
and makes sure only 1 V (RMS) maximum is put into the
IC. Using this application for a 2 V (RMS) input signal, the
switch must be set to 0 dB. When a 1 V (RMS) input signal
is input to the ADC in the same application, the gain switch
must be set to 6 dB.
In Table 1 an overview is given of the maximum input
voltages allowed against the presence of an external
resistor and the setting of the gain switch.
Table 1 Application modes using input gain stage
RESISTOR
(12 kΩ)
Present 0 dB 2 V (RMS) input signal
Present 6 dB 1 V (RMS) input signal
Absent 0 dB 1 V (RMS) input signal
Absent 6 dB 0.5 V (RMS) input signal
Decimation filter (ADC)
The decimation from 128f
The first stage realizes 3rd-order characteristic.
INPUT GAIN
SWITCH
is performed in two stages.
s
MAXIMUM INPUT
VOLTAGE
sin x
----------- x
UDA1344TS
This filter decreases the sample rate by 16. The second
stage, an FIR filter, consists of 3 half-band filters, each
decimating by a factor of 2.
Table 2 Decimation filter characteristics
ITEM CONDITIONS VALUE (dB)
Passband ripple 0 − 0.45f
Stopband >0.55f
Dynamic range 0 − 0.45f
Overall gain when
s
s
s
DC −1.16
0 dB signal is input to
ADC to digital output
Mute (ADC)
On recovery from power-down or switching on of the
system clock, the serial data output DATAO is held LOW
until valid data is available from the decimation filter. This
time depends on whether the DC cancellation filter is
selected:
DC cancel off: time =
t = 23.2 ms when f
DC cancel on: time =
t = 279 ms when f
1024
------------ f
s
= 44.1 kHz
s
12288
----------------
f
s
= 44.1 kHz
s
Interpolation filter (DAC)
The digital filter interpolates from 1 to 128f
cascade of a recursive filter and an FIR filter.
Table 3 Interpolation filter characteristics
ITEM CONDITIONS VALUE (dB)
Passband ripple 0 − 0.45f
Stopband >0.55f
Dynamic range 0 − 0.45f
s
s
s
Gain DC −3.5
Noise shaper (DAC)
The 3rd-order noise shaper operates at 128fs. It shifts
in-band quantization noise to frequencies well above the
audio band. This noise shaping technique enables high
signal-to-noise ratios to be achieved. The noise shaper
output is converted into an analog signal using a filter
stream digital-to-analog converter.
±0.05
−60
108
by means of a
s
±0.03
−50
108
1998 Jul 28 6
Philips Semiconductors Preliminary specification
Low-voltage low-power stereo audio
CODEC with DSP features
The Filter Stream DAC (FSDAC)
The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at
virtual ground of the output operational amplifier. In this
way very high signal-to-noise performance and low clock
jitter sensitivity is achieved. A post-filter is not needed due
to the inherent filter function of the DAC. On-board
amplifiers convert the FSDAC output current to an output
voltage signal capable of driving a line output.
The output voltage of the FSDAC scales proportionally
with the power supply voltage.
L3MODE or static pin control
The UDA1344TS can be used under L3 microcontroller
interface mode or under static pin control. The mode can
be set via the Mode Control (MC) pins MC1 (pin 8) and
MC2 (pin 21). The function of these pins is given in
Table 4.
Table 4 Mode Control pins MC1 and MC2
MODE MC2 MC1
L3MODE LOW LOW
Test modes LOW HIGH
HIGH LOW
Static pin mode HIGH HIGH
Important: in L3MODE the UDA1344TS is completely pin
and function compatible with the UDA1340M.
UDA1344TS
Table 5 Pinning definition under L3 control
SYMBOL PIN DESCRIPTION
MP1 9 overload
MP2 13 L3-bus mode input
MP3 14 L3-bus clock input
MP4 15 L3-bus data input
MP5 20 ADC 1 or 2 V (RMS) input control
YSTEM CLOCK
S
Under L3 control the options are 256, 384 and 512fs.
M
ULTIPLE FORMAT INPUT/OUTPUT INTERFACE
The UDA1344TS supports the following data input/output
formats under L3 control:
• I2S-bus with data word length of up to 20 bits
• MSB-justified serial format with data word length of up to
20 bits
• LSB-justified serial format with data word lengths of
16, 18 or 20 bits
• Three combined data formats with MSB data output and
LSB 16, 18 and 20 bits LSB data input.
The formats are illustrated in Fig.3. Left and right
data-channel words are time multiplexed.
ADC
INPUT VOLTAGE CONTROL
The UDA1344TS supports 2 V (RMS) input using a series
resistor of 12 kΩ as described in Section “Analog
front-end”. In L3 microcontroller mode, the gain can be
selected via pin MP5.
L3 microcontroller mode
The UDA1344TS is set to the L3 microcontroller mode by
setting both MC1 (pin 8) and MC2 (pin 21) LOW.
The definition of the control registers is given in
Section “L3 interface”.
P
INNING DEFINITION
The pinning definition under L3 microcontroller interface is
given in Table 5.
1998 Jul 28 7
When MP5 is set LOW 0 dB gain is selected. When MP5
is set HIGH 6 dB gain is selected.
O
VERLOAD DETECTION (ADC)
In practice the output is used to indicate whenever the
output data, in either the left or right channel, is greater
than −1 dB (actual figure is −1.16 dB) of the maximum
possible digital swing. When this condition is detected the
OVERFL output is forced HIGH for at least 512fs cycles
(11.6 ms at fs= 44.1 kHz). This time-out is reset for each
infringement.
Philips Semiconductors Preliminary specification
Low-voltage low-power stereo audio
CODEC with DSP features
DC CANCELLATION FILTER (ADC)
An optional IIR high-pass filter is provided to remove
unwanted DC components. The operation is selected by
the microcontroller via the L3-bus. The filter characteristics
are given in Table 6.
Table 6 DC cancellation filter characteristics
ITEM CONDITIONS VALUE (dB)
Passband ripple none
Passband gain 0
Droop at 0.00045f
Attenuation at DC at 0.00000036f
Dynamic range 0 − 0.45f
s
s
s
Static pin mode
The UDA1344TS is set to static pin control mode by setting
both MC1 (pin 8) and MC2 (pin 21) HIGH.
P
INNING DEFINITION
The pinning definition under static pin control is given in
Table 7.
0.031
>40
>110
UDA1344TS
MUTE AND DE-EMPHASIS
Under static pin control via MP2 we can select
de-emphasis and mute. The definition of the MP2 pin is
given in Table 9.
Table 9 Settings for pin MP2
MODE MP2
No de-emphasis and mute LOW
De-emphasis 44.1 kHz 0.5V
Muted HIGH
M
ULTIPLE FORMAT INPUT/OUTPUT INTERFACE
The data input/output formats supported under static pin
control.
• I2S-bus with data word length of up to 20 bits
• MSB justified serial format with data word length of up to
20 bits
• Two combined data formats with MSB data output and
LSB 16 and 20 bits LSB data input.
The data formats can be selected using pins MP1 (pin 9)
and MP5 (pin 20) as given in Table 10.
DDD
Table 7 Pinning definition for static pin control
SYMBOL PIN DESCRIPTION
MP1 9 data input/output setting
MP2 13 three level pin controlling
deemphasis and mute
MP3 14 256f
or 384fs system clock
s
MP4 15 three-level pin to control ADC
power mode and 1 V (RMS) or
2 V (RMS) input
MP5 20 data input/output setting
S
YSTEM CLOCK
Under static pin control the options are 256fs and 384fs.
With pin MP3 (pin 14) the mode can be set as is given in
Table 8.
Table 8 System clock settings under static pin mode
MODE MP3
256f
clock mode LOW
s
384f
clock mode HIGH
s
Table 10 Data format settings under static pin control
INPUT FORMAT MP1 MP5
MSB mode LOW LOW
2
I
S-bus LOW HIGH
MSB output
HIGH LOW
LSB 20 input
MSB output
HIGH HIGH
LSB 16 input
The formats are illustrated in Fig.3. Left and right data
channel words are time multiplexed.
ADC
INPUT VOLTAGE CONTROL
The UDA1344TS supports 2 V (RMS) input using a series
resistor as is described in Section “Analog front-end”.
In static pin mode the three-level pin MP4 (pin 15) is used
to select 0 or 6 dB gain mode. When MP4 is set LOW the
ADC is powered down. When MP4 is set to half the power
supply voltage, then 6 dB gain is selected, and when MP4
is set HIGH then 0 dB gain is selected.
1998 Jul 28 8
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1998 Jul 28 9
ndbook, full pagewidth
Philips Semiconductors Preliminary specification
Low-voltage low-power stereo audio
CODEC with DSP features
WS
BCK
DATA
WS
BCK
DATA
WS
BCK
DATA
WS
BCK
LEFT
>=8 >=8
MSB B2 MSBLSB LSB MSBB2
LEFT
1321
>=8 >=8
MSB B2 MSBLSB LSB MSB B2B2
LEFT
1516 1
MSB LSBB2
LEFT
RIGHT
321321
INPUT FORMAT I
RIGHT
32
MSB-JUSTIFIED FORMAT
2
B15
LSB-JUSTIFIED FORMAT 16 BITS
215161718 1
2
S-BUS
RIGHT
21516 1
MSB LSBB2 B15
RIGHT
215161718 1
DATA
WS
BCK
DATA
MSB B2 B3 B4
LEFT
MSB B2 B3 B4 B5 B6
LSB
B17
LSB-JUSTIFIED FORMAT 18 BITS
2151617181920 1
LSB
B19
LSB-JUSTIFIED FORMAT 20 BITS
Fig.3 Serial interface formats.
MSB B2 B3 B4
RIGHT
MSB B2 B3 B4 B5 B6
B17
B19
LSB
2151617181920 1
LSB
MGG841
UDA1344TS
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