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UDA1334BTS
Datasheet
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Datasheet
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Philips UDA1334BTS Datasheet

INTEGRATED CIRCUITS
DATA SH EET
UDA1334BTS
Low power audio DAC
Product specification Supersedes data of 2000 Feb 07 File under Integrated Circuits, IC01
2000 Jul 31
Philips Semiconductors Product specification
Low power audio DAC UDA1334BTS

CONTENTS

1 FEATURES
1.1 General
1.2 Multiple format data interface
1.3 DAC digital sound processing
1.4 Advanced audio configuration 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 ORDERING INFORMATION 5 QUICK REFERENCE DATA 6 BLOCK DIAGRAM 7 PINNING 8 FUNCTIONAL DESCRIPTION
8.1 System clock
8.2 Interpolation filter
8.3 Noise shaper
8.4 Filter stream DAC
8.5 Power-on reset
8.6 Feature settings
8.6.1 Digital interface format select
8.6.2 Mute control
8.6.3 De-emphasis control
8.6.4 Power control and sampling frequency select 9 LIMITING VALUES 10 HANDLING 11 THERMAL CHARACTERISTICS 12 QUALITY SPECIFICATION
13 DC CHARACTERISTICS 14 AC CHARACTERISTICS
14.1 2.0 V supply voltage
14.2 3.0 V supply voltage
14.3 Timing 15 APPLICATION INFORMATION 16 PACKAGE OUTLINE 17 SOLDERING
17.1 Introduction to soldering surface mount packages
17.2 Reflow soldering
17.3 Wave soldering
17.4 Manual soldering
17.5 Suitability of surface mount IC packages for wave and reflow soldering methods
18 DATA SHEET STATUS 19 DEFINITIONS 20 DISCLAIMERS
Philips Semiconductors Product specification
Low power audio DAC UDA1334BTS

1 FEATURES

1.1 General

• 1.8 to 3.6 V power supply voltage
• Integrated digital filter plus DAC
• Supports sample frequencies from 8 to 100 kHz
• Automatic system clock versus sample rate detection
• Low power consumption
• No analog post filtering required for DAC
• Slave mode only applications
• Easy application
• SSOP16 package.

2 APPLICATIONS

This audio DAC is excellently suitable for digital audio portable application, such as portable MD, MP3 and DVD players.

1.2 Multiple format data interface

• I2S-bus and LSB-justified format compatible
• 1fs input data rate.

1.3 DAC digital sound processing

• Digital de-emphasis for 44.1 kHz sampling rate
• Mute function.
1.4 Advanced audio configuration
• High linearity, wide dynamic range and low distortion
• Standby or Sleep mode in which the DAC is powered
down.

4 ORDERING INFORMATION

TYPE
NUMBER
UDA1334BTS SSOP16 plastic shrink small outline package; 16 leads; body width 4.4 mm SOT369-1
NAME DESCRIPTION VERSION

3 GENERAL DESCRIPTION

The UDA1334BTS supports the I2S-bus data format with word lengths of up to 24 bits and the LSB-justified serial data format with word lengths of 16, 20 and 24 bits.
The UDA1334BTS has basic features such as de-emphasis (at 44.1 kHz sampling rate) and mute.
PACKAGE
Philips Semiconductors Product specification
Low power audio DAC UDA1334BTS

5 QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies
V
DDA
V
DDD
I
DDA
I
DDD
T
amb
Digital-to-analog converter (V
V
o(rms)
(THD + N)/S total harmonic
S/N signal-to-noise ratio f
α
cs
Digital-to-analog converter (V
V
o(rms)
(THD + N)/S total harmonic
S/N signal-to-noise ratio f
α
cs
Power dissipation (at fs= 44.1 kHz)
DAC analog supply voltage 1.8 2.0 3.6 V digital supply voltage 1.8 2.0 3.6 V DAC analog supply current normal operating mode − 2.3 − mA
Sleep mode − 125 −µA
digital supply current normal operating mode − 1.4 − mA
Sleep mode
clock running − 250 −µA no clock running − 20 −µA
ambient temperature −40 − +85 °C
DDA=VDDD
= 2.0 V)
output voltage (RMS value) at 0 dB (FS) digital input; note 1 − 600 − mV
= 44.1 kHz; at 0 dB −−80 − dB
f
s
distortion-plus-noise to signal ratio
f
= 44.1 kHz; at −60 dB; A-weighted −−37 − dB
s
= 96 kHz; at 0 dB −−75 − dB
f
s
f
= 96 kHz; at −60 dB; A-weighted −−35 − dB
s
= 44.1 kHz; code = 0; A-weighted − 97 − dB
s
= 96 kHz; code = 0; A-weighted − 95 − dB
f
s
channel separation − 100 − dB
DDA=VDDD
= 3.0 V)
output voltage (RMS value) at 0 dB (FS) digital input; note 1 − 900 − mV
f
= 44.1 kHz; at 0 dB −−90 − dB
s
distortion-plus-noise to signal ratio
f
= 44.1 kHz; at −60 dB; A-weighted −−40 − dB
s
f
= 96 kHz; at 0 dB −−85 − dB
s
= 96 kHz; at −60 dB; A-weighted −−37 − dB
f
s
= 44.1 kHz; code = 0; A-weighted − 100 − dB
s
f
= 96 kHz; code = 0; A-weighted − 98 − dB
s
channel separation − 100 − dB
P power dissipation playback mode
at 2.0 V supply voltage − 7.4 − mW at 3.0 V supply voltage − 17 − mW
Sleep mode; at 2.0 V supply voltage
clock running − 0.75 − mW no clock running − 0.3 − mW
Note
1. The DAC output voltage scales proportionally to the power supply voltage.
Philips Semiconductors Product specification
Low power audio DAC UDA1334BTS

6 BLOCK DIAGRAM

handbook, full pagewidth
BCK
WS
DATAI
SYSCLK
MUTE
DEEM
PCS
VOUTL
V
DDD
4
1 2 3
UDA1334BTS
6 8 9 10
14
13 12
V
DDA
DIGITAL INTERFACE
DE-EMPHASIS
INTERPOLATION FILTER
NOISE SHAPER
DAC
15
V
SSA
V
DAC
SSD
5
7
SFOR1
11
SFOR0
16
VOUTR
MGL964
V
ref(DAC)
Fig.1 Block diagram.
Philips Semiconductors Product specification
Low power audio DAC UDA1334BTS

7 PINNING

SYMBOL PIN PAD TYPE DESCRIPTION
BCK 1 5 V tolerant digital input pad; note 1 bit clock input WS 2 5 V tolerant digital input pad; note 1 word select input DATAI 3 5 V tolerant digital input pad; note 1 serial data input V
DDD
V
SSD
SYSCLK 6 5 V tolerant digital input pad; note 1 system clock input SFOR1 7 5 V tolerant digital input pad; note 1 serial format select 1 MUTE 8 5 V tolerant digital input pad; note 1 mute control DEEM 9 5 V tolerant digital input pad; note 1 de-emphasis control PCS 10 3-level input pad; note 2 power control and sampling frequency select SFOR0 11 digital input pad; note 2 serial format select 0 V
ref(DAC)
V
DDA
VOUTL 14 analog output pad DAC output left V
SSA
VOUTR 16 analog output pad DAC output right
4 digital supply pad digital supply voltage 5 digital ground pad digital ground
12 analog pad DAC reference voltage 13 analog supply pad DAC analog supply voltage
15 analog ground pad DAC analog ground
Notes
1. 5 V tolerantis only supported if the power supply voltage is between 2.7 and 3.6 V. For lower power supply voltages this is maximum 3.3 V tolerant.
2. Because of test issues these pads are not 5 V tolerant and they should be at power supply voltage level or at a maximum of 0.5 V above that level.
handbook, halfpage
BCK
WS
DATAI
V
DDD
V
SSD
1 2 3 4
UDA1334BTS
5 6 7 8
MGL963
16 15 14 13 12 11 10
9
VOUTR V
SSA
VOUTL V
DDA
V
ref(DAC)
SFOR0SYSCLK PCSSFOR1 DEEMMUTE
Fig.2 Pin configuration.
Philips Semiconductors Product specification
Low power audio DAC UDA1334BTS

8 FUNCTIONAL DESCRIPTION

8.1 System clock

The UDA1334BTS operates in slave mode only; this means that in all applications the system must provide the system clock and the digital audio interface signals (BCK and WS).
Thesystemclockmustbelocked in frequency to the digital interface signals.
TheUDA1334BTSautomaticallydetectstheratiobetween the SYSCLK and WS frequencies.
The BCK clock can be up to 64fs, or in other words the BCK frequency is 64 times the Word Select (WS) frequency or less: f
≤ 64 × fWS.
BCK
Remarks:
1. The WS edge MUST fall on the negative edge of the BCK at all times for proper operation of the digital I/O data interface
2. For LSB-justified formats it is important to have a WS signal with a duty factor of 50%.
The modes which are supported are given in Table 1.
Table 1 Supported sampling ranges
CLOCK MODE SAMPLING RANGE
768f 512f 384f 256f 192f 128f
s s s s s s
8to55kHz 8 to 100 kHz 8 to 100 kHz 8 to 100 kHz
8 to 100 kHz
8 to 100 kHz
(1)(2)
(2)
Notes
1. This mode can only be supported for power supply voltages down to 2.4 V. For lower voltages, in 192fsmode the sampling frequency should be limited to 55 kHz.
2. Not supported in the low sampling frequency mode.
Table 2 Example using a 12.228 MHz system clock
CLOCK MODE SAMPLING FREQUENCY
128f 192f 256f 384f 512f 768f
s s s s s s
96 kHz
64 kHz
48 kHz 32 kHz 24 kHz 16 kHz
(1)
Note
1. This mode can only be supported for power supply voltages down to 2.4 V. For lower voltages, in 192f mode the sampling frequency should be limited to 55 kHz.
8.2 Interpolation filter
The interpolation digital filter interpolates from 1fsto 64f by cascading FIR filters (see Table 3).
Table 3 Interpolation filter characteristics
ITEM CONDITION VALUE (dB)
Pass-band ripple 0 to 0.45f Stop band >0.55f Dynamic range 0 to 0.45f
s
s
s
±0.02
−50
>114

8.3 Noise shaper

The 5th-order noise shaper operates at 64f
. It shifts
s
in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog signal using a Filter Stream DAC (FSDAC).
s
s
An example is given in Table 2 for a 12.228 MHz system clock input.
Philips Semiconductors Product specification
Low power audio DAC UDA1334BTS

8.4 Filter stream DAC

The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. No post-filter is needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output.
The output voltage of the FSDAC scales proportionally with the power supply voltage.
handbook, halfpage
3.0 V
V
V
ref(DAC)
DDA
13
50 kΩ
RESET
12
CIRCUIT

8.5 Power-on reset

The UDA1334BTS has an internal Power-on reset circuit (see Fig.3) which resets the test control block.
The reset time (see Fig.4) is determined by an external capacitor which is connected between pin V
ref(DAC)
and ground. The reset time should be at least 1 µs for V
ref(DAC)
will be reset again for V
< 1.25 V. When V
ref(DAC)
is switched off, the device
DDA
< 0.75 V.
During the reset time the system clock should be running.
3.0
handbook, halfpage
V
DDD (V)
1.5
V
0
3.0
DDA (V)
1.5
t
C1 > 10 µF
50 kΩ
UDA1334BTS
MGL985
Fig.3 Power-on reset circuit.
V
ref(DAC)
(V)
1.25
0.75
3.0
1.5
0
0
>1 µs
Fig.4 Power-on reset timing.
t
t
MGL984
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