Philips UDA1330ATS-N2, UDA1330ATS-N1 Datasheet

INTEGRATED CIRCUITS

DATA SHEET

UDA1330ATS

Low-cost stereo filter DAC

Preliminary specification

2000 Apr 18

Supersedes data of 1999 Dec 20

File under Integrated Circuits, IC01

Philips Semiconductors	Preliminary specification
Low-cost stereo filter DAC	UDA1330ATS

FEATURES

General

∙Low power consumption

∙Power supply voltage from 2.7 to 5.5 V

∙Selectable control via L3 microcontroller interface or via static pin control

∙System clock frequencies of 256fs, 384fs and 512fs selectable via L3 interface or 256fs and 384fs via static pin control

∙Supports sampling frequencies (fs) from 16 to 55 kHz

∙Integrated digital filter plus non inverting Digital-to-Analog Converter (DAC)

∙No analog post filtering required for DAC

∙Slave mode only applications

∙Easy application

∙Small package size (SSOP16)

∙TTL tolerant input pads

∙Pin and function compatible with the UDA1320ATS.

Multiple format input interface

∙L3 mode: I2S-bus, MSB-justified or LSB-justified 16, 18 and 20 bits format compatible

∙Static pin mode: I2S-bus and LSB-justified 16, 18 and 20 bits format compatible

∙1fs input format data rate.

DAC digital sound processing

∙Digital logarithmic volume control in L3 mode

∙Digital de-emphasis for 32, 44.1 and 48 kHz sampling frequencies in L3 mode or 44.1 kHz sampling frequency in static pin mode

∙Soft mute control both in static pin mode and L3 mode.

Advanced audio configuration

∙Stereo line output (volume control in L3 mode)

∙High linearity, wide dynamic range and low distortion.

ORDERING INFORMATION

APPLICATIONS

∙PC audio applications

∙Car radio applications.

GENERAL DESCRIPTION

The UDA1330ATS is a single-chip stereo DAC employing bitstream conversion techniques.

The UDA1330ATS supports the I2S-bus data format with word lengths of up to 20 bits, the MSB-justified data format with word lengths of up to 20 bits and the LSB-justified serial data format with word lengths of 16, 18 and 20 bits.

The UDA1330ATS can be used in two modes: L3 mode or the static pin mode.

In the L3 mode, all digital sound processing features must be controlled via the L3 interface, including the selection of the system clock setting.

In the two static modes, the UDA1330ATS can be operated in the 256fs and 384fs system clock mode. Muting, de-emphasis for 44.1 kHz and four digital input formats (I2S-bus or LSB-justified 16, 18, and 20 bits) can be selected via static pins. The L3 interface cannot be used in this application mode, so volume control is not available in this mode.

	TYPE NUMBER		PACKAGE
		NAME	DESCRIPTION	VERSION
	UDA1330ATS	SSOP16	plastic shrink small outline package; 16 leads; body width 4.4 mm	SOT369-1

2000 Apr 18

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Philips Semiconductors				Preliminary specification
Low-cost stereo filter DAC				UDA1330ATS
QUICK REFERENCE DATA
SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
Supplies
VDDA	DAC analog supply voltage		2.7	5.0	5.5	V
VDDD	digital supply voltage		2.7	5.0	5.5	V
IDDA	DAC analog supply current	VDDA = 5.0 V
		operating	−	9.5	−	mA
		power-down	−	400	−	μA
		VDDA = 3.3 V
		operating	−	7.0	−	mA
		power-down	−	250	−	μA
IDDD	digital supply current	VDDD = 5.0 V	−	5.5	−	mA
		VDDD = 3.3 V	−	3.0	−	mA
Tamb	ambient temperature		−40	−	+85	°C
Digital-to-analog converter (VDDA = VDDD = 5.0 V)
Vo(rms)	output voltage (RMS value)	note 1	−	1.45	−	V
(THD + N)/S	total harmonic distortion-plus-noise to	at 0 dB	−	−90	−85	dB
	signal ratio
		at −60 dB; A-weighted	−	−40	−35	dB
S/N	signal-to-noise ratio	code = 0; A-weighted	−	+100	−95	dB
αcs	channel separation		−	100	−	dB
Digital-to-analog converter (VDDA = VDDD = 3.3 V)
Vo(rms)	output voltage (RMS value)	note 1	−	1.0	−	V
(THD + N)/S	total harmonic distortion-plus-noise to	at 0 dB	−	−85	−	dB
	signal ratio
		at −60 dB; A-weighted	−	−38	−	dB
S/N	signal-to-noise ratio	code = 0; A-weighted	−	100	−	dB
αcs	channel separation		−	100	−	dB
Power dissipation
P	power dissipation	playback mode
		VDDA = VDDD = 5.0 V	−	75	−	mW
		VDDA = VDDD = 3.3 V	−	33	−	mW

Note

1. The output voltage scales linearly with the power supply voltage.

2000 Apr 18

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Philips Semiconductors	Preliminary specification
Low-cost stereo filter DAC	UDA1330ATS

	BLOCK DIAGRAM
	handbook, full pagewidth	VDDD		VSSD
		4		5
		1				7	APPSEL
						11
	BCK						APPL0
		2			CONTROL	10
	WS		DIGITAL INTERFACE				APPL1
		3
					INTERFACE	9
	DATAI						APPL2
						8
							APPL3
		UDA1330ATS	VOLUME/MUTE/DE-EMPHASIS
	SYSCLK	6	INTERPOLATION FILTER
				NOISE SHAPER
	VOUTL	14	DAC	DAC		16	VOUTR
		13		15	12		MGL401
		VDDA		VSSA	Vref(DAC)

Fig.1 Block diagram.

PINNING
SYMBOL	PIN	DESCRIPTION
BCK	1	bit clock input
WS	2	word select input		handbook, halfpage
DATAI	3	data input
				BCK	1		16	VOUTR
VDDD	4	digital supply voltage		WS	2		15	VSSA
VSSD	5	digital ground		DATAI	3		14	VOUTL
SYSCLK	6	system clock input: 256fs, 384fs		VDDD	4		13	VDDA
		and 512fs				UDA1330ATS
				VSSD	5		12	Vref(DAC)
APPSEL	7	application mode select input
APPL3	8	application input 3		SYSCLK	6		11	APPL0
APPL2	9	application input 2		APPSEL	7		10	APPL1
APPL1	10	application input 1		APPL3	8		9	APPL2
APPL0	11	application input 0
						MGL402
Vref(DAC)	12	DAC reference voltage
VDDA	13	analog supply voltage for DAC
VOUTL	14	left channel output
VSSA	15	analog ground		Fig.2		Pin configuration.
VOUTR	16	right channel output

2000 Apr 18

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Philips Semiconductors	Preliminary specification
Low-cost stereo filter DAC	UDA1330ATS

FUNCTIONAL DESCRIPTION

System clock

The UDA1330ATS operates in slave mode only. Therefore, in all applications the system devices must provide the system clock. The system frequency (fsys) is selectable and depends on the application mode. The options are: 256fs, 384fs and 512fs for the L3 mode and 256fs or 384fs for the static pin mode. The system clock must be locked in frequency to the digital interface input signals.

The UDA1330ATS supports sampling frequencies from 16 to 55 kHz.

Application modes

The application mode can be set with the three-level pin APPSEL (see Table 1):

∙L3 mode

∙Static pin mode with fsys = 384fs

∙Static pin mode with fsys = 256fs.

Table 1 Selecting application mode and system clock frequency via pin APPSEL

	VOLTAGE ON	MODE	fsys
	PIN APPSEL
	VSSD	L3 mode	256fs, 384fs or 512fs
	0.5VDDD	static pin mode	384fs
	VDDD		256fs

The function of an application input pin (active HIGH) depends on the application mode (see Table 2).

Table 2 Functions of application input pins

PIN		FUNCTION
	L3 MODE		STATIC PIN MODE
APPL0	TEST		MUTE
APPL1	L3CLOCK		DEEM
APPL2	L3MODE		SF0
APPL3	L3DATA		SF1

For example, in the static pin mode the output signal can be soft muted by setting pin APPL0 to HIGH. De-emphasis can be switched on for 44.1 kHz by setting pin APPL1 to HIGH; setting pin APPL1 to LOW will disable de-emphasis.

In the L3 mode, pin APPL0 must be set to LOW. It should be noted that when the L3 mode is used, an initialization must be performed when the IC is powered-up.

Multiple format input interface

DATA FORMATS

The digital interface of the UDA1330ATS supports multiple format inputs (see Fig.3).

Left and right data-channel words are time multiplexed.

The WS signal must have a 50% duty factor for all LSB-justified formats.

The BCK clock can be up to 64fs, or in other words the BCK frequency is 64 times the Word Select (WS) frequency or less: fBCK ≤ 64 × fWS.

Important: the WS edge MUST fall on the negative edge of the BCK at all times for proper operation of the digital interface.

The UDA1330ATS also accepts double speed data for double speed data monitoring purposes

L3 MODE

This mode supports the following input formats:

∙I2S-bus format with data word length of up to 20 bits

∙MSB-justified format with data word length up to 20 bits

∙LSB-justified format with data word length of 16, 18 or 20 bits.

STATIC PIN MODE

This mode supports the following input formats:

∙I2S-bus format with data word length of up to 20 bits

∙LSB-justified format with data word length of 16, 18 or 20 bits.

These four formats are selectable via the static pin codes SF0 and SF1 (see Table 3).

Table 3 Input format selection using SF0 and SF1

FORMAT	SF0	SF1
I2S-bus	0	0
LSB-justified 16 bits	0	1
LSB-justified 18 bits	1	0
LSB-justified 20 bits	1	1

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Philips Semiconductors	Preliminary specification
Low-cost stereo filter DAC	UDA1330ATS

Interpolation filter (DAC)

The digital filter interpolates from 1fs to 128fs by cascading a recursive filter and an FIR filter (see Table 4).

Table 4 Interpolation filter characteristics

ITEM	CONDITION	VALUE (dB)
Pass-band ripple	0 to 0.45fs	±0.1
Stop band	>0.55fs	−50
Dynamic range	0 to 0.45fs	108

Noise shaper

The 3rd-order noise shaper operates at 128fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog signal using a Filter Stream DAC (FSDAC).

Filter stream DAC

The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. A post-filter is not needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output.

The output voltage of the FSDAC scales linearly with the power supply voltage.

Pin compatibility

In the L3 mode the UDA1330ATS can be used on boards that are designed for the UDA1320ATS.

Remark: It should be noted that the UDA1330ATS is designed for 5 V operation while the UDA1320ATS is designed for 3 V operation. This means that the UDA1330ATS can be used with the UDA1320ATS supply voltage range, but the UDA1320ATS can not be used with the 5 V supply voltage.

2000 Apr 18

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_

18 Apr 2000

pagewidth full ok,

WS

LEFT

RIGHT

1

2

3

> = 8

1

2

3

> = 8

BCK

DATA

MSB

B2

MSB

B2

MSB

I2S-BUS FORMAT

WS

LEFT

RIGHT

1

2

3

> = 8

1

2

3

> = 8

BCK

DATA MSB

B2

LSB

MSB

B2

LSB MSB

B2

MSB-JUSTIFIED FORMAT

WS

LEFT

RIGHT

16

15

2

1

16

15

2

1

BCK

7

DATA

MSB

B2

B15

LSB

MSB

B2

B15

LSB

LSB-JUSTIFIED FORMAT 16 BITS

WS

LEFT

RIGHT

18

17

16

15

2

1

18

17

16

15

2

1

BCK

DATA

MSB

B2

B3

B4

B17

LSB

MSB

B2

B3

B4

B17

LSB

LSB-JUSTIFIED FORMAT 18 BITS

WS

LEFT

RIGHT

20

19

18

17

16

15

2

1

20

19

18

17

16

15

2

1

BCK

DATA

MSB B2

B3

B4

B5

B6

B19

LSB

MSB

B2

B3

B4

B5

B6

B19

LSB

LSB-JUSTIFIED FORMAT 20 BITS

MBL140

Fig.3 Digital interface input format data format.

DAC filter stereo cost-Low

UDA1330ATS

Semiconductors Philips

specification Preliminary

Philips Semiconductors	Preliminary specification
Low-cost stereo filter DAC	UDA1330ATS

L3 INTERFACE

The following system and digital sound processing features can be controlled in the L3 mode of the UDA1330ATS:

∙System clock frequency

∙Data input format

∙De-emphasis for 32, 44.1 and 48 kHz

∙Volume

∙Soft mute.

The exchange of data and control information between the microcontroller and the UDA1330ATS is accomplished through a serial interface comprising the following signals:

∙L3DATA

∙L3MODE

∙L3CLOCK.

Information transfer through the microcontroller bus is organized in accordance with the L3 interface format, in which two different modes of operation can be distinguished: address mode and data transfer mode.

Address mode

The address mode (see Fig.4) is required to select a device communicating via the L3 interface and to define the destination registers for the data transfer mode.

Data bits 7 to 2 represent a 6-bit device address where bit 7 is the MSB. The address of the UDA1330ATS is 000101 (bit 7 to bit 2). If the UDA1330ATS receives a different address, it will deselect its microcontroller interface logic.

Data transfer mode

The selected address remains active during subsequent data transfers until the UDA1330ATS receives a new address command.

The fundamental timing of data transfers (see Fig.5) is essentially the same as the address mode. The maximum input clock frequency and data rate is 64fs.

Data transfer can only be in one direction, consisting of input to the UDA1330ATS to program sound processing and other functional features. All data transfers are by 8-bit bytes. Data will be stored in the UDA1330ATS after reception of a complete byte.

A multibyte transfer is illustrated in Fig.6.

Registers

The sound processing and other feature values are stored in independent registers. The first selection of the registers is achieved by the choice of data type that is transferred. This is performed in the address mode using bit 1 and bit 0 (see Table 5).

Table 5 Selection of data transfer

BIT 1	BIT 0	TRANSFER
0	0	data (volume, de-emphasis, mute)
0	1	not used
1	0	status (system clock frequency,
		data input format)
1	1	not used

The second selection is performed by the 2 MSBs of the data byte (bit 7 and bit 6). The other bits in the data byte (bit 5 to bit 0) represent the value that is placed in the selected registers.

The ‘status’ settings are given in Table 6 and the ‘data’ settings are given in Table 7.

2000 Apr 18

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