INTEGRATED CIRCUITS
DATA SHEET
UDA1324TS
Ultra low-voltage stereo filter DAC
Preliminary specification |
2000 Jan 20 |
Supersedes data of 1999 Oct 12
File under Integrated Circuits, IC01
Philips Semiconductors |
Preliminary specification |
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Ultra low-voltage stereo filter DAC |
UDA1324TS |
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FEATURES
General
∙Low power consumption
∙Ultra low power supply voltage from 1.9 to 2.7 V
∙Selectable control via L3 microcontroller interface or via static pin control
∙System clock frequencies of 256fs, 384fs and 512fs selectable via L3 interface or 256fs and 384fs via static pin control
∙Supports sampling frequencies (fs) from 16 to 48 kHz
∙Integrated digital filter plus non inverting Digital-to-Analog Converter (DAC)
∙No analog post filtering required for DAC
∙Slave mode only applications
∙Easy application
∙Small package size (SSOP16).
Multiple format input interface
∙L3 mode: I2S-bus, MSB-justified or LSB-justified 16, 18 and 20 bits format compatible
∙Static pin mode: I2S-bus or LSB-justified 16, 18 and 20 bits format compatible
∙1fs input format data rate.
DAC digital sound processing
∙Digital logarithmic volume control in L3 mode
∙Digital de-emphasis selection for 32, 44.1 and 48 kHz sampling frequencies in L3 mode or 44.1 kHz sampling frequency in static pin mode
∙Soft mute control in static pin mode or in L3 mode.
Advanced audio configuration
∙Stereo line output (volume control in L3 mode)
∙High linearity, wide dynamic range and low distortion.
ORDERING INFORMATION
APPLICATIONS
∙ Portable digital audio equipment.
GENERAL DESCRIPTION
The UDA1324TS is a single-chip stereo DAC employing bitstream conversion techniques. The ultra low-voltage requirements make the device eminently suitable for use in portable digital audio equipment which incorporates playback functions.
The UDA1324TS supports the I2S-bus data format with word lengths of up to 20 bits, the MSB-justified data format with word lengths of up to 20 bits and the LSB-justified serial data format with word lengths of 16, 18 and 20 bits.
The UDA1324TS can be used in two modes: L3 mode or static pin mode.
In the L3 mode, all digital sound processing features must be controlled via the L3 interface, including the selection of the system clock setting.
In the two static modes, the UDA1324TS can be operated in the 256fs and 384fs system clock mode. Muting, de-emphasis for 44.1 kHz and four digital input formats (I2S-bus or LSB-justified 16, 18 and 20 bits) can be selected via static pins. The L3 interface cannot be used in this application mode, so volume control is not available in this mode.
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NUMBER |
NAME |
DESCRIPTION |
VERSION |
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UDA1324TS |
SSOP16 |
plastic shrink small outline package; 16 leads; body width 4.4 mm |
SOT369-1 |
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2000 Jan 20 |
2 |
Philips Semiconductors |
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Preliminary specification |
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Ultra low-voltage stereo filter DAC |
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UDA1324TS |
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QUICK REFERENCE DATA |
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SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
TYP. |
MAX. |
UNIT |
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Supplies |
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VDDA |
analog supply voltage |
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1.9 |
2.0 |
2.7 |
V |
VDDD |
digital supply voltage |
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1.9 |
2.0 |
2.7 |
V |
IDDA |
analog supply current |
VDDA = 2.0 V |
− |
3.0 |
− |
mA |
IDDD |
digital supply current |
VDDD = 2.0 V |
− |
1.5 |
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mA |
DAC; note 1 |
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Vo(rms) |
output voltage (RMS value) |
note 2 |
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500 |
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mV |
(THD + N)/S |
total harmonic distortion-plus-noise to |
at 0 dB |
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−83 |
−78 |
dB |
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signal ratio |
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at −60 dB; A-weighted |
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−36 |
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dB |
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S/N |
signal-to-noise ratio |
code = 0; A-weighted |
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97 |
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dB |
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αcs |
channel separation |
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100 |
− |
dB |
T |
ambient temperature |
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−40 |
− |
+70 |
°C |
amb |
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Notes |
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1.The analog performance figures are measured at 2.0 V supply voltage.
2.The DAC output voltage scales linearly with the power supply voltage.
BLOCK DIAGRAM
handbook, full pagewidth |
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VDDD |
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VSSD |
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4 |
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1 |
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7 |
APPSEL |
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11 |
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BCK |
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APPL0 |
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2 |
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CONTROL |
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WS |
DIGITAL INTERFACE |
APPL1 |
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DATAI |
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INTERFACE |
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APPL2 |
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APPL3 |
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UDA1324TS |
VOLUME/MUTE/DE-EMPHASIS |
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SYSCLK |
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INTERPOLATION FILTER |
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NOISE SHAPER |
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VOUTL |
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DAC |
DAC |
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VOUTR |
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12 |
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MBK770 |
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VDDA |
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VSSA |
Vref(DAC) |
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Fig.1 Block diagram.
2000 Jan 20 |
3 |
Philips Semiconductors |
Preliminary specification |
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Ultra low-voltage stereo filter DAC |
UDA1324TS |
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PINNING
SYMBOL |
PIN |
DESCRIPTION |
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BCK |
1 |
bit clock input |
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WS |
2 |
word select input |
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DATAI |
3 |
data input |
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VDDD |
4 |
digital supply voltage |
VSSD |
5 |
digital ground |
SYSCLK |
6 |
system clock input: 256fs, 384fs |
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and 512fs |
APPSEL |
7 |
application mode select input |
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APPL3 |
8 |
application input pin 3 |
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APPL2 |
9 |
application input pin 2 |
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APPL1 |
10 |
application input pin 1 |
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APPL0 |
11 |
application input pin 0 |
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Vref(DAC) |
12 |
DAC reference voltage |
VDDA |
13 |
analog supply voltage for DAC |
VOUTL |
14 |
left channel output |
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VSSA |
15 |
analog ground for DAC |
VOUTR |
16 |
right channel output |
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handbook, halfpage |
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BCK |
1 |
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16 |
VOUTR |
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WS |
2 |
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15 |
VSSA |
DATAI |
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VOUTL |
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VDDD |
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VDDA |
4 |
UDA1324TS |
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VSSD |
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Vref(DAC) |
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12 |
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SYSCLK |
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11 |
APPL0 |
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APPSEL |
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10 |
APPL1 |
APPL3 |
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APPL2 |
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9 |
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MBK769 |
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Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
System clock
The UDA1324TS operates in the slave mode only. Therefore, in all applications the system devices must provide the system clock. The system frequency (fsys) is selectable and depends on the application mode.
The options are: 256fs, 384fs and 512fs for the L3 mode and 256fs or 384fs for the static pin mode. The system clock must be locked in frequency to the digital interface input signals.
The UDA1324TS supports sampling frequencies (fs) from 16 to 48 kHz.
Application modes
The application mode can be set with the three-level pin APPSEL (see Table 1):
∙L3 mode
∙Static pin mode with fsys = 384fs
∙Static pin mode with fsys = 256fs.
Table 1 Selecting application mode and system clock frequency via pin APPSEL
VOLTAGE ON |
MODE |
fsys |
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PIN APPSEL |
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VSSD |
L3 mode |
256fs, 384fs or 512fs |
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0.5VDDD |
static pin mode |
384fs |
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VDDD |
256fs |
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The function of an application input pin (active HIGH) depends on the application mode (see Table 2).
Table 2 Functions of application input pins
PIN |
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FUNCTION |
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L3 MODE |
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STATIC PIN MODE |
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APPL0 |
TEST |
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MUTE |
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APPL1 |
L3CLOCK |
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DEEM |
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APPL2 |
L3MODE |
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SF0 |
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APPL3 |
L3DATA |
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SF1 |
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For example, in the static pin mode the output signal can be soft muted by setting pin APPL0 to HIGH. De-emphasis can be switched on for 44.1 kHz by setting pin APPL1 to HIGH; setting pin APPL1 to LOW will disable de-emphasis.
2000 Jan 20 |
4 |
Philips Semiconductors |
Preliminary specification |
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Ultra low-voltage stereo filter DAC |
UDA1324TS |
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In the L3 mode, pin APPL0 must be set to LOW. It should be noted that when the L3 mode is used, an initialization must be performed when the IC is powered-up.
Digital interface
DATA FORMATS
The digital interface of the UDA1324TS supports multiple format inputs (see Fig.3).
Left and right data-channel words are time multiplexed.
The WS signal must have a 50% duty factor for all LSB-justified formats.
The BCK clock can be up to 64fs, or in other words the BCK frequency is 64 times the Word Select (WS) frequency or less: fBCK ≤ 64 × fWS.
Important: the WS edge MUST fall on the negative edge of the BCK at all times for proper operation of the digital interface.
The UDA1324TS also accepts double speed data for double speed data monitoring purposes.
L3 MODE
∙I2S-bus format with data word length of up to 20 bits
∙MSB-justified format with data word length up to 20 bits
∙LSB-justified format with data word length of 16, 18 or 20 bits.
STATIC PIN MODE
∙I2S-bus format with data word length of up to 20 bits
∙LSB-justified format with data word length of 16, 18 or 20 bits.
These four formats are selectable via the static pin codes SF0 and SF1 (see Table 3).
Table 3 Input format selection using SF0 and SF1
FORMAT |
SF0 |
SF1 |
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I2S-bus |
0 |
0 |
LSB-justified 16 bits |
0 |
1 |
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LSB-justified 18 bits |
1 |
0 |
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LSB-justified 20 bits |
1 |
1 |
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Interpolation filter
The digital filter interpolates from 1fs to 128fs by cascading a recursive filter and a FIR filter (see Table 4).
Table 4 Interpolation filter characteristics
ITEM |
CONDITION |
VALUE (dB) |
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Pass-band ripple |
0 to 0.45fs |
±0.1 |
Stop band |
>0.55fs |
−50 |
Dynamic range |
0 to 0.45fs |
108 |
Noise shaper
The 3rd-order noise shaper operates at 128fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog signal using a Filter Stream Digital-to-Analog Converter (FSDAC).
Filter stream DAC
The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. A post filter is not needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage capable of driving a line output.
The output voltage of the FSDAC scales linearly with the power supply voltage.
2000 Jan 20 |
5 |
_
20 Jan 2000
6
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full ndbook, |
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WS |
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LEFT |
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RIGHT |
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BCK |
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3 |
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> = 8 1 |
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3 |
pagewidth |
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DATA |
MSB |
B2 |
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MSB |
B2 |
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MSB |
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I2S-BUS FORMAT |
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WS |
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LEFT |
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RIGHT |
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1 |
2 |
3 |
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> = 8 |
1 |
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2 |
3 |
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> = 8 |
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BCK |
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DATA MSB |
B2 |
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LSB |
MSB |
B2 |
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LSB |
MSB B2 |
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MSB-JUSTIFIED FORMAT |
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WS |
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LEFT |
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RIGHT |
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16 |
15 |
2 |
1 |
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16 |
15 |
2 |
1 |
BCK |
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DATA |
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MSB |
B2 |
B15 |
LSB |
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MSB |
B2 |
B15 |
LSB |
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LSB-JUSTIFIED FORMAT 16 BITS |
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WS |
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LEFT |
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RIGHT |
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18 |
17 |
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16 |
15 |
2 |
1 |
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18 |
17 |
16 |
15 |
2 |
1 |
BCK |
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DATA |
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MSB |
B2 |
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B3 |
B4 |
B17 |
LSB |
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MSB |
B2 |
B3 |
B4 |
B17 |
LSB |
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WS |
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LEFT |
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RIGHT |
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20 |
19 |
18 |
17 |
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16 |
15 |
2 |
1 |
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20 |
19 |
18 |
17 |
16 |
15 |
2 |
1 |
BCK |
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DATA |
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MSB |
B2 |
B3 |
B4 |
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B5 |
B6 |
B19 |
LSB |
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MSB |
B2 |
B3 |
B4 |
B5 |
B6 |
B19 |
LSB |
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LSB-JUSTIFIED FORMAT 20 BITS |
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WS |
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LEFT |
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24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
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16 |
15 |
2 |
1 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
2 |
1 |
BCK |
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DATA |
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MSB |
B2 |
B3 |
B4 |
B5 |
B6 |
B7 |
B8 |
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B9 |
B10 |
B23 |
LSB |
MSB |
B2 |
B3 |
B4 |
B5 |
B6 |
B7 |
B8 |
B9 |
B10 |
B23 |
LSB |
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LSB-JUSTIFIED FORMAT 24 BITS |
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MBL121 |
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Fig.3 Digital interface input data formats.
DAC filter stereo voltage-low Ultra
UDA1324TS
Semiconductors Philips
specification Preliminary
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