Philips UDA1324TS Datasheet

INTEGRATED CIRCUITS

DATA SH EET

UDA1324TS

Ultra low-voltage stereo filter DAC

Preliminary specification
Supersedes data of 1998 Oct 02
File under Integrated Circuits, IC01

1999 Oct 12

Philips Semiconductors Preliminary specification

Ultra low-voltage stereo filter DAC UDA1324TS

FEATURES
General

• Low power consumption

• Ultra low power supply voltage 1.9 to 2.7 V

• Selectable controlvia L3 microcontroller interface or via

static pin control.

• 256, 384 and 512fs system clock (f
the L3 interface or 256 and 384fs clock mode via static
pin control

• Supports sampling frequencies from 16 to 48 kHz.

• Integrated digital filter plus non inverting

Digital-to-Analog Converter (DAC)

• No analog post filtering required for DAC

• Slave mode only applications

• Easy application

• Small package size (SSOP16).

Multiple format input interface

• I2S-bus, MSB-justified and LSB-justified
16, 18 and 20 bits format compatible (in L3-mode)

• I2S-bus and LSB-justified 16, 18 and 20 bits format
compatible

• 1fs input format data rate.

DAC digital sound processing

• Digital logarithmic volume control via L3

• Digital de-emphasis for 32, 44.1 and 48 kHz fs via

L3 or 44.1 kHz fs via static pin control

• Soft mute via static pin control or via L3 interface.

Advanced audio configuration

• Stereo line output (under L3 volume control)

• High linearity, wide dynamic range, low distortion.

), selectable via

sys

APPLICATIONS

• Portable digital audio equipment, see Fig.8.

GENERAL DESCRIPTION

The UDA1324TS is a single-chip stereo DAC employing
bitstream conversion techniques. The ultra low voltage
requirements make the device eminently suitable for use
in portable digital audio equipment which incorporates
playback functions.

The UDA1324TS supports the I2S-bus data format with
wordlengths of upto20 bits, the MSB-justified dataformat
with word lengths of up to 20 bits and the LSB-justified
serial data format with word lengths of 16, 18 and 20 bits.

The UDA1324TS can be used in two modes, either
L3-mode or static pin mode.

In the L3-mode, all digital soundprocessing features must
becontrolled via the L3 interface, includingtheselectionof
the system clock setting.

In the two static-modes, the UDA1324TS can be operated
in the 256fs and 384fs system clock mode. The mute,
de-emphasis for 44.1 kHz and 4 digital input formats
(I2S-bus, 16, 18 and 20 bits LSB formats) canbeselected
via static pins. The L3 interface cannot be used in this
application mode, volume control is also not available in
this mode.

ORDERING INFORMATION

TYPE

NUMBER

UDA1324TS SSOP16 plastic shrink small outline package; 16 leads; body width 4.4 mm SOT369-1

1999 Oct 12 2

NAME DESCRIPTION VERSION

PACKAGE

Philips Semiconductors Preliminary specification

Ultra low-voltage stereo filter DAC UDA1324TS

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

DDA

V

DDD

I

DDA

I

DDD

DAC; note 1
V

o(rms)

(THD + N)/S total harmonic distortion plus

S/N signal-to-noise ratio code = 0; A-weighted − 97 − dB

α

cs

T

amb

analog supply voltage 1.9 2.0 2.7 V
digital supply voltage 1.9 2.0 2.7 V
analog supply current for DAC note 1 − 4.0 − mA
digital supply current note 1 − 1.5 − mA

output voltage (RMS value) note 2 − 500 − mV

at 0 dB −−83 −78 dB

noise-to-signal ratio

at −60 dB; A-weighted −−36 − dB

channel separation − 100 − dB
operating ambient temperature −20 − +70

°

C

Notes

1. The analog performance figures and supply currents are given assuming a 2.0 V supply voltage.

2. The DAC output voltage scales linearly with the power supply voltage.

BLOCK DIAGRAM

handbook, full pagewidth

BCK

WS

DATAI

SYSCLK

1
2
3

UDA1324TS

6

V

DDD

4

DIGITAL INTERFACE

VOLUME/MUTE/DE-EMPHASIS

INTERPOLATION FILTER

NOISE SHAPER

V

SSD

5

CONTROL

INTERFACE

7

APPSEL

11

APPL0

10

APPL1

9

APPL2

8

APPL3

VOUTL

14

13 12

V

DDA

DAC

V

Fig.1 Block diagram.

1999 Oct 12 3

SSA

DAC

15

V

ref(DAC)

16

VOUTR

MBK770

Philips Semiconductors Preliminary specification

Ultra low-voltage stereo filter DAC UDA1324TS

PINNING

SYMBOL PIN DESCRIPTION

BCK 1 bit clock
WS 2 word select
DATAI 3 data input
V
V

DDD
SSD

4 digital power supply

5 digital ground
SYSCLK 6 system clock: 256, 384 and 512f
APPSEL 7 application mode select
APPL3 8 application pin 3
APPL2 9 application pin 2
APPL1 10 application pin 1
APPL0 11 application pin 0
V

ref(DAC)

V

DDA

12 DAC reference voltage

13 analog supply voltage
VOUTL 14 left channel output voltage
V

SSA

15 analog ground
VOUTR 16 right channel output voltage

s

handbook, halfpage

BCK

1
2

WS

DATAI

3

V

4

V

DDD

SSD

UDA1324TS

5
6
7
8

MBK769

Fig.2 Pin configuration.

16
15
14
13
12
11
10

9

VOUTR
V

SSA

VOUTL
V

DDA

V

ref(DAC)

APPL0SYSCLK
APPL1APPSEL
APPL2APPL3

FUNCTIONAL DESCRIPTION
System clock

The UDA1324TS operates in slave mode only. In all
applications, therefore, the system devices must provide
the system clock. The system frequency is selectable and
depends on the mode of operation.

The options are 256, 384 and 512fs for the L3 mode and
256fs plus 384fs for the static mode. The system clock
must be locked in frequency to the digital interface input
signals.

The UDA1324TS supports sampling frequencies from
16 to 48 kHz.

Application modes

Operation can be set with the tri-value APPSEL pin, to
L3 mode(APPSEL = V
(APPSEL = 0.5V

DDD

)orto either of two staticmodes

SSD

or APPSEL = V

). See Table 1 for

DDD

APPL0 to APPL3 pin functions (active = HIGH).

Table 1 Selection modes via APPSEL

APPSEL

PIN

V

SSD

0.5V
(384fs)

DDD

V

DDD

(256fs)

APPL0 TEST MUTE MUTE
APPL1 L3CLK DEEM DEEM
APPL2 L3MODE SF0 SF0
APPL3 L3DATA SF1 SF1

For example, in the static pin control mode, the output
signal can be soft muted by setting APPL0 HIGH.
De-emphasis can be switched on for 44.1 kHz by setting
APPL1 HIGH. APPL1 LOW will disable de-emphasis.

It should be noted that when the L3 interface is used, an
L3initialization must beperformedwhen the ICispowered
up. In the L3 mode, the APPL0 pin must be set LOW.

1999 Oct 12 4

Philips Semiconductors Preliminary specification

Ultra low-voltage stereo filter DAC UDA1324TS

Multiple format input interface

L3 MODE:

• I2S-bus with data word length of up to 20 bits

• MSB-justified format with data word length up to 20 bits

• LSB-justified format with data word length of 16,

18 or 20 bits.
STATIC PIN MODE
The UDA1324TS supports the following data input name

formats in the static pin mode (via SF0 and SF1):

• I2S-bus with data word length of up to 20 bits

• LSB-justified format with data word length of 16,

18 or 20 bits.
The static pin codes of the 4 formats, selectable via SF0

and SF1, is given in Table 2.
The UDA1324TS also accepts double speed data for

double speed data monitoring purposes.

Table 2 Input format selection using SF0 and SF1

FORMAT SF0 SF1

2

I

S-bus 0 0

LSB-justified 16 bits 0 1
LSB-justified 18 bits 1 0
LSB-justified 20 bits 1 1

The formats are illustrated in Fig.3. Left and right
data-channel words are time multiplexed. The WS signal
must have 50% duty factor for all LSB-justified modes.

For BCK and WS hold times the BCK frequency must be
equal or smaller then 64 × WS, or f

≤ 64fWSin both L3

BCK

and static modes.

Interpolation filter (DAC)

The digital filter interpolates from 1 to 128fs by cascading
a recursive filter and a FIR filter, see Table 3.

Table 3 Interpolation filter characteristics

ITEM CONDITION VALUE (dB)

Pass-band ripple 0 to 0.45f
Stop band >0.55f
Dynamic range 0 to 0.45f

s

s

s

±0.1

−50

108

Noise shaper

The 3rd-order noise shaper operates at 128f

. It shifts

s

in-band quantization noise to frequencies well above the
audio band. This noise shaping technique enables high
signal-to-noise ratios to be achieved. The noise shaper
output is converted into an analog signal using a
Filter-Stream DAC (FSDAC).

Filter-Stream DAC

The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at
virtual ground of the output operational amplifier. In this
way very high signal-to-noise performance and low clock
jitter sensitivity is achieved. A post-filter isnot needed due
to the inherent filter function of the DAC. On-board
amplifiers convert the FSDAC output current to an output
voltage signal capable of driving a line output.

The output voltage of the FSDAC scales linearly with the
power supply voltage.

1999 Oct 12 5

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1999 Oct 12 6

andbook, full pagewidth

Philips Semiconductors Preliminary specification

Ultra low-voltage stereo filter DAC UDA1324TS

WS

BCK

DATAI

WS

BCK

DATAI

WS

BCK

DATAI

WS

BCK

LEFT

≥8 ≥8

MSB B2 MSBLSB LSB MSBB2

LEFT

1321

≥8 ≥8

MSB B2 MSBLSB LSB MSB B2B2

LEFT

1516 1

MSB LSBB2

LEFT

RIGHT

321321

INPUT FORMAT I

RIGHT

32

MSB-JUSTIFIED FORMAT

2

B15

LSB-JUSTIFIED FORMAT 16 BITS

215161718 1

2

S-BUS

RIGHT

21516 1

MSB LSBB2 B15

RIGHT

215161718 1

DATAI

WS

BCK

DATAI

MSB B2 B3 B4

LEFT

MSB B2 B3 B4 B5 B6

Fig.3 Serial interface; input format I2S-bus.

LSB

B17

LSB-JUSTIFIED FORMAT 18 BITS

2151617181920 1

LSB

B19

LSB-JUSTIFIED FORMAT 20 BITS

MSB B2 B3 B4

RIGHT

MSB B2 B3 B4 B5 B6

B17

B19

LSB

2151617181920 1

LSB

MBK071