Philips TEA1207UK Technical data

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TEA1207UK
High efficiency DC/DC converter Chip Scale package
Product specification 2002 Jul 03
High efficiency DC/DC converter Chip Scale package
FEATURES
Fully integrated DC/DC converter circuit
Up-or-down conversion
Start-up from 1.85 V input voltage
Adjustable output voltage
High efficiency over large load range
Power handling capability up to 0.85 A continuous
average current
275 kHz switching frequency
Low quiescent power consumption
Synchronizing with external clock
True current limit for Li-ion battery compatibility
Up to 100% duty cycle in down mode
Undervoltage lockout
Shut-down function
2 × 2 mm footprint chip scale package.
TEA1207UK
GENERAL DESCRIPTION
The TEA1207UK is a fully integrated DC/DC converter. Efficient, compact and dynamic power conversion is achievedusinganoveldigitallycontrolledconceptsuchas Pulse Width Modulation (PWM) or Pulse Frequency Modulation (PFM), integrated low R switches with low parasitic capacitances, and fully synchronous rectification.
The device operates at a 275 kHz switching frequency which enables the use of external components with minimum size. Deadlock is prevented by an on-chip undervoltage lockout circuit.
Efficient behaviour during short load peaks and compatibility with Li-ion batteries is guaranteed by an accurate current limiting function.
CMOS power
DSon
APPLICATIONS
Cellular and cordless phones, Personal Digital Assistants (PDAs) and others
Supply voltage source for low-voltage chip sets
Portable computers
Battery backup supplies
Cameras.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME DESCRIPTION VERSION
TEA1207UK LFBGA8 plastic low profile fine-pitch ball grid array package;
8 balls; body 2 × 2 × 0.46 mm
2002 Jul 03 2
High efficiency DC/DC converter Chip
TEA1207UK
Scale package
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Voltage levels
UPCONVERSION; BALL U/D=LOW V
I
V
O
V
I(start)
input voltage V output voltage 2.80 5.50 V
start-up input voltage IL< 125 mA 1.40 1.60 1.85 V DOWNCONVERSION; BALL U/D = HIGH V
I
V
O
input voltage 2.80 5.50 V
output voltage 1.30 5.50 V GENERAL V
fb
feedback voltage 1.19 1.24 1.29 V
Current levels
I
q
I
shdwn
I
LX
quiescent current on ball A1 down mode; VI=3.6V 526572µA
current in shut-down state 210µA
maximum continuous current on
ball A2 I
lim
current limiting deviation I
Power MOSFETs
R
DSon
drain-to-source on-state resistance
N-type 0.10 0.20 0.30 P-type 0.10 0.22 0.35
Efficiency
η1 efficiency upconversion V
η2 efficiency downconversion V
Timing
f
sw
f
sync
t
res
switching frequency PWM mode 220 275 330 kHz
synchronization clock input frequency 4 6.5 20 MHz
response time from standby to P
T
=60°C −−0.85 A
amb
= 0.5 to 5 A
lim
up mode 17.5 +17.5 % down mode 17.5 +17.5 %
= 3.6 V; VO= 4.6 V;
I
L1 = 10 µH
I
=1mA 88 %
L
I
= 200 mA 95 %
L
= 1 A; pulsed 83 %
I
L
= 3.6 V; VO= 2.0 V;
I
L1 = 10 µH
I
=1mA 86 %
L
I
= 200 mA 93 %
L
= 1 A; pulsed 81 %
I
L
o(max)
50 −µs
5.50 V
I(start)
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High efficiency DC/DC converter Chip Scale package
BLOCK DIAGRAM
UPOUT/DNIN
A1
SUPPLY
INTERNAL
TEA1207UK
B2
FB
BAND GAP
REFERENCE
TIME
COUNTER
TEA1207UK
MGU402
book, full pagewidth
P-type POWER FET
A2
sense FET
I/V
CONVERTER
C1
CIRCUIT
START-UP
AND
MODE GEARBOX
CONTROL LOGIC
CURRENT LIMIT
COMPARATORS
I/V
CONVERTER
N-type
PROTECTION
TEMPERATURE
FET
POWER
FET
sense
DIGITAL CONTROLLER
GATE
SYNC
13 MHz
OSCILLATOR
B1A3 C3 C2
SHDWN
SYNC U/D
GND
Fig.1 Block diagram.
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2002 Jul 03 4
LX
ILIM
High efficiency DC/DC converter Chip Scale package
PINNING
SYMBOL BALL DESCRIPTION
UPOUT/DNIN A1 output voltage in up mode;
input voltage in down mode LX A2 inductor connection GND A3 ground SYNC B1 synchronization clock input FB B2 feedback input ILIM C1 current limiting resistor
connection U/D C2 up-or-down mode selection
input; active LOW for up mode SHDWN C3 shut-down input
handbook, halfpage
C2 C3C1
B2B1
A2 A3
A1
MGU399
TEA1207UK
When high output power is requested, the device will operate in the PWM mode. This results in minimum AC currents in the circuit components and hence optimum efficiency, minimum cost and low EMC. In this operating mode, the output voltage is allowed to vary between two predefined voltage levels. As long as the output voltage stays within this so-called window, switching continues in a fixed pattern. When the output voltage reaches one of the window borders, the digital controller immediately reacts by adjusting the pulse width and inserting a current step in such a way that the output voltage stays within the window with higher or lower current capability. This approach enables very fast reaction to load variations. Figure 3 shows the converter’s response to a sudden load increase. The upper trace shows the output voltage. The ripple on top of the DC level is a result of the current in the output capacitor, which changes in sign twice per cycle, times the capacitor’s internal Equivalent Series Resistance (ESR). After each ramp-down of the inductor current, i.e. when the ESR effect increases the output voltage, the converter determines what to do in the next cycle. As soon as more load current is taken from the output the output voltage starts to decay.
When the output voltage becomes lower than the low limit of the window, a corrective action is taken by a ramp-up of theinductorcurrent during a much longer time. As a result, the DC current level is increased and normal PWM control can continue. The output voltage (including ESR effect) is again within the predefined window. Figure 4 shows the spread of the output voltage window. The absolute value ismostdependentonspread,whiletheactualwindowsize is not affected. For one specific device, the output voltage will not vary more than 2% typical.
Fig.2 Ball configuration (bottom view).
FUNCTIONAL DESCRIPTION Control mechanism
The TEA1207UK is able to operate in PFM (discontinuous conduction) or PWM (continuous conduction) operating mode. All switching actions are completely determined by a digital control circuit which uses the output voltage level asitscontrolinput. This novel digital approach enables the use of a new pulse width and frequency modulation scheme,whichensuresoptimumpowerefficiencyoverthe complete operating range of the converter.
2002 Jul 03 5
In low output power situations, the TEA1207UK will switch over to PFM mode. In this mode, regulation information from earlier PWM operating modes is used. This results in optimum inductor peak current levels in the PFM mode, which are slightly larger than the inductor ripple current in the PWM mode. As a result, the transition between PFM andPWMmodeisoptimumunderallcircumstances. In the PFM mode the TEA1207UK regulates the output voltage to the high window limit shown in Fig.3.
High efficiency DC/DC converter Chip Scale package
Synchronous rectification
For optimum efficiency over the whole load range, synchronous rectifiers within the TEA1207UK ensure that during the whole second switching phase, all inductor current will flow through the low-ohmic power MOSFETs. Special circuitry is included which detects when the inductorcurrentreaches zero. Following this detection, the digital controller switches off the power MOSFET and proceeds with regulation.
Start-up
Start-up from low input voltage in boost mode is realized by an independent start-up oscillator, which starts switching the N-type power MOSFET as soon as the voltage at ball UPOUT/DNIN is sufficiently high. The switch actions of the start-up oscillator will increase the output voltage. As soon as the output voltage is high enough for normal regulation, the digital control system takes over the control of the power MOSFETs.
Undervoltage lockout
As a result of too high load or disconnection of the input power source, the output voltage can drop so low that normal regulation cannot be guaranteed. In this event, the device switches back to start-up mode. If the output voltage drops down even further, switching is stopped completely.
Shut-down
When the shut-down input is made HIGH, the converter disables both power switches and the power consumption is reduced to a few microamperes.
Power switches
The power switches in the IC are one N-type and one P-type power MOSFET, having a typical drain-to-source resistance of 0.20 and 0.22 respectively. The maximum average current in the power switches is 0.60 A at T
=80°C.
amb
TEA1207UK
Current limiters
If the current in one of the power switches exceeds its limit in the PWM mode, the current ramp is stopped immediately, and the next switching phase is entered. Current limiting is required to enable optimum use of energy in Li-ion batteries, and to keep power conversion efficientduring temporary high loads. Furthermore,current limiting protects the IC against overload conditions, inductor saturation, etc. The current limiting level is set by an external resistor.
External synchronization
If an external high frequency clock is applied to the synchronization clock input, the switching frequency in PWM mode will be exactly that frequency divided by 22. In PFM mode, the switching frequency is always lower. The quiescent current of the device increases when external clock pulses are applied. If no external synchronization is necessary, the synchronization clock input must be connected to ground.
Behaviour when the input voltage exceeds the specified range
In general, an input voltage exceeding the specified range isnot recommended since instability may occur. There are two exceptions:
Upconversion: at an input voltage higher than the target output voltage, but up to 6 V, the converter will stop switchingandtheinternal P-type power MOSFET will be conducting. The output voltage will equal the input voltage minus some resistive voltage drop. The current limiting function is not active.
Downconversion: when the input voltage is lower than the target output voltage, but higher than 2.8 V, the P-type power MOSFET will stay conducting resulting in an output voltage being equal to the input voltage minus some resistive voltage drop. The current limiting function remains active.
Temperature protection
When the device operates in the PWM mode, and the die temperature gets too high (typically 175 °C), the converter stops operating. It resumes operation when the die temperature falls below 175 °C again. As a result, low frequent cycling between the on and off state will occur. It shouldbenotedthat in the event of a device temperature around the cut-off limit, the application will differ strongly from the maximum specification.
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