Philips TDF8704T-4-C1, TDF8704T-5-C1, TDF8704T-2-C1 Datasheet

DATA SH EET

Product specification
Supersedes data of April 1993
File under Integrated Circuits, IC02

June 1994

INTEGRATED CIRCUITS

Philips Semiconductors

TDF8704

8-bit high-speed analog-to-digital
converter

June 1994 2

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDF8704

FEATURES

• 8-bit resolution

• Sampling rate up to 50 MHz

• Extended temperature range (−40 to +85 °C)

• High signal-to-noise ratio over a large analog input

frequency range (7.4 effective bits at 4.43 MHz full-scale
input and at f

clk

= 50 MHz)

• Binary 3-state TTL outputs

• Overflow/underflow 3-state TTL output

• TTL compatible digital inputs

• Low-level AC clock input signal allowed

• Stable internal reference voltage regulator included

• Power dissipation only 380 mW (typical)

• Low analog input capacitance, no buffer amplifier

required

• No sample-and-hold circuit required.

APPLICATIONS

• General purpose high-speed analog-to-digital
conversion for extended temperature applications

• Automotive

• RF, satellite and GPS (Global Positioning System)

• Medical

• General industrial

• Digital video (VCR, TV and satellite).

GENERAL DESCRIPTION

The TDF8704T is an 8-bit high-speed analog-to-digital
converter (ADC) for general industrial applications. It
converts the analog input signal into 8-bit binary-coded
digital words at a maximum sampling rate of 50 MHz. All
digital inputs and outputs are TTL compatible, although a
low-level AC clock input signal is allowed.

QUICK REFERENCE DATA

Note

1. Full-scale sine wave (f

i

= 4.43 MHz; f

clk

= 50 MHz).

ORDERING INFORMATION

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CCA

analog supply voltage 4.75 5.0 5.25 V

V

CCD

digital supply voltage 4.75 5.0 5.25 V

V

CCO

output stages supply voltage 4.75 5.0 5.25 V

I

CCA

analog supply current − 37 46 mA

I

CCD

digital supply current − 23 35 mA

I

CCO

output stages supply current − 16 21 mA
ILE DC integral linear error −±0.4 ±1 LSB
DLE DC differential linearity error −±0.2 ±0.5 LSB
AILE AC integral linearity error note 1 −−±2 LSB
f

clk(max)

maximum clock frequency 50 −−MHz
P

tot

total power dissipation − 380 535 mW

TYPE NUMBER

PACKAGE

SAMPLING

FREQUENCY

PINS PIN POSITION MATERIAL CODE

TDF8704T/2 24 SO24L plastic SOT137-1 20 MHz
TDF8704T/4 24 SO24L plastic SOT137-1 40 MHz
TDF8704T/5 24 SO24L plastic SOT137-1 50 MHz

June 1994 3

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDF8704

BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

4

8

9

V

RB

V

I

V

RT

7

V

CCA

23

15

13

24 D2

D3

D4

D5

D6

1
2

12

D1
D0

D7

TTL OUTPUTS

CLOCK DRIVER

16

CLK

TDF8704

analog

voltage input

overflow / underflow

output

data outputs

LSB

MSB

14

ANALOG - TO - DIGITAL

CONVERTER

LATCHES

MSA685

17
DGND

6
AGND

analog ground digital ground

18

V

CCD

11

22

CE

STABILIZER

TTL OUTPUT

OVERFLOW / UNDERFLOW

LATCH

5DEC

19

V

CCO1

21

V

CCO2

20

output ground

OGND

June 1994 4

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDF8704

PINNING

SYMBOL PIN DESCRIPTION

D1 1 data output; bit 1
D0 2 data output; bit 0 (LSB)
n.c. 3 not connected
V

RB

4 reference voltage BOTTOM

(decoupling)

DEC 5 decoupling input (internal

stabilization loop decoupling)
AGND 6 analog ground
V

CCA

7 analog supply voltage (+5 V)

V

I

8 analog input voltage

V

RT

9 reference voltage TOP (decoupling)
n.c. 10 not connected
O/UF 11 overflow/underflow data output
D7 12 data output; bit 7 (MSB)
D6 13 data output; bit 6
D5 14 data output; bit 5
D4 15 data output; bit 4
CLK 16 clock input
DGND 17 digital ground
V

CCD

18 digital supply voltage (+5 V)

V

CCO1

19 supply voltage for output stages 1

(+5 V)
OGND 20 output ground
V

CCO2

21 supply voltage for output stages 2

(+5 V)
CE 22 chip enable input (TTL level input,

active LOW)
D3 23 data output; bit 3
D2 24 data output; bit 2

Fig.2 Pin configuration.

handbook, halfpage

1
2
3
4
5
6
7
8

9
10
11
12

24
23
22
21

20
19
18
17
16
15
14
13

TDF8704

MSA686

D1
D0

n.c.

V

RB

DEC

AGND
V

CCA

V

RT

n.c.

O/UF

D7

D6

D5

D4

CLK

V

CCD

V

CCO1

OGND

D3

D2

CE

DGND

V

CCO2

V

I

June 1994 5

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDF8704

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC134).

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CCA

analog supply voltage −0.3 +7.0 V

V

CCD

digital supply voltage −0.3 +7.0 V

V

CCO

output stages supply voltage −0.3 +7.0 V

∆V

CC

supply voltage differences between V

CCA

and V

CCD

−1.0 +1.0 V

∆V

CC

supply voltage differences between V

CCO

and V

CCD

−1.0 +1.0 V

∆V

CC

supply voltage differences between V

CCA

and V

CCO

−1.0 +1.0 V

V

I

input voltage referenced to AGND −0.3 +7.0 V

V

clk(p-p)

AC input voltage for switching (peak-to-peak value) referenced to DGND − V

CCD

V

I

O

output current − 10 mA

T

stg

storage temperature −55 +150 °C

T

amb

operating ambient temperature −40 +85 °C

T

j

junction temperature − +150 °C

SYMBOL PARAMETER VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air 75 K/W

June 1994 6

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDF8704

CHARACTERISTICS (see Tables 1 and 2)

V

CCA

= V7 to V6 = 4.75 to 5.25 V; V

CCD

= V18to V17 = 4.75 to 5.25 V; V

CCO

= V19and V21to V20 = 4.75 to 5.25 V; AGND

and DGND shorted together; V

CCA

to V

CCD

= −0.25 to +0.25 V; V

CCO

to V

CCD

= −0.25 to +0.25 V;

V

CCA

to V

CCD

= −0.25 to +0.25 V; T

amb

= −40 to +85 °C; typical readings taken at V

CCA=VCCD

= 5 V and T

amb

=25°C;

unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V

CCA

analog supply voltage 4.75 5.0 5.25 V

V

CCD

digital supply voltage 4.75 5.0 5.25 V

V

CCO

output stages supply voltage 4.75 5.0 5.25 V

I

CCA

analog supply current − 37 46 mA

I

CCD

digital supply current − 23 35 mA

I

CCO

output stages supply current all outputs LOW − 16 21 mA

Inputs

C

LOCK INPUT CLK (REFERENCED TO DGND)

V

IL

LOW level input voltage 0 − 0.8 V

V

IH

HIGH level input voltage 2.0 − V

CCD

V

I

IL

LOW level input current V

clk

= 0.4 V −400 −−µA

I

IH

HIGH level input current V

clk

= 2.7 V −−100 µA

V

clk=VCCD

−−300 µA

Z

I

input impedance f

clk

= 50 MHz − 2 − kΩ

C

I

input capacitance f

clk

= 50 MHz − 4.5 − pF
VI(ANALOG INPUT VOLTAGE REFERENCED TO AGDN; SEE FIGS 3 AND 4 AND TABLE 1)
V

I(B)

input voltage (BOTTOM) 1.21 1.25 1.29 V

V

I(0)

input voltage output code = 0 1.42 1.48 1.51 V

V

os(B)

offset voltage (BOTTOM) V

I(0)

to V

I(B)

210 225 240 V

V

I(T)

input voltage (TOP) 3.37 3.46 3.58 V

V

I(255)

input voltage output code = 255 3.14 3.22 3.30 V

V

os(T)

offset voltage (TOP) V

I(T)

to V

I(255)

225 240 255 V

V

I(p-p)

input voltage amplitude
(peak-to-peak value)

1.69 1.74 1.79 V

I

L

load current on VRT and V

RB

−300 − +300 µA

I

IL

LOW level input current VI = 1.25 V − 0 −µA

I

IH

HIGH level input current VI = 3.46 V 40 150 400 µA

Z

I

input impedance fi = 4.43 MHz − 10 − kΩ

C

I

input capacitance fi = 4.43 MHz − 14 − pF