Philips TDA9962 Datasheet

INTEGRATED CIRCUITS

DATA SH EET

TDA9962

12-bit, 3.0 V, 20 Msps analog-to-digital interface for CCD cameras

Objective speciﬁcation File under Integrated Circuits, IC02

2000 May 01

Philips Semiconductors Objective speciﬁcation

12-bit, 3.0 V, 20 Msps analog-to-digital interface for CCD cameras

FEATURES

• Correlated Double Sampling (CDS), Programmable GainAmplifier (PGA),12-bitAnalog-to-DigitalConverter (ADC) and reference regulator included

• Fully programmable via a 3-wire serial interface

• Sampling frequency up to 20 MHz

• PGA gain range of 24 dB (in steps of 0.1 dB)

• Low power consumption of only 140 mW at 2.7 V

• Power consumption in standby mode of 4.5 mW (typ.)

• 3.0 V operation and 2.2 to 3.6 V operation for the digital

outputs

• All digital inputs accept 5 V signals

• Active control pulses polarity selectable via serial

interface

• 8-bit DAC included for analog settings

• TTL compatible inputs, CMOS compatible outputs.

TDA9962

APPLICATIONS

• Low-power, low-voltage CCD camera systems.

GENERAL DESCRIPTION

The TDA9962 is a 12-bit analog-to-digital interface for CCD cameras. The device includes a correlated double samplingcircuit, PGA, clamploops and alow-power 12-bit ADC together with its reference voltage regulator.

The PGA gain and the ADC input clamp level are controlled via the serial interface.

An additional DAC is provided for additional system controls; its output voltage range is 1.0 V (p-p) which is available at pin OFDOUT.

ORDERING INFORMATION

TYPE

NUMBER

TDA9962HL LQFP48 plastic low proﬁle quad ﬂat package; 48 leads; body 7 × 7 × 1.4 mm SOT313-2

NAME DESCRIPTION VERSION

PACKAGE

2000 May 01 2

Philips Semiconductors Objective speciﬁcation

12-bit, 3.0 V, 20 Msps analog-to-digital

TDA9962

interface for CCD cameras

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

CCA

CCD

CCO

CCA

CCD

CCO

ADC

res

i(CDS)(p-p)

pix(max)

pix(min)

PGA

tot(rms)

in(rms)

tot

analog supply voltage 2.7 3.0 3.6 V digital supply voltage 2.7 3.0 3.6 V digital outputs supply voltage 2.2 2.5 3.6 V analog supply current all clamps active − 49 − mA digital supply current − 2 − mA digital outputs supply current f

= 20 MHz; CL= 20 pF; input

pix

− 1 − mA

ramp response time is 800 µs ADC resolution − 12 − bits maximum CDS input voltage

(peak-to-peak value)

VCC= 2.85 V 650 −−mV

≥ 3.0 V 800 −−mV

maximum pixel rate 20 −−MHz minimum pixel rate tbf −−MHz PGA dynamic range − 24 − dB total noise from CDS input to

PGA gain = 0 dB; see Fig.8 − 1.2 − LSB ADC output

equivalent input noise

gain=24dB − 95 −µV (RMS value)

total power consumption V

CCA=VCCD=VCCO

=3V − 155 − mW = 2.7 V − 140 − mW

2000 May 01 3

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2000 May 01 4

BLOCK DIAGRAM

Philips Semiconductors Objective speciﬁcation

12-bit, 3.0 V, 20 Msps analog-to-digital

interface for CCD cameras

CPCDS1

CPCDS2

CCA2

AGND2

CCA3

AGND3

OFDOUT

REGULATOR

OUTPUT BUFFER

22 21

38 36 35 34 33 32 31 30 29 28 27 26 25

24 23

FCE504

DGND1 V

CCD1

OGND2

CCO2

D11 D10

D9 D8 D7 D6 D5 D4 D3 D2 D1

OGND1

CCO1

DCLPC

BLK

BLANKING

STDBY

SHD

AGND4

CCA1

SHIFT

ref

AGND5

SHP

CDS CLOCK GENERATOR

9 7

CORRELATED

DOUBLE

SAMPLING

OFD DAC

12 6

TEST

CLAMP

AGND1

CLAMP

CCA4

AGND6

PGA

8-BIT

CLPDM

CLPOB

OPGA OPGAC

TDA9962

BLACK LEVEL SHIFT

SEN

7-BIT

SERIAL

INTERFACE

SCLK

SDATA

12-bit ADC

VSYNC

CLK

DATA

FLIP-

FLOP

handbook, full pagewidth

Fig.1 Block diagram.

TDA9962

Philips Semiconductors Objective speciﬁcation

12-bit, 3.0 V, 20 Msps analog-to-digital

TDA9962

interface for CCD cameras

PINNING

SYMBOL PIN DESCRIPTION

CCA1

AGND1 2 analog ground 1 AGND2 3 analog ground 2 IN 4 input signal from CCD AGND3 5 analog ground 3 AGND4 6 analog ground 4 V

CCA2

CPCDS1 8 clamp storage capacitor pin 1 CPCDS2 9 clamp storage capacitor pin 2 DCLPC 10 regulator decoupling pin OFDOUT 11 analog output of the additional 8-bit control DAC TEST 12 test mode input pin (should be connected to AGND5) AGND5 13 analog ground 5 V

CCA3

OPGA 15 PGA output (test pin) OPGAC 16 PGA complementary output (test pin) SDATA 17 serial data input for serial interface control SCLK 18 serial clock input for serial interface SEN 19 strobe pin for serial interface VSYNC 20 vertical sync pulse input V

CCD1

DGND1 22 digital ground 1 V

CCO1

OGND1 24 digital output ground 1 D0 25 ADC digital output 0 (LSB) D1 26 ADC digital output 1 D2 27 ADC digital output 2 D3 28 ADC digital output 3 D4 29 ADC digital output 4 D5 30 ADC digital output 5 D6 31 ADC digital output 6 D7 32 ADC digital output 7 D8 33 ADC digital output 8 D9 34 ADC digital output 9 D10 35 ADC digital output 10 D11 36 ADC digital output 11 (MSB) OGND2 37 digital output ground 2 V

CCO2

OE 39 output enable control input (LOW = outputs active; HIGH = outputs in high-impedance) AGND6 40 analog ground 6

1 analog supply voltage 1

7 analog supply voltage 2

14 analog supply voltage 3

21 digital supply voltage 1

23 digital outputs supply voltage 1

38 digital outputs supply voltage 2

2000 May 01 5

Philips Semiconductors Objective speciﬁcation

12-bit, 3.0 V, 20 Msps analog-to-digital

TDA9962

interface for CCD cameras

SYMBOL PIN DESCRIPTION

CCA4

STDBY 42 standby mode control input (LOW = TDA9962 active; HIGH = TDA9962 standby) BLK 43 blanking control input CLPOB 44 clamp pulse input at optical black SHP 45 preset sample-and-hold pulse input SHD 46 data sample-and-hold pulse input CLK 47 data clock input CLPDM 48 clamp pulse input at dummy pixel

handbook, full pagewidth

41 analog supply voltage 4

CLPDM

CLK

SHD 46

SHP 45

CLPOB

BLK

STDBY

CCA4

AGND6 40

CCO2

V 38

OGND2 37

CCA1 AGND1 AGND2

AGND3 AGND4

CCA2

CPCDS1

CPCDS2

DCPLC

OFD

TEST

D11

OGND1

36 35 34 33 32 31 30 29 28 27 26 25

FCE505

D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

1 2 3 4 5 6 7 8 9

10 11 12

CCA3

AGND5

OPGA

TDA9962HL

SDATA

OPGAC

SCLK

SEN

CCD1

VSYNC

CCO1

DGND1

Fig.2 Pin configuration.

2000 May 01 6

Philips Semiconductors Objective speciﬁcation

12-bit, 3.0 V, 20 Msps analog-to-digital

TDA9962

interface for CCD cameras

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

CCA

CCD

CCO

∆V

stg

amb

Note

1. The supply voltages V voltage difference ∆VCC remains as indicated.

analog supply voltage note 1 −0.3 +7.0 V digital supply voltage note 1 −0.3 +7.0 V digital outputs supply voltage note 1 −0.3 +7.0 V supply voltage difference

between V between V between V

CCA CCA CCD

and V and V and V

CCD CCO CCO

−0.5 +0.5 V

−0.5 +1.2 V

input voltage referenced to AGND −0.3 +7.0 V data output current −±10 mA storage temperature −55 +150 °C ambient temperature −20 +75 °C junction temperature − +150 °C

, V

CCA

CCD

and V

may have any value between −0.3 and +7.0 V provided that the supply

CCO

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

th(j-a)

thermal resistance from junction to ambient in free air 76 K/W

2000 May 01 7

Philips Semiconductors Objective speciﬁcation

12-bit, 3.0 V, 20 Msps analog-to-digital

TDA9962

interface for CCD cameras

CHARACTERISTICS

CCA=VCCD

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

CCA

CCD

CCO

CCA

CCD

CCO

Digital inputs

INS SHP, SHD AND CLK (REFERENCED TO DGND)

P V

PINS CLPDM, CLPOB, SEN, SCLK, SDATA, STBY, OE, BLK AND VSYNC V

Clamps

= 3.0 V; V

CCO

= 2.5 V; f

= 20 MHz; T

pix

=25°C; unless otherwise speciﬁed.

amb

analog supply voltage 2.7 3.0 3.6 V digital supply voltage 2.7 3.0 3.6 V digital outputs supply

2.2 2.5 3.6 V

voltage analog supply current all clamps active − 49 − mA digital supply current − 2 − mA digital outputs supply

current

CL= 20 pF on all data outputs; input ramp

− 1 − mA

response time is 800 µs

LOW-level input voltage 0 − 0.6 V HIGH-level input voltage 2.2 − 5.5 V input current 0 ≤ Vi≤ 5.5 V −3 − +3 µA input impedance f input capacitance f

=20MHz − 50 − kΩ

CLK

=20MHz −− 2pF

CLK

LOW-level input voltage 0 − 0.6 V HIGH-level input voltage 2.2 − 5.5 V input current 0 ≤ Vi≤ 5.5 V −2 − +2 µA

GLOBAL CHARACTERISTICS OF THE CLAMP LOOPS t

W(clamp)

clamp active pulse width in number of pixels

PGA code = 255 for

maximum 4 LSB error INPUT CLAMP (DRIVEN BY CLPDM) g

m(CDS)

CDS input clamp transconductance

Correlated Double Sampling (CDS)

i(CDS)(p-p)

reset(max)

maximum peak-to-peak CDS input amplitude (video signal)

maximum CDS input reset

VCC= 2.85 V 650 −−mV

≥ 3.0 V 800 −−mV

pulse amplitude

i(IN)

CDS(min)

input current into pin IN at ﬂoating gate level tbf − tbf µA input capacitance − 2 − pF CDS control pulses

minimum active time

i(CDS)(p-p)

= 800 mV black-to-white transition in 1 pixel with 99% Vi recovery

2000 May 01 8

12 −−pixels

− 20 − mS

500 −−mV

11 15 − ns

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