Philips TDA9855WP, TDA9855 Datasheet

INTEGRATED CIRCUITS

DATA SH EET

TDA9855

2

I

C-bus controlled BTSC
stereo/SAP decoder and audio
processor

Product specification
Supersedes data of July 1994
File under Integrated Circuits, IC02

1997 Nov 04

Philips Semiconductors Product specification

I2C-bus controlled BTSC stereo/SAP
decoder and audio processor

FEATURES

• Quasi alignment-free BTSC stereo decoder due to
automatic adjustment of channel separation via I2C-bus

• High integration level with automatically tuned
integrated filters

• Input level adjustment I2C-bus controlled

• Alignment-free SAP processing

• dbx noise reduction circuit

• I2C-bus transceiver.

Audio processor

• Selector for internal and external signals (line in)

• Automatic volume level control

• Subwoofer or surround output with separate volume

control

• Volume control

• Special loudness characteristic automatically controlled

in combination with volume setting

• Bass and treble control

• Audio signal zero-crossing detection between any

volume step switching

• Mute control at audio signal zero-crossing.

TDA9855

GENERAL DESCRIPTION

The TDA9855 is a bipolar-integrated BTSC stereo/SAP
decoder with hi-fi audio processor (I2C-bus controlled) for
application in TV sets.

ORDERING INFORMATION

TYPE NUMBER

NAME DESCRIPTION VERSION

TDA9855 SDIP52 plastic shrink dual in-line package; 52 leads (600 mil) SOT247-1
TDA9855WP PLCC68 plastic leaded chip carrier; 68 leads SOT188-2

LICENSE INFORMATION

A license is required for the use of this product. For further information, please contact

COMPANY BRANCH ADDRESS

THAT Corporation Licensing Operations 734 Forest St.

Tokyo Office 405 Palm House, 1-20-2 Honmachi

PACKAGE

Marlborough, MA 01752
USA
Tel.: [phone]
Fax: [phone]

Shibuya-ku, Tokyo 151
Japan
Tel.: [phone]
Fax: [phone]

1997 Nov 04 2

Philips Semiconductors Product specification

I2C-bus controlled BTSC stereo/SAP

TDA9855

decoder and audio processor

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CC

I

CC

V

COMP(rms)

V

oR,L(rms)

G

LA

α

cs

THD

L,R

V

I, O(rms)

AVL control range −15 − +6 dB
G

c

L

B

G

bass

G

treble

G

s

S/N signal-to-noise ratio line out (mono); V

supply voltage 8.0 8.5 9.0 V
supply current 50 75 95 mA
input signal voltage (RMS value) 100% modulation L + R;

− 250 − mV

fi= 300 Hz

output signal voltage (RMS value) 100% modulation L + R;

− 500 − mV

fi= 300 Hz

input level adjustment control maximum gain − 4 − dB

maximum attenuation −−3.5 − dB
stereo channel separation fL= 300 Hz; fR= 3 kHz 25 35 − dB
total harmonic distortion L + R fi= 1 kHz − 0.2 − %
signal handling (RMS value) THD < 0.5% 2 −−V

volume control range −71 − +16 dB
maximum loudness boost fi=40Hz − 17 − dB
bass control range fi=40Hz −12 − +16.5 dB
treble control range fi= 15 kHz −12 − +12 dB
subwoofer control range fi=40Hz −14 − +14 dB

= 0.5 V (RMS)

o

CCIR noise weighting filter

− 60 − dB

(peak value)
DIN noise weighting filter

− 73 − dBA

(RMS value)

audio section; V

= 2 V (RMS);

o

gain = 0 dB

CCIR noise weighting filter

− 94 − dB

(peak value)
DIN noise weighting filter

− 107 − dBA

(RMS value)

1997 Nov 04 3

Philips Semiconductors Product specification

I2C-bus controlled BTSC stereo/SAP
decoder and audio processor

BLOCK DIAGRAM

OUTR

C36

(63) 47

C14

52

handbook, full pagewidth

R3

R2

C11

CC

V

C10

(EIR)

C7

External Input Right

C4 C5
C3

Q1

C20

C16

CERAMIC

C13

C45

C6

RESONATOR

C2

C12

C9

C8

C28

MURATA

R1

(68)

50

(66)

51

(67)

46

(59)

VIR

45

(58)

44

(57)

43

(56)

42

(55)

10

(14)

40

(52)

39

(51)

41

(54)

38

(50)

LOR LIR

37

(49)

36

(48)

CSB503F58

35

(47)

34

(46)

33

(43)

32

(41)

31

(40)

RIGHT

TREBLE

CONTROL

BASS

RIGHT

CONTROL

RIGHT

VOLUME

CONTROL

LOUDNESS

STEREO DECODER

C35

(65) 49

OUTS

C40

(5) 4

MATRIX,

VOLUME

SURROUND

SUBWOOFER

ZERO

CROSSING

TDA9855

EFFECTS

AUTOMATIC

VOLUME AND

LEVEL CONTROL

INPUT

SELECT

+

SELECT

LINEOUT

DEMATRIX

/SAP

SWITCH

STEREO

INPUT

LEVEL

ADJUST

29 (38)

C1

OUTL

C39

(7) 6

LEFT

TREBLE

LEFT

BASS

LEFT

VOLUME

LOUDNESS

C-

2

I

LOGIC,

SUPPLY

ADJUST

STEREO

DBX

SAP

DEMODULATOR

(1)

CONTROL

(4)

(3)

CONTROL

(11)

(12)

CONTROL

(13)

(36)

(35)

(6)

TRANCEIVER

(33,

34)

(15)
(39)

(37)

(18)

(19)

(16)

(20)
(21)

(22)
(23)
(24)

(27)

(25)
(29)

(30)

(31)

TDA9855

MHA837

C33

1

3

C32

2

C31

D1

C29

C26

R5

R4

C30

SCL

SDA

MAD

C15 C34

C49

CC

V

C47

(EIL)

C37 C27

External Input Left

C25C24

C23C22

R7

C21

C19

C18

C17

Fig.1 Block diagram.

7

8

VIL

9

27

28

5

25
11

30

28

13

14

12

15
16

LOL LIL

17
18
19

21

R6

20
22

23

24

1997 Nov 04 4

COMP

The numbers given in parenthesis refer to the TDA9855WP version.

Philips Semiconductors Product specification

I2C-bus controlled BTSC stereo/SAP

TDA9855

decoder and audio processor

Component list

Electrolytic capacitors ±20%; foil or ceramic capacitors ±10%; resistors ±5%; unless otherwise specified; see Fig.1.

COMPONENTS VALUE TYPE REMARK

C1 10 µF electrolytic 63 V
C2 470 nF foil −
C3 4.7 µF electrolytic 63 V
C4 220 nF foil −
C5 10 µF electrolytic 63 V; I
C6 2.2 µF electrolytic 16 V
C7 4.7 µF electrolytic 16 V
C8 15 nF foil ±5%

C9 15 nF foil ±5%
C10 2.2 µF electrolytic 63 V
C11 8.2 nF foil or ceramic ±5% SMD 2220/1206
C12 150 nF foil ±5%
C13 33 nF foil ±5%
C14 5.6 nF foil or ceramic ±5% SMD 2220/1206
C15 100 µF electrolytic 16 V
C16 4.7 µF electrolytic 63 V
C17 4.7 µF electrolytic 63 V
C18 100 nF foil
C19 10 µF electrolytic 63 V
C20 4.7 µF electrolytic 63 V
C21 47 nF foil ±5%
C22 1 µF electrolytic 63 V
C23 1 µF electrolytic 63 V
C24 10 µF electrolytic 63 V ±10%
C25 10 µF electrolytic 63 V ±10%
C26 2.2 µF electrolytic 16 V
C27 2.2 µF electrolytic 63 V
C28 4.7 µF electrolytic 63 V ±10%
C29 2.2 µF electrolytic 16 V
C30 8.2 nF foil or ceramic ±5% SMD 2220/1206
C31 150 nF foil ±5%
C32 33 nF foil ±5%
C33 5.6 nF foil or ceramic ±5% SMD 2220/1206
C34 100 µF electrolytic 16 V
C35 150 nF foil ±5%
C36 4.7 µF electrolytic 16 V
C37 4.7 µF electrolytic 16 V
C39 4.7 µF electrolytic 16 V
C40 4.7 µF electrolytic 16 V

leak

< 1.5 µA

1997 Nov 04 5

Philips Semiconductors Product specification

I2C-bus controlled BTSC stereo/SAP
decoder and audio processor

COMPONENTS VALUE TYPE REMARK

C45 2.2 µF electrolytic 16 V
C47 220 µF electrolytic 25 V
C49 100 nF foil or ceramic SMD 1206

D1 −−general purpose diode

R1 2.2 kΩ− −

R2 20 kΩ− −

R3 2.2 kΩ− −

R4 20 kΩ− −

R5 2.2 kΩ− −

R6 8.2 kΩ− ±2%

R7 160 Ω− ±2%

Q1 CSB503F58 radial leads

CSB503JF958 alternative as SMD

PINNING

TDA9855

SYMBOL

DESCRIPTION

PLCC68 SDIP52

TL 1 1 treble control capacitor, left channel
n.c. 2 − not connected
B1L 3 2 bass control capacitor, left channel
B2L 4 3 bass control capacitor, left channel
OUTS 5 4 output subwoofer or output surround sound
MAD 6 5 programmable address bit (module address)
OUTL 7 6 output, left channel
n.c. 8 to 10 − not connected
LDL 11 7 input loudness, left channel
VIL 12 8 input volume control, left channel
EOL 13 9 output effects, left channel

PINS

C

AV

V

ref

14 10 automatic volume control capacitor
15 11 reference voltage 0.5V

CC

LIL 16 12 input line, left channel
n.c. 17 − not connected
AVL 18 13 input automatic volume control, left channel
SOL 19 14 output selector, left channel
LOL 20 15 output line control, left channel
C

TW

C

TS

C

W

C

S

21 16 capacitor timing wideband for dbx
22 17 capacitor timing spectral for dbx
23 18 capacitor wideband for dbx
24 19 capacitor spectral for dbx

VEO 25 20 variable emphasis output for dbx

1997 Nov 04 6

Philips Semiconductors Product specification

I2C-bus controlled BTSC stereo/SAP

TDA9855

decoder and audio processor

SYMBOL

PLCC68 SDIP52

n.c. 26 − not connected
VEI 27 21 variable emphasis input for dbx
n.c. 28 − not connected
C

NR

C

M

C

DEC

29 22 capacitor noise reduction for dbx
30 23 capacitor mute for SAP

31 24 capacitor DC-decoupling for SAP
n.c. 32 − not connected
AGND 33 − analog ground
DGND 34 − digital ground
GND − 25 ground
SDA 35 26 serial data input/output (I
SCL 36 27 serial clock input (I
V

CC

37 28 supply voltage
COMP 38 29 composite input signal
V
C
C

CAP

P1
P2

39 30 capacitor for electronic filtering of supply

40 31 capacitor for pilot detector

41 32 capacitor for pilot detector
n.c. 42 − not connected
C

PH

43 33 capacitor for phase detector
n.c. 44, 45 − not connected
C

ADJ

46 34 capacitor for filter adjustment
CER 47 35 ceramic resonator
C

MO

C

SS

48 36 capacitor DC-decoupling mono

49 37 capacitor DC-decoupling stereo/SAP
LOR 50 38 output line control, right channel
SOR 51 39 output selector, right channel
AVR 52 40 input automatic volume control, right channel
n.c. 53 − not connected
LIR 54 41 input line control, right channel
C

PS2

C

PS1

55 42 capacitor 2 pseudo function

56 43 capacitor 1 pseudo function
EOR 57 44 output effects, right channel
VIR 58 45 input volume control, right channel
LDR 59 46 input loudness, right channel
n.c. 60 to 62 − not connected
OUTR 63 47 output, right channel
n.c. 64 48 not connected
SW 65 49 filter capacitor for subwoofer

PINS

DESCRIPTION

2

C-bus)

2

C-bus)

1997 Nov 04 7

Philips Semiconductors Product specification

I2C-bus controlled BTSC stereo/SAP
decoder and audio processor

n.c.

8

PINS

OUTL
7

MAD
6

OUTS

5

B2L

4

n.c.

B1L
3

2

TDA9855H

TL

DESCRIPTION

TR

B1R

B2RSWn.c.

1

68

67

66

65

OUTR

64

63

n.c.

62

n.c.

61

SYMBOL

PLCC68 SDIP52

B2R 66 50 bass control capacitor, right channel
B1R 67 51 bass control capacitor, right channel
TR 68 52 treble control capacitor

handbook, full pagewidth

n.c.

9

10

n.c.

11

LDL

12

VIL

13

EOL
C

14

AV

V

15

ref

16

LIL

17

n.c.

18

AVL

19

SOL

20

LOL

C

21

TW

C

22

TS

23

C

W

C

24

S

25

VEO

26

n.c.

TDA9855

60

n.c.

59

LDR

58

VIR

57

EOR
C

56

PS1

C

55

PS2

54

LIR

53

n.c.

52

AVR

51

SOR

50

LOR
C

49

SS

C

48

MO

47

CER
C

46

ADJ

45

n.c.

44

n.c.

27

28

29

30

31

32

33

34

M

NR

VEI

n.c.

C

C

DEC

C

n.c.

AGND

DGND

Fig.2 Pin configuration (PLCC version).

1997 Nov 04 8

35

SDA

36

SCL

V

37

CC

38

COMP

39

CAP

V

40

CP1C

41

42

43

P2

n.c.

MHA836

PH

C

Philips Semiconductors Product specification

I2C-bus controlled BTSC stereo/SAP
decoder and audio processor

handbook, halfpage

TL TR

1

B1L B1R

2

B2L B2R

3

OUTS SW

4

MAD n.c.

5

OUTL OUTR

6

LDL LDR

7

VIL VIR

8

EOL EOR

9

C

10

AV

V

11

ref

LIL LIR

12

AVL AVR

13

52

51
50
49
48
47
46
45
44

C

43

PS1

C

42

PS2

41
40

TDA9855

SOL SOR

14

LOL LOR

15

C

16

TW

C

17

TS

C

18

W

C

19

s

VEO

20

VEI

21

C

22

NR

C

23

M

C

24

DEC

GND

25

SDA SCL

26

MHA835

39
38

C

37

SS

C

36

MO

CER

35

C

34

ADJ

C

33

PH

C

32

P2

C

31

P1

V

30

CAP

COMP

29

V

28

CC

27

TDA9855

FUNCTIONAL DESCRIPTION
Decoder

NPUT LEVEL ADJUSTMENT

I
The composite input signal is fed to the input level

adjustment stage. In order to compensate tolerances of
the FM demodulator which supplied the composite input
signal, the TDA9855 provides an input level adjustment
stage. The control range is from−3.5 to +4.0 dB in steps of

0.5 dB. The subaddress control 3 of Tables 5 and 6 and
the level adjust setting of Table 22 allows an optimum
signal adjustment during the set alignment in the
production line. This value has to be stored in a
non-volatile memory. The maximum input signal voltage is
2 V (RMS).

TEREO DECODER

S
The output signal of the level adjustment stage is coupled

to a low-pass filter which suppresses the baseband noise
above 125 kHz. The composite signal is then fed into a
pilot detector/pilot cancellation circuit and into the MPX
demodulator. The main L + R signal passes a 75 µs fixed
de-emphasis filter and is fed into the dematrix circuit.
The decoded sub-signal L − R is sent to the stereo/SAP
switch. To generate the pilot signal the stereo demodulator
uses a PLL circuit including a ceramic resonator.
The stereo channel separation can be adjusted by an
automatic procedure or manually. For a detailed
description see Section “Adjustment procedure”.
The stereo identification can be read by the I2C-bus
(see Table 2). Two different pilot thresholds can be
selected via the I2C-bus (see Table 24).

DEMODULATOR

SAP
The composite signal is fed from the output of the input

level adjustment stage to the SAP demodulator circuit
through a 5fH (fH= horizontal frequency) band-pass filter.
The demodulator level is automatically controlled.
The SAP demodulator includes internal noise and field
strength detectors that mute the SAP output in the event of
insufficient signal conditions. The SAP identification signal
can be read by the I2C-bus (see Table 2).

S

WITCH

Fig.3 Pin configuration (SDIP version).

1997 Nov 04 9

The stereo/SAP switch feeds either the L − R signal or the
SAP demodulator output signal via the internal dbx noise
reduction circuit to the dematrix/line out select circuit.
Table 21 shows the different switch modes provided at the
output pins LOR and LOL.

Philips Semiconductors Product specification

I2C-bus controlled BTSC stereo/SAP
decoder and audio processor

dbx DECODER
The circuit includes all blocks required for the noise

reduction system in accordance with the BTSC system
specification. The output signal is fed through a 73 µs fixed
de-emphasis circuit to the dematrix block.

I

NTEGRATED FILTERS

The filter functions necessary for stereo and SAP
demodulation and part of the dbx filter circuits are provided
on-chip using transconductor circuits. The required filter
accuracy is attained by an automatic filter alignment
circuit.

Audio processor

SELECTOR
The selector allows selecting either the internal line out

signals LOR or LOL (dematrix output) or the external line
in signals LIR and LIL and combines the left and right
signals in several modes (see Table 12). The input signal
capability of the line inputs (LIR/LIL) is 2 V (RMS).
The output of the selector is AC-coupled to the automatic
volume level control circuit via pins SOR/SOL and
AVR/AVL to avoid offset voltages.

A

UTOMATIC VOLUME LEVEL CONTROL

The automatic volume level stage controls its output
voltage to a constant level of typically 200 mV (RMS) from
an input voltage range of 0.1 to 1.1 V (RMS). The circuit
adjusts variations in modulation during broadcasting and
due to changes in the programme material. The function
can be switched off. To avoid audible ‘plops’ during the
permanent operation of the AVL circuit a soft blending
scheme has been applied between the different gain
stages. A capacitor (4.7 µF) at pin CAV determines the
attack and decay time constants. In addition the ratio of
attack and decay time can be changed via the I2C-bus
(see notes 7 and 8 of Chapter “Characteristics”).

E

FFECTS

The audio processor section offers the following mode
selections: linear stereo, pseudo stereo, spatial stereo and
forced mono.The spatial mode provides an antiphase
crosstalk of 30% or 52% (switchable via the I2C-bus;
see Table 18).

OLUME/LOUDNESS

V
The volume control range is from +16 dB to −71 dB in

steps of 1 dB and ends with a mute step (see Table 8).
Balance control is achieved by the independent volume

TDA9855

control of each channel. The volume control blocks
operate in combination with the loudness control. The filter
is linear when maximum gain for volume control is
selected. The filter characteristic changes automatically
over a range of 28 dB down to a setting of −12 dB.
At −12 dB volume control the maximum loudness boost is
obtained. The filter characteristic is determined by external
components. The proposed application provides a
maximum boost of 17 dB for bass and 4.5 dB for treble.
The loudness may be switched on or off via I
control (see Table 14). The left and right volume control
stages include two independent zero-crossing detectors.
In the zero-crossing mode a change in volume is
automatically activated but not executed. The execution is
enabled at the next zero-crossing of the signal. If a new
volume step is activated before the previous one has been
processed, the previous value will be executed first, and
then the new value will be activated. If no zero-crossing
occurs the next volume transmission will enforce the last
activated volume setting.

The zero-crossing mode is realized between adjoining
steps and between any steps, but not from any step to
mute. In this case the GMU bit is required for use. In case
only one channel has to be muted, two steps are
necessary. The first step is a transmission of any step to

−71 dB and the second step is the −71 dB step to mute
mode. The step of −71 dB to mute mode has no
zero-crossing but this is not relevant. This procedure has
to be provided by software.

B

ASS CONTROL

A single external 33 nF capacitor for each channel in
combination with a linear operational amplifier and internal
resistors provides a bass control range of +16.5 to −12 dB
in steps of 1.5 dB at low frequencies (40 Hz). Internally the
basic step width is 3 dB, with intermediate steps obtained
by a toggle function that provides an additional 1.5 dB
boost or attenuation (see Table 9). It should be noted that
both loudness and bass control together result in a
maximum bass boost of 34.5 dB for low volume steps.

T

REBLE CONTROL

The adjustable range of the treble control stage is from

−12 to +12 dB in steps of 3 dB. The filter characteristic is
determined by an external 5.6 nF capacitor for each
channel. The logic circuitry is arranged in a way that the
same data words (06H to 16H) can be used for both tone
controls if a bass control range from −12 to +12 dB and a
treble control range from −12 to +12 dB with 3 dB steps
are used (see Tables 9 and 10).

2

C-bus

1997 Nov 04 10

Philips Semiconductors Product specification

I2C-bus controlled BTSC stereo/SAP
decoder and audio processor

SUBWOOFER; SURROUND SOUND CONTROL
The subwoofer or the surround mode can be activated with

the control bit SUR (see Table 6). A low bit provides an
output signal1⁄2(L + R) in subwoofer mode, a high bit
selects surround mode and provides an output signal

1

⁄2(L − R). The signal is fed through a volume control stage

with a range from +14 to −14 dB in 2 dB steps on top of the
main channel control to the output pin OUTS. The last
setting is the mute position (see Table 11). The capacitor
C35 at pin SW provides a 230 Hz low-pass filter in
subwoofer mode. In surround mode this capacitor should
be disconnected. If balance is not in mid position the
selected left and right output levels will be combined.

M

UTE

The mute function can be activated independently with the
last step of volume or subwoofer/surround control at the
left, right or centre output. By setting the general mute bit
GMU via the I2C-bus all audio part outputs are muted.
All channels include an independent zero-crossing
detector. The zero-crossing mute feature can be selected
via bit TZCM:

TZCM = 0: forced mute with direct execution
TZCM = 1: execution in time with signal zero-crossing.

In the zero-crossing mode a change of the GMU bit is
activated but not executed. The execution is enabled at
the next zero-crossing of the signal. To avoid a large delay
of mute switching, when very low frequencies are
processed, or the output signal amplitude is lower than the
DC offset voltage, the following I2C-bus transmissions are
needed:

A first transmission for mute execution
A second transmission approximately 100 ms later,

which must switch the zero-crossing mode to forced
mute (TZCM = 0)

A third transmission to reactivate the zero-crossing
mode (TZCM = 1). This transmission can take place
immediately, but must follow before the next mute
execution.

Adjustment procedure

COMPOSITE INPUT LEVEL ADJUSTMENT
Apply the composite signal (from the FM demodulator)

with 100% modulation (25 kHz deviation) L + R;
fi= 300 Hz. Set input level control via the I2C-bus
monitoring line output (500 mV ±20 mV). Store the setting
in a non-volatile memory. Adjustment of the spectral and

TDA9855

wideband expander is performed via the stereo channel
separation adjust.

UTOMATIC ADJUSTMENT PROCEDURE

A

• Capacitors of external inputs EIL and EIR must be
grounded

• Composite input signal L = 300 Hz, R = 3.1 kHz,
14% modulation for each channel; volume gain +16 dB
via the I2C-bus; to avoid annoying sound level set GMU
bit to logic 1 during adjustment procedure

• Effects, AVL, loudness off

• Selector setting SC0, SC1 and SC2 = 0, 0, 0

(see Table 12)

• Line out setting bits: STEREO = 1, SAP = 0
(see Table 21)

• Start adjustment by transmission ADJ = 1 in register
ALI3; the decoder will align itself

• After 1 second, stop alignment by transmitting ADJ = 0
in register ALI3 read the alignment data by an I
read operation from ALR1 and ALR2
(see Chapter “I2C-bus protocol”) and store it in a
non-volatile memory; the alignment procedure
overwrites the previous data stored in ALI1 and ALI2

• Disconnect the capacitors of external inputs from
ground.

M

ANUAL ADJUSTMENT

Manual adjustment is necessary when no dual tone
generator is available (e.g. for service).

• Spectral and wideband data have to be set to 10000
(middle position for adjustment range)

• Composite input L = 300 Hz; 14% modulation

• Adjust channel separation by varying wideband data

• Composite input L = 3 kHz; 14% modulation

• Adjust channel separation by varying spectral data

• Iterative spectral/wideband operation for optimum

adjustment

• Store data in non-volatile memory.

After every power-on, the alignment data and the input
level adjustment data must be loaded from the non-volatile
memory.

T

IMING CURRENT FOR RELEASE RATE

Due to possible internal and external spreading, the timing
current can be adjusted via the I2C-bus (see Table 25) as
recommended by dbx.

2

C-bus

1997 Nov 04 11

Philips Semiconductors Product specification

I2C-bus controlled BTSC stereo/SAP

TDA9855

decoder and audio processor

Requirements for the composite input signal to ensure correct system performance

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

COMP

L+R(rms)

composite input level for 100%
modulation L + R;
25 kHz deviation;
fi= 300 Hz; RMS value

∆COMP composite input level

spreading under operating
conditions

Z

o

f

lf

f

hf

THD

L,R

output impedance note 1 − low-ohmic 5 kΩ
low frequency roll-off 25 kHz deviation L + R; −2dB −− 5Hz
high frequency roll-off 25 kHz deviation L + R; −2 dB 100 −−kHz
total harmonic distortion L + R fi= 1 kHz; 25 kHz deviation −− 0.5 %

S/N signal-to-noise ratio

L + R/noise

α

SB

side band suppression mono
into unmodulated SAP carrier;
SAP carrier/side band

α

SP

spectral spurious attenuation
L + R/spurious

measured at pin COMP 162 250 363 mV

T

= −20 to +70 °C; aging;

amb

−0.5 − +0.5 dB

power supply influence

f

= 1 kHz; 125 kHz deviation;

i

−− 1.5 %

note 2
CCIR 468-2 weighted quasi

peak; L + R; 25 kHz deviation;
f

= 1 kHz; 75 µs de-emphasis

i

critical picture modulation 44 −−dB
with sync only 54 −−dB

mono signal: 25 kHz deviation,

46 −−dB
fi= 1 kHz; side band: SAP
carrier frequency ±1 kHz

50 Hz to 100 kHz;

40 −−dB
mainly n × fH; no de-emphasis;
L + R; 25 kHz deviation,
f = 1 kHz as reference

Notes

1. Low-ohmic preferred, otherwise the signal loss and spreading at COMP, caused by Z

and the composite input

o

impedance (see Chapter “Characteristics”, Section INPUT LEVEL ADJUSTMENT CONTROL) must be taken into
account.

2. In order to prevent clipping at over-modulation (maximum deviation in the BTSC system for 100% modulation is
73 kHz).

1997 Nov 04 12

Philips Semiconductors Product specification

I2C-bus controlled BTSC stereo/SAP

TDA9855

decoder and audio processor

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CC

V

n

T

amb

T

stg

V

esd

Notes

1. Human body model: C = 100 pF; R = 1.5 kΩ.

2. Charge device model: C = 200 pF; R = 0 Ω.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

supply voltage 0 9.5 V
voltage of all other pins with respect to pin

GND
operating ambient temperature −20 +70 °C
storage temperature −65 +150 °C
electrostatic handling note 1 −2000 +2000 V

note 2 −300 +300 V

thermal resistance from junction to ambient in free air

SOT247-1 43 K/W
SOT188-2 38 K/W

0VCCV

1997 Nov 04 13

Philips Semiconductors Product specification

I2C-bus controlled BTSC stereo/SAP

TDA9855

decoder and audio processor

CHARACTERISTICS

All voltages are measured relative to GND; VCC= 8.5 V; source resistance Rs≤ 600 Ω; output load RL≥ 10 kΩ;
CL≤ 2.5 nF; AC-coupled; fi= 1 kHz; T
loudness off; AVL off; effects linear; composite input signal in accordance with BTSC standard; see Fig.1;
unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

General

V

CC

I

CC

V

DC

supply voltage 8.0 8.5 9.0 V
supply current 50 75 95 mA
DC voltage at signal handling

pins

Decoder section

I

NPUT LEVEL ADJUSTMENT CONTROL

G

G
V

LA

step

i(rms)

input level adjustment control maximum gain − 4.0 − dB

step resolution − 0.5 − dB
maximum input voltage level

(RMS value)

Z

i

input impedance 29.5 35 40.5 kΩ
STEREO DECODER
MPX

L+R(rms)

input voltage level for 100%

modulation L + R; 25 kHz

deviation (RMS value)
MPX

L−R

input voltage level for 100%

modulation L − R; 50 kHz

deviation (peak value)
MPX

(max)

maximum headroom for L + R,

L, R

MPX

pilot(rms)

nominal stereo pilot voltage

level (RMS value)
ST

on(rms)

pilot threshold voltage stereo

on (RMS value)
ST

off(rms)

pilot threshold voltage stereo

off (RMS value)
hys hysteresis − 2.5 − dB

OUT

L+R

output voltage level for 100%

modulation L + R at LINE OUT

=25°C; volume gain control Gc= 0 dB; bass linear; treble linear;

amb

−

1

⁄2V

CC

maximum attenuation −−3.5 − dB

2 −−V

input level adjusted via I2C-bus

− 250 − mV
(L + R; fi= 300 Hz);
monitoring line out

− 707 − mV

f

< 15 kHz; THD < 15% for

mod

9 −−dB
75 µs equivalent input
modulation

− 50 − mV

data STS = 1 −− 35 mV
data STS = 0 −− 30 mV
data STS = 1 15 −−mV
data STS = 0 10 −−mV

input level adjusted via I2C-bus

480 500 520 mV
(L + R; fi= 300 Hz);
monitoring LINE OUT

− V

1997 Nov 04 14

Philips Semiconductors Product specification

I2C-bus controlled BTSC stereo/SAP

TDA9855

decoder and audio processor

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

α

cs

f

L, R

THD

L,R

S/N signal-to-noise ratio mono mode; CCIR 468-2

TEREO DECODER, OSCILLATOR (VCXO); note 1

S
f

o

f

of

∆f

H

SAP DEMODULATOR; note 2
SAP

i(rms)

SAP

on(rms)

SAP

off(rms)

SAP

hys

SAP

LEV

f

res

THD total harmonic distortion f

stereo channel separation L/R
at LINE OUT

aligned with dual tone 14%
modulation; see Section
“Adjustment procedure” in
Chapter “Functional
description”

= 300 Hz; fR= 3 kHz 25 35 − dB

f

L

f

= 300 Hz; fR= 8 kHz 20 30 − dB

L

f

= 300 Hz; fR= 10 kHz 15 25 − dB

L

L, R frequency response 14% modulation;

f

= 300 Hz L or R

ref

=50Hzto11kHz −3 −−dB

f

i

f

= 12 kHz −−3 −dB

i

total harmonic distortion L, R
at LINE OUT

modulation L or R
1% to 100%; fi= 1 kHz

− 0.2 1.0 %

50 60 − dB
weighted; quasi peak;
500 mV output signal

nominal VCXO output
frequency (32fH)

spread of free-running
frequency

capture range frequency

with nominal ceramic
resonator

with nominal ceramic
resonator

− 503.5 − kHz

500.0 − 507.0 kHz

±190 ±265 − Hz

(nominal pilot)

nominal SAP carrier input
voltage level (RMS value)

pilot threshold voltage SAP on

15 kHz frequency deviation of
intercarrier

− 150 − mV

−− 85 mV

(RMS value)
pilot threshold voltage SAP off

35 −−mV

(RMS value)
hysteresis − 2 − dB
SAP output voltage level at

LINE OUT

LINE OUT (LOL, LOR) in
position SAP/SAP;
f

= 300 Hz;

mod

− 500 − mV

100% modulation

frequency response 14% modulation;

50 Hz to 8 kHz; f

= 1 kHz − 0.5 2.0 %

i

= 300 Hz

ref

−3 −−dB

1997 Nov 04 15

Philips Semiconductors Product specification

I2C-bus controlled BTSC stereo/SAP

TDA9855

decoder and audio processor

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

LINE OUT AT PINS LOL AND LOR
V

o(rms)

nominal output voltage
(RMS value)

HEAD

o

Z

o

V

O

R

L

C

L

α

ct

output headroom 9 −−dB
output impedance − 80 120 Ω
DC output voltage 0.45VCC0.5V
output load resistance 5 −−kΩ
output load capacitance −− 2.5 nF
idle crosstalk L, R into SAP 100% modulation; fi= 1 kHz;

idle crosstalk SAP into L, R 100% modulation; f

∆V

ST-SAP

output voltage difference if

switched from L, R to SAP
dbx NOISE REDUCTION CIRCUIT
t

adj

I

s

stereo adjustment time see Section “Adjustment

nominal timing current for

nominal release rate of

spectral RMS detector
∆I

s

I

s(range)

spread of timing current −− 15 %

timing current adjustment

range
I

t

timing current for release rate

of wideband RMS detector
Rel

rate

nominal RMS detector

release rate

100% modulation − 500 − mV

CC

0.55VCCV

50 −−dB
L or R; line out switched to
SAP/SAP

= 1 kHz;

i

50 −−dB
SAP; line out switched to
stereo

250 Hz to 6.3 kHz −− 3dB

−− 1s
procedure” in Chapter
“Functional description”

Is can be measured at pin 17

− 24 −µA
(pin 22) via current meter
connected to1⁄2VCC+1V

7 steps via I2C-bus −±30 − %

−

1

⁄3I

s

−µA

nominal timing current and
external capacitor values

wideband − 125 − dB/s
spectral − 381 − dB/s

1997 Nov 04 16