Philips TDA9852H, TDA9852 Datasheet

INTEGRATED CIRCUITS

DATA SH EET

TDA9852

C-bus controlled BTSC stereo/SAP decoder and audio processor

Preliminary speciﬁcation Supersedes data of 1996 Feb 28 File under Integrated Circuits, IC02

1997 Mar 11

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled BTSC stereo/SAP decoder and audio processor

FEATURES

• Quasi alignment-free application due to automatic adjustment of channel separation via I2C-bus

• High integration level with automatically tuned integrated filters

• Input level adjustment I2C-bus controlled

• Alignment-free SAP processing

• dbx noise reduction circuit

• Power supply

• I2C-bus transceiver.

Stereo decoder

• Stereo pilot PLL circuit with ceramic resonator, automatic adjustment procedure for stereo channel separation, two pilot thresholds selectable via I

Audio processor

C-bus.

TDA9852

GENERAL DESCRIPTION

The TDA9852 is a bipolar-integrated BTSC stereo decoder with hi-fi audio processor (I application in TV sets, VCRs and multimedia.

C-bus controlled) for

• Selector for internal and external signals (line in)

• Automatic volume level control (control range +6 to −15 dB)

• Interface for external noise reduction circuits

• Volume control (control range +16 to −71 dB)

• Special loudness characteristic automatically controlled

in combination with volume setting (control range 28 dB)

• Audio signal zero crossing detection between any volume step switching

• Mute control at audio signal zero crossing

• Mute control via I

ORDERING INFORMATION

TYPE

NUMBER

TDA9852 SDIP42 plastic shrink dual in-line package; 42 leads (600 mil) SOT270-1 TDA9852H QFP44

C-bus.

PACKAGE

NAME DESCRIPTION VERSION

plastic quad ﬂat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm

SOT307-2

1997 Mar 11 2

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled BTSC stereo/SAP

TDA9852

decoder and audio processor

LICENSE INFORMATION

A license is required for the use of this product. For further information, please contact

COMPANY BRANCH ADDRESS

THAT Corporation Licensing Operations 734 Forest St.

Marlborough, MA 01752 USA Tel.: (508) 229-2500 Fax: (508) 229-2590

Tokyo Ofﬁce 405 Palm House, 1-20-2 Honmachi

Shibuya-ku, Tokyo 151 Japan Tel.: (03) 3378-0915 Fax: (03) 3374-5191

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

comp(rms)

oR,L(rms)

THD V

I, O(rms)

AVL control range −15 − +6 dB G

S/N signal-to-noise ratio line out (mono); V

S/N signal-to-noise ratio audio section; V

supply voltage 8.0 8.5 9.0 V supply current − 75 95 mA input signal voltage (RMS value) 100% modulation L + R; fi= 300 Hz − 250 − mV output signal voltage (RMS value) 100% modulation L + R; fi= 300 Hz − 500 − mV input level adjustment control −3.5 − +4.0 dB stereo channel separation fL= 300 Hz; fR= 3 kHz 25 35 − dB total harmonic distortion L + R fi= 1 kHz − 0.2 − %

L,R

signal handling (RMS value) THD < 0.5% 2 −−V

volume control range −71 − +16 dB maximum loudness boost fi=40Hz − 17 − dB

= 0.5 V (RMS)

CCIR noise weighting filter

− 60 − dB

(peak value) DIN noise weighting filter

− 73 − dBA

(RMS value)

= 2 V (RMS);

gain = 0 dB

CCIR noise weighting filter

− 94 − dB

(peak value) DIN noise weighting filter

− 107 − dBA

(RMS value)

1997 Mar 11 3

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled BTSC stereo/SAP decoder and audio processor

BLOCK DIAGRAM

OUTR

(38)

OUT

RIGHT

C12

C11

C8C28

(EIR)

External Input Right

C20

C16

CERAMIC

41

40

VIR

39

C10

38

37

5

35

34

36

LIR

33

LOR

32

31

30

RESONATOR

MURATA

CSB503F58

29

28

27

26

(37)

(36)

RIGHT

VOLUME

LOUDNESS

(35) (34)

(33)

TDA9852

(44)

(31)

(30)

(32)

(29)

(28)

(27)

(26)

(25)

(24)

(23)

STEREO DECODER

(22)

CONTROL

ZERO

CROSSING

EFFECTS

AUTOMATIC

VOLUME AND

LEVEL CONTROL

INPUT

SELECT

LINEOUT

DEMATRIX

SAP

SWITCH

STEREO/

INPUT

LEVEL

ADJUST

(20)

COMP

OUTL

(40)

OUT

LEFT

LEFT

VOLUME

CONTROL

LOUDNESS

C

LOGIC

TRANSCEIVER

SUPPLY

ADJUST

STEREO

DBX

SAP

DEMODULATOR

(41)

(42)

(43) (18)

(17)

(1)

(21) (19) (3)

(4)

(2)

(5) (6)

(7) (8)

(9) (11)

(10)

(12)

(13)

(14)

(15) (16) (39) 20

25 23 8

10 11

12 13

14 16

MHA309

n.c.

C14

VIL

LIL

LOL

C29

C26

SDA SCL

C27

C19

C18C17

C30

C34

C15

C49

C47

C25

C24 C23

C22

C21

AGND DGND

(EIL)

External Input Left

TDA9852

handbook, full pagewidth

Fig.1 Block diagram.

The numbers given in parenthesis refer to the TDA9852H version.

1997 Mar 11 4

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled BTSC stereo/SAP

TDA9852

decoder and audio processor

Component list

Electrolytic capacitors ±20%; foil or ceramic capacitors ±10%; resistors ±5%; unless otherwise speciﬁed; see Fig.1.

COMPONENTS VALUE TYPE REMARK

C1 10 µF electrolytic 63 V C2 470 nF foil C3 4.7 µF electrolytic 63 V C4 220 nF foil C5 10 µF electrolytic 63 V; I C6 2.2 µF electrolytic 16 V C7 2.2 µF electrolytic 63 V C8 15 nF foil ±5%

C9 15 nF foil ±5% C10 2.2 µF electrolytic 16 V C11 8.2 nF foil or ceramic ±5% SMD 2220/1206 C12 150 nF foil ±5% C14 150 nF foil ±5% C15 100 µF electrolytic 16 V C16 4.7 µF electrolytic 63 V C17 4.7 µF electrolytic 63 V C18 100 nF foil C19 10 µF electrolytic 63 V C20 4.7 µF electrolytic 63 V C21 47 nF foil ±5% C22 1 µF electrolytic 63 V C23 1 µF electrolytic 63 V C24 10 µF electrolytic 63 V ±10% C25 10 µF electrolytic 63 V ±10% C26 2.2 µF electrolytic 16 V C27 2.2 µF electrolytic 63 V C28 4.7 µF electrolytic 63 V ±10% C29 2.2 µF electrolytic 16 V C30 8.2 nF foil or ceramic ±5% SMD 2220/1206 C34 100 µF electrolytic 16 V C47 220 µF electrolytic 25 V C49 100 nF foil or ceramic SMD 1206

R1 2.2 kΩ−

R2 20 kΩ−

R3 2.2 kΩ−

R4 20 kΩ−

R5 2.2 kΩ−

R6 8.2 kΩ− ±2%

leak

< 1.5 µA

1997 Mar 11 5

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled BTSC stereo/SAP decoder and audio processor

COMPONENTS VALUE TYPE REMARK

R7 160Ω− ±2%

Q1 CSB503F58 radial leads

CSB503JF958 alternative as SMD

PINNING

SYMBOL

SDIP42 QFP44

OUTL 1 40 output, left channel LDL 2 41 input loudness, left channel VIL 3 42 input volume, left channel EOL 4 43 output effects, left channel C

ref

5 44 automatic volume control capacitor

6 1 reference voltage 0.5V LIL 7 2 input line control, left channel AVL 8 3 input automatic volume control, left channel SOL 9 4 output selector, left channel LOL 10 5 output line control, left channel C

11 6 capacitor timing wideband for dbx 12 7 capacitor timing spectral for dbx 13 8 capacitor wideband for dbx

14 9 capacitor spectral for dbx VEO 15 10 variable emphasis output for dbx VEI 16 11 variable emphasis input for dbx C

DEC

17 12 capacitor noise reduction for dbx

18 13 capacitor mute for SAP

19 14 capacitor DC-decoupling for SAP GND 20 − ground AGND − 15 analog ground DGND − 16 digital ground SDA 21 17 serial data input/output (I SCL 22 18 serial clock input (I V

23 19 supply voltage COMP 24 20 composite input signal V C C C C

CAP

P1 P2 PH ADJ

25 21 capacitor for electronic ﬁltering of supply

26 22 capacitor for pilot detector

27 23 capacitor for pilot detector

28 24 capacitor for phase detector

29 25 capacitor for ﬁlter adjustment CER 30 26 ceramic resonator C

31 27 capacitor DC-decoupling mono

PINS

DESCRIPTION

C-bus)

TDA9852

1997 Mar 11 6

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled BTSC stereo/SAP

TDA9852

decoder and audio processor

SYMBOL

SDIP42 QFP44

32 28 capacitor DC-decoupling stereo/SAP LOR 33 29 output line control, right channel SOR 34 30 output selector, right channel AVR 35 31 input automatic volume control, right channel LIR 36 32 input line control, right channel C

PS2

PS1

37 33 capacitor 2 pseudo function

38 34 capacitor 1 pseudo function EOR 39 35 output effects, right channel VIR 40 36 input volume, right channel LDR 41 37 input loudness, right channel OUTR 42 38 output, right channel n.c. − 39 not connected

PINS

DESCRIPTION

handbook, full pagewidth

AVL

SOL

LOL

VEO

VEI

ref

LIL

CAVEOL 44

1 2 3 4 5 6 7 8

10 11

VIL

LDL

OUTL

n.c.

OUTR

LDR

VIR

TDA9852H

DEC

AGND

DGND

SDA

SCL

COMP

EOR

CAP

PS1

33 32 31 30 29 28 27 26 25 24 23

MHA696

PS2

LIR AVR SOR LOR C

CER C

ADJ

Fig.2 Pin configuration (QFP-version).

1997 Mar 11 7

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled BTSC stereo/SAP decoder and audio processor

handbook, halfpage

OUTL

LDL

EOL C

AVL

SOL

LOL

VEO

VEI

DEC

GND

SDA

VIL

ref

LIL

NR C

1 2 3 4 5 6 7 8

9 10 11

TDA9852

12 13

15 16 17 18

19 20

MHA310

42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 2221

OUTR LDR VIR EOR C

PS1

PS2

LIR AVR SOR LOR C

CER C

ADJ

CAP

COMP V

SCL

TDA9852

FUNCTIONAL DESCRIPTION Stereo decoder

NPUT LEVEL ADJUSTMENT

I The composite input signal is fed to the input level

adjustment stage. The control range is from

−3.5 to +4.0 dB in steps of 0.5 dB. The subaddress control 3 of Tables 5 and 6 and the level adjust setting of Table 21 allows an optimum signal adjustment during the set alignment. The maximum input signal voltage is 2 V (RMS).

TEREO DECODER

S The output signal of the level adjustment stage is coupled

to a low-pass filter which suppresses the baseband noise above 125 kHz. The composite signal is then fed into a pilot detector/pilot cancellation circuit and into the MPX demodulator. The main L + R signal passes a 75 µs fixed de-emphasis filter and is fed into the dematrix circuit. The decoded sub-signal L − R is sent to the stereo/SAP switch. To generate the pilot signal the stereo demodulator uses a PLL circuit including a ceramic resonator. The stereo channel separation is adjusted by an automatic procedure to be performed during set production. For a detailed description see Section “Adjustment procedure”. The stereo identification can be read by the I2C-bus (see Table 2). Two different pilot thresholds (data STS = 1; STS = 0) can be selected via the I2C-bus (see Table 19).

DEMODULATOR

SAP The composite signal is fed from the output of the input

level adjustment stage to the SAP demodulator circuit through a 5fH (fH= horizontal frequency) band-pass filter. The demodulator level is automatically controlled. The SAP demodulator includes internal noise and field strength detectors that mute the SAP output in the event of insufficient signal conditions. The SAP identification signal can be read by the I2C-bus (see Table 2).

Fig.3 Pin configuration (SDIP-version).

1997 Mar 11 8

WITCH

S The stereo/SAP switch feeds either the L − R signal or the

SAP demodulator output signal via the internal dbx noise reduction circuit to the dematrix/switching circuit. Table 12 shows the different switch modes provided at the output pins LOR and LOL.

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled BTSC stereo/SAP decoder and audio processor

dbx DECODER The circuit includes all blocks required for the noise

reduction system in accordance with the BTSC system specification. The output signal is fed through a 73 µs fixed de-emphasis circuit to the dematrix block.

NTEGRATED FILTERS

The filter functions necessary for stereo and SAP demodulation and part of the dbx filter circuits are provided on-chip using transconductor circuits. The required filter accuracy is attained by an automatic filter alignment circuit.

Audio processor

ELECTOR

S The selector allows selecting either the internal line out

signals LOR or LOL (dematrix output) or the external line in signals LIR and LIL and combines the left and right signals in several modes (see Tables 5 and 6 for subaddress and Table 11 for data). The input signal capability of the line inputs (LIR/LIL) is 2 V (RMS). The output of the selector is AC-coupled to the automatic volume level control circuit via pins SOR/SOL and AVR/AVL to avoid offset voltages.

UTOMATIC VOLUME LEVEL CONTROL

A The automatic volume level stage controls its output

voltage to a constant level of typically 200 mV (RMS) from an input voltage range of 0.1 to 1.1 V (RMS). The circuit adjusts variations in modulation during broadcasting and due to changes in the programme material. The function can be switched off. To avoid audible ‘plops’ during the permanent operation of the AVL circuit a soft blending scheme has been applied between the different gain stages. A capacitor (4.7 µF) at pin CAV determines the attack and decay time constants. In addition the ratio of attack and decay time can be changed via I2C-bus (see Table 15). At power on, the discharged 4.7 µF capacitor at CAV must be loaded by the internal decay current. If AVL is chosen, this would result in an attenuated AVL gain for about 10 seconds after poweron. This can be speeded up by choosing via I2C-bus an increased charge current (about 10 times higher) for about the first 2 seconds after power on (see Table 6, CCD bit in control 1 and Table 18).

TDA9852

FFECTS

The audio processor section offers the following mode selections: linear stereo, pseudo stereo, spatial stereo and forced mono.The spatial mode provides an antiphase crosstalk of 30% or 52% (switchable via I2C-bus; see Table 10).

OLUME/LOUDNESS

The volume control range is from +16 dB to −71 dB in steps of 1 dB and ends with a mute step (see Table 8). Balance control is achieved by the independent volume control of each channel. The volume control blocks operate in combination with the loudness control. The filter is linear when maximum gain for volume control is selected. The filter characteristic changes automatically over a range of 28 dB down to a setting of −12 dB. At −12 dB volume control the maximum loudness boost is obtained. The filter characteristic is determined by external components. The proposed application provides a maximum boost of 17 dB for bass and 4.5 dB for treble. The loudness may be switched on or off via I2C-bus control (see Table 9). The left and right volume control stages include two independent zero crossing detectors. A change in volume is automatically activated but not executed. The execution is enabled at the next zero crossing of the signal. If a new volume step is activated before the previous one has been processed, the previous value will be executed first, and then the new value will be activated. If no zero crossing occurs the next volume transmission will enforce the last activated volume setting.

The zero crossing is realized between adjoining steps and between any steps, but not from any step to mute. In this case the GMU bit is needed to use. In case only one channel has to be muted, two steps are necessary. The first step is a transmission of any step to −71 dB and the second step is the−71 dB step to mute mode. The step of −71 dB to mute mode has no zero crossing but this is not relevant.

1997 Mar 11 9

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled BTSC stereo/SAP decoder and audio processor

MUTE The mute function can be activated independently with last

step of volume control at the left or right output. By setting the general mute bit GMU via the I2C-bus all outputs are muted. All channels include an independent zero cross detector. The zero crossing mute feature can be selected via bit TZCM:

TZCM = 0: forced mute with direct execution TZCM = 1: execution in time with signal zero crossing.

In the zero cross mode a change in the GMU polarity is activated but not executed. The execution is enabled at the next zero crossing of the signal. To avoid a large delay of mute switching, when very low frequencies are processed, or the output signal amplitude is lower than the DC offset voltage, the following I needed:

a first transmission for mute execution a second transmission about 100 ms later, which must

switch the zero crossing mode to forced mute (TZCM = 0)

a third transmission to reactivate the zero crossing mode (TZCM = 1). This transmission can take place immediately, but must follow before the next mute execution.

Adjustment procedure

COMPOSITE INPUT LEVEL ADJUSTMENT Feed in from FM demodulator the composite signal with

100% modulation (25 kHz deviation) L + R; fi= 300 Hz. Set input level control via I2C-bus monitoring line out (500 mV ±20 mV). Store the setting in a non-volatile memory.

UTOMATIC ADJUSTMENT PROCEDURE

C-bus transmissions are

TDA9852

• Effects, AVL, loudness off.

• Line out setting bits: STEREO = 1, SAP = 0

(see Table 12)

• Selector setting SC0, SC1, SC2 = 0, 0, 0 (see Table 11)

• Start adjustment by transmission ADJ = 1 in register

ALI3; the decoder will align itself

• After 1 second minimum stop alignment by transmitting ADJ = 0 in register ALI3 read the alignment data by an

C-bus read operation from ALR1 and ALR2 (see Chapter “I2C-bus protocol”) and store it in a non-volatile memory; the alignment procedure overwrites the previous data stored in ALI1 and ALI2

• Disconnect the capacitors of external inputs from ground.

ANUAL ADJUSTMENT

Manual adjustment is necessary when no dual tone generator is available (e.g. for service).

• Spectral and wideband data have to be set to 10000 (middle position for adjustment range)

• Composite input L = 300 Hz; 14% modulation

• Adjust channel separation by varying wideband data

• Composite input L = 3 kHz; 14% modulation

• Adjust channel separation by varying spectral data

• Iterative spectral/wideband operation for optimum

adjustment

• Store data in non-volatile memory.

IMING CURRENT FOR RELEASE RATE

T Due to possible internal and external spreading, the timing

current can be adjusted via I2C-bus, see Table 20, as recommended by dbx.

• Capacitors of external inputs LIL and LIR must be grounded at EIL and EIR

• Composite input signal L = 300 Hz, R = 3.1 kHz, 14% modulation for each channel; volume gain +16 dB via I2C-bus

1997 Mar 11 10

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled BTSC stereo/SAP

TDA9852

decoder and audio processor

Requirements for the composite input signal to ensure correct system performance

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

COMP

L+R(rms)

composite input level for 100% modulation L + R; 25 kHz deviation; fi= 300 Hz; RMS value

∆COMP composite input level

spreading under operating conditions

THD

L,R

output impedance note 1 − low-ohmic 5 kΩ low frequency roll-off 25 kHz deviation L + R; −2dB −− 5Hz high frequency roll-off 25 kHz deviation L + R; −2 dB 100 −−kHz total harmonic distortion L + R fi= 1 kHz; 25 kHz deviation −− 0.5 %

S/N signal-to-noise ratio

L + R/noise

side band suppression mono into unmodulated SAP carrier; SAP carrier/side band

spectral spurious attenuation L + R/spurious

measured at COMP 162 250 363 mV

= −20 to +70 °C; aging;

amb

−0.5 − +0.5 dB

power supply inﬂuence

= 1 kHz; 125 kHz deviation;

−− 1.5 %

note 2 CCIR 468-2 weighted quasi

peak; L + R; 25 kHz deviation;

= 1 kHz; 75 µs de-emphasis

critical picture modulation;

44 −−dB

note 3 with sync only 54 −−dB

mono signal: 25 kHz deviation,

46 −−dB fi= 1 kHz; side band: SAP carrier frequency ±1 kHz

50 Hz to 100 kHz; mainly n × fH; no de-emphasis; L + R; 25 kHz deviation, f = 1 kHz as reference

n = 1, 5 35 −−dB n = 4, 6 40 −−dB n = 2, 3 26 −−dB

Notes

1. Low-ohmic preferred, otherwise the signal loss and spreading at COMP, caused by Z

and the composite input

impedance (see Chapter “Characteristics”, Section “Input level adjustment control”) must be taken into account.

2. In order to prevent clipping at over-modulation (maximum deviation in the BTSC system for 100% modulation is 73 kHz).

3. For example colour bar or flat field white; 100% video modulation.

1997 Mar 11 11

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled BTSC stereo/SAP

TDA9852

decoder and audio processor

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER MIN. MAX. UNIT

amb

stg

Note

1. Human body model: C = 100 pF; R = 1.5 kΩ; V = 2 kV; Charge device model: C = 200 pF; R = 0 Ω; V = 300 V.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

th j-a

supply voltage 0 9.5 V voltage of all other pins to pin V

0VCCV operating ambient temperature −20 +70 °C storage temperature −65 +150 °C electrostatic handling; note 1

thermal resistance from junction to ambient in free air

SOT270-1 43 K/W SOT307-2 60 K/W

1997 Mar 11 12

+ 28 hidden pages