Philips TDA8793HL Datasheet
INTEGRATED CIRCUITS
DATA SH EET
TDA8793
8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)
Product specification
Supersedes data of 1999 Oct 06
File under Integrated Circuits, IC02
2000 Nov 20
Philips Semiconductors Product specification
8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)
FEATURES
• 8-bit low-power ADC: 180 mW (typical value)
• 2.7 to 3.6 V operation
• Track-and-hold circuit
• In track-and-hold mode: sampling rate from
70 to 100 Msps
• In non track-and-hold mode: sampling rate from
1 sps to 100 Msps
• CMOS/TTL compatible digital inputs and outputs
• Internal reference voltages
• Adjustable full-scale range possibility with external
reference
• Power-down mode: 5 mW.
APPLICATIONS
• Radio communications
• Digital data storage read channels
• Medical imaging
• Digital instrumentation.
TDA8793
GENERAL DESCRIPTION
The TDA8793 is an 8-bit low-power Analog-to-Digital
Converter (ADC) which includes a track-and-hold circuit
and internal references. The device converts an analog
input signal, up to 100 MHz, into 8-bit binary codes at a
maximum sample rate of 100 Msps. All digital inputs and
outputs are CMOS/TTL compatible. A sine wave clock
input signal can also be used.
The Power-down mode enables the device power
consumption to be reduced to 5 mW.
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
V
V
I
CCA
CCA
CCD
CCO
analog supply voltage 2.7 3.0 3.6 V
digital supply voltage 2.7 3.0 3.6 V
output stages supply voltage 2.7 3.0 3.6 V
analog supply current operating 32 40 48 mA
standby 0 2 100 µA
I
CCD
digital supply current operating 12 16 24 mA
standby 0 0.66 1.1 mA
I
CCO
INL integral non-linearity ramp input; f
DNL differential non-linearity ramp input; f
f
CLK(max)
P
tot
output stages supply current ramp input − 4 6.5 mA
V
CCA=VCCD
V
CCA=VCCD
CLK
=3V
CLK
=3V
= 2 MHz;
= 2 MHz;
−±0.85 ±1.70 LSB
−±0.25 ±0.80 LSB
maximum clock input frequency 100 −−MHz
total power dissipation VCC=3V − 180 − mW
ORDERING INFORMATION
TYPE
NUMBER
NAME DESCRIPTION VERSION
PACKAGE
TDA8793HL LQFP32 plastic low profile quad flat package; 32 leads; body 5 × 5 × 1.4 mm SOT401-1
2000 Nov 20 2
Philips Semiconductors Product specification
8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)
BLOCK DIAGRAM
handbook, full pagewidth
INP
INN
REFOUT
REFIN
4
3
5
2
TEN
12
TRACK-AND-
HOLD
V
CCA
TDA8793
V
7
V
CCD
CCO2
10
ADC
CLOCK DRIVER
V
22
LATCHES
CCO1
20
CMOS
OUTPUTS
26
D7
25
D6
24
D5
23
D4
18
D3
17
D2
16
D1
15
D0
11
CLK
SDN
STDBY
32
8
REFERENCE
VOLTAGES
31
DEC
TDA8793
6
AGND
9
DGND
Fig.1 Block diagram.
21
OGND119OGND2
MGR016
2000 Nov 20 3
Philips Semiconductors Product specification
8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)
PINNING
SYMBOL PIN DESCRIPTION
n.c. 1 not connected
REFIN 2 reference input for ADC
INN 3 negative input
INP 4 positive input
REFOUT 5 reference output for AC coupling of
input
AGND 6 analog ground
V
CCA
STDBY 8 standby mode input
DGND 9 digital ground
V
CCD
CLK 11 clock input
TEN 12 track enable input (active LOW)
n.c. 13 not connected
n.c. 14 not connected
D0 15 data output bit 0 (LSB)
D1 16 data output bit 1
7 analog supply voltage
10 digital supply voltage
TDA8793
SYMBOL PIN DESCRIPTION
D2 17 data output bit 2
D3 18 data output bit 3
OGND1 19 output ground 1
V
CCO1
OGND2 21 output ground 2
V
CCO2
D4 23 data output bit 4
D5 24 data output bit 5
D6 25 data output bit 6
D7 26 data output bit 7 (MSB)
n.c. 27 not connected
n.c. 28 not connected
n.c. 29 not connected
n.c. 30 not connected
DEC 31 decoupling
SDN 32 stabilized decoupling node output
20 output supply voltage 1
22 output supply voltage 2
handbook, full pagewidth
n.c.
REFIN
INN
INP
1
2
3
4
SDN
32
DEC
31
n.c.
30
n.c.
29
TDA8793
AGND
V
CCA
5
6
7
8
9
DGND
10
CCD
V
11
CLK
12
TEN
REFOUT
STDBY
Fig.2 Pin configuration.
2000 Nov 20 4
n.c.
28
13
n.c.
n.c.
27
14
n.c.
D7
26
15
D0
D6
25
16
D1
24
23
22
21
20
19
18
17
MGR017
D5
D4
V
CCO2
OGND2
V
CCO1
OGND1
D3
D2
Philips Semiconductors Product specification
8-bit, low-power, 3 V, 100 Msps
TDA8793
Analog-to-Digital Converter (ADC)
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
V
V
∆V
V
I
O
T
T
CCA
CCD
CCO
CC
n
stg
amb
analog supply voltage note 1 −0.3 +5.0 V
digital supply voltage note 1 −0.3 +5.0 V
output stages supply voltage note 1 −0.3 +5.0 V
supply voltage differences between
V
V
V
CCA
CCO
CCA
and V
and V
and V
CCD
CCD
CCO
−1.0 +1.0 V
−1.0 +1.0 V
−1.0 +1.0 V
voltage on pins
INP, INN, CLK,
TEN and STDBY note 2 −0.3 +4.5 V
REFIN −0.3 +4.5 V
output current − 10 mA
storage temperature −55 +150 °C
ambient temperature 0 70 °C
Notes
1. The supply voltages V
CCA
, V
CCD
, V
may have any value between −0.3 and +5.0 V provided that the supply
CCO
voltage differences ∆VCC are respected.
2. All voltages are typical values and are referenced to all ground pins connected together.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS VALUE UNIT
R
th(j-a)
thermal resistance from junction to ambient in free air 94 K/W
2000 Nov 20 5
Philips Semiconductors Product specification
8-bit, low-power, 3 V, 100 Msps
TDA8793
Analog-to-Digital Converter (ADC)
CHARACTERISTICS
V
CCA=V7
DGND and OGND shorted together; V
V
CCA
T
amb
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies
V
CCA
V
CCD
V
CCO
I
CCA
I
CCD
I
CCO
Internal reference voltage output (pin SDN); note 1
V
ref
V
reg
TC temperature coefficient − 20 − ppm/K
I
L
Internal reference voltage output (pin REFOUT)
V
ref
V
reg
TC temperature coefficient − 20 − ppm/K
I
L
Clock input (pin CLK); note 2
V
IL
V
IH
I
IL
I
IH
Z
i
C
i
Standby input (pin STDBY); see Table 1
V
IL
V
IH
I
IL
I
IH
Track enable input (pin TEN); see Table 2
V
IL
V
IH
I
IL
I
IH
to V6= 2.7 to 3.6 V; V
to V
= −0.15 to +0.15 V; T
CCO
CCD=V10
amb
to V9= 2.7 to 3.6 V; V
CCA
to V
= −0.15 to +0.15 V; V
CCD
= 0 to 70 °C; typical values measured at V
=25°C; single-ended input; unless otherwise specified.
analog supply voltage 2.7 3.0 3.6 V
digital supply voltage 2.7 3.0 3.6 V
output stages supply voltage 2.7 3.0 3.6 V
analog supply current 32 40 48 mA
digital supply current 12 16 24 mA
output stages supply current ramp input − 4 6.5 mA
f
= 20 MHz − 8.7 12 mA
i
reference voltage 1.21 1.26 1.31 V
line regulation voltage 2.7 < V
CCA
load current −1 −−mA
reference voltage 1.76 1.84 1.92 V
line regulation voltage 2.7 < V
CCA
load current −1 −−mA
LOW-level input voltage 0 − 0.8 V
HIGH-level input voltage 2 − V
LOW-level input current V
HIGH-level input current V
input impedance f
input capacitance f
=0 −2 − +2 µA
CLK
CLK=VCCD
= 100 MHz − 32 − kΩ
CLK
= 100 MHz − 2 − pF
CLK
LOW-level input voltage 0 − 0.8 V
HIGH-level input voltage 2 − V
LOW-level input current V
HIGH-level input current V
=0 −5 −−µA
STDBY
STDBY=VCCD
LOW-level input voltage 0 − 0.8 V
HIGH-level input voltage 2 − V
LOW-level input current V
HIGH-level input current V
=0 −5 −−µA
TEN
TEN=VCCD
CCO=V20
to V19 and V22to V21= 2.7 to 3.6 V; AGND,
CCD
to V
= −0.15 to +0.15 V;
CCO
CCA=VCCD=VCCO
= 3.0 V and
< 3.6 V − 1.25 4 mV
< 3.6 V − 1.5 5 mV
CCD
V
−−5µA
CCD
V
−−5µA
CCD
V
−−5µA
2000 Nov 20 6
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