Philips TDA8792M-C2-R1, TDA8792M-C2, TDA8792M-C1 Datasheet

INTEGRATED CIRCUITS

TDA8792

3.3 V, 25 MHz 8-bit analog-to-digital converter (ADC)

Product specification

1996 Feb 21

Supersedes data of 1995 Apr 26

File under Integrated Circuits, IC02

Philips Semiconductors	Product specification

3.3 V, 25 MHz 8-bit

TDA8792

analog-to-digital converter (ADC)

FEATURES

∙8-bit resolution

∙Sampling rate up to 25 MHz

∙30 MHz input signal bandwidth (full scale)

∙High signal-to-noise ratio over a large analog input frequency range (7.3 effective bits at 4.43 MHz full-scale input at fclk = 25 MHz)

∙CMOS compatible digital inputs

∙External reference voltage regulator

∙Power dissipation only 53 mW (typical)

∙Standby mode (only 1.2 mW typical)

∙Low analog input capacitance, no buffer amplifier required

∙No sample-and-hold circuit required.

APPLICATIONS

Analog-to-digital conversion for:

∙General purpose

∙Hand-held equipment

∙Mobile telecommunication

∙Instrumentation

∙Video.

GENERAL DESCRIPTION

The TDA8792 is a 8-bit analog-to-digital converter (ADC) for low-voltage, portable applications. It operates at 3.3 V and converts the analog input signal into 8-bit binary-coded digital words at a maximum sampling rate of 25 MHz. The output data is valid after a delay of 6 clock cycles.

QUICK REFERENCE DATA

SYMBOL	PARAMETER		CONDITIONS	MIN.	TYP.	MAX.	UNIT
VDDA	analog supply voltage			2.85	3.3	3.6	V
VDDD	digital supply voltage			2.70	3.3	3.6	V
VDDO	output stages supply voltage			2.5	3.3	3.6	V
IDDA	analog supply current			−	12	20	mA
IDDD	digital supply current			−	3	6	mA
IDDO	output stages supply current	fclk = 25	MHz; CL = 15 pF;	−	1	2	mA
		ramp input
INL	integral non-linearity	fclk = 25	MHz; ramp input	−	±0.4	±0.8	LSB
DNL	differential non-linearity	fclk = 25	MHz; ramp input	−	±0.3	±0.75	LSB
fclk(max)	maximum clock frequency			25	−	−	MHz
Ptot	total power dissipation	fclk = 25	MHz; CL = 15 pF;	−	53	100	mW
		ramp input

ORDERING INFORMATION

TYPE		PACKAGE
NUMBER	NAME	DESCRIPTION	VERSION
TDA8792M	SSOP24	plastic shrink small outline package; 24 leads; body width 5.3 mm	SOT340-1

1996 Feb 21

2

Philips Semiconductors	Product specification

3.3 V, 25 MHz 8-bit

TDA8792

analog-to-digital converter (ADC)

BLOCK DIAGRAM

dbook, full pagewidth
STDBY	1				24		CLK
VDDD					23		VSSO
	2			TDA8792
					22
							VDDO
VSSD2	3
VSSA1	4				21	D7	MSB
VI	5				20	D6
		7 x 8
				8
		OFFSET	DECODER		19	D5
VDDA
	6	COMPENSATED	LATCHES
		COMPARATORS
I bias	7				18	D4
				OUTPUT
							data outputs
				BUFFER
					17	D3
V RT	8
VRM	9				16	D2
		REFERENCE
		LADDER			15	D1
VRB	10
			DAC
					14	D0	LSB
VSSA2 12					13	OE
					MLD119 - 1

Fig.1 Block diagram.

1996 Feb 21

3

Philips Semiconductors	Product specification

3.3 V, 25 MHz 8-bit

TDA8792

analog-to-digital converter (ADC)

PINNING

	SYMBOL		PIN	DESCRIPTION
	STDBY		1	standby input
	VDDD		2	digital supply voltage (+3.3 V)
	VSSD2		3	digital ground 2
	VSSA1		4	analog ground 1
	VI		5	analog input voltage
	VDDA		6	analog supply voltage (+3.3 V)
	Ibias		7	bias current input
	VRT		8	reference voltage TOP input
	VRM		9	reference voltage MIDDLE
	VRB		10	reference voltage BOTTOM input
	n.c.		11	not connected
	VSSA2		12	analog ground 2
				output enable input (CMOS level
	OE		13
				input, active LOW)
	D0		14	data output; bit 0 (LSB)
	D1		15	data output; bit 1
	D2		16	data output; bit 2
	D3		17	data output; bit 3
	D4		18	data output; bit 4
	D5		19	data output; bit 5
	D6		20	data output; bit 6
	D7		21	data output; bit 7 (MSB)
	VDDO		22	positive supply voltage for output
				stage (+3.3 V)
	VSSO		23	output ground
	CLK		24	clock input

handbook, halfpage

STDBY	1			24		CLK
VDDD	2		23				VSSO
VSSD2	3		22				VDDO
VSSA1	4		21			D7
VI	5		20			D6
						D5
V DDA	6			19
			TDA8792
I bias	7			18		D4
VRT	8			17		D3
VRM						D2
	9			16
V RB						D1
	10			15
n.c.						D0
	11			14
VSSA2
	12			13		OE
			MLD120 - 1

Fig.2 Pin configuration.

1996 Feb 21

4

Philips Semiconductors	Product specification

3.3 V, 25 MHz 8-bit

TDA8792

analog-to-digital converter (ADC)

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL	PARAMETER	CONDITIONS	MIN.	MAX.	UNIT
VDDA	analog supply voltage	note 1	−0.5	+5.0	V
VDDD	digital supply voltage	note 1	−0.5	+5.0	V
VDDO	output stages supply voltage	note 1	−0.5	+5.0	V
VDD1	supply voltage differences between		−0.3	+0.3	V
	VDD1 = VDDA − VDDD
VDD2	supply voltage differences between		−1.0	+1.0	V
	VDD2 = VDDD − VDDO
VDD3	supply voltage differences between		−1.0	+1.0	V
	VDD3 = VDDA − VDDO
VI	input voltage	referenced to VSSA	−0.5	+5.0	V
Vclk(p-p)	AC input voltage for switching	referenced to VSSD	−	VDDD	V
	(peak-to-peak value)
IO	output current		−	10	mA
Tstg	storage temperature		−55	+150	°C
Tamb	operating ambient temperature		−20	+75	°C
Tj	junction temperature		−	+125	°C

Note

1.The supply voltages VDDA, VDDD and VDDO may have any value between −0.5 V and +5.0 V provided that the differences VDD1, VDD2 and VDD3 are respected.

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL	PARAMETER	VALUE	UNIT
Rth j-a	thermal resistance from junction to ambient in free air	119	K/W

1996 Feb 21

5

Philips Semiconductors	Product specification

3.3 V, 25 MHz 8-bit

TDA8792

analog-to-digital converter (ADC)

CHARACTERISTICS

VDDA = V6 to V4,12 = 2.85 to 3.6 V; VDDD = V2 to V3 and V1 = 2.7 to 3.6 V; VDDO = V22 to V23 = 2.5 to 3.6 V;

VSSA, VSSD and VSSO shorted together; VDDA to VDDD = −0.15 to +0.15 V; fclk = 25 MHz; 50% duty factor; VIL = 0 V; VIH = VDDD; CL = 15 pF; Tamb = 0 to +70 °C; typical values measured at VDDA = VDDD = VDDO = 3.3 V and Tamb = 25 °C; unless otherwise specified.

SYMBOL		PARAMETER		CONDITIONS	MIN.	TYP.	MAX.	UNIT
Supply
VDDA		analog supply voltage			2.85	3.3	3.6	V
VDDD		digital supply voltage			2.7	3.3	3.6	V
VDDO		output stages supply voltage			2.5	3.3	3.6	V
IDDA		analog supply current			−	12	20	mA
IDDD		digital supply current			−	3	6	mA
IDDO		output stages supply current	CL = 15 pF; ramp input		−	1	2	mA
Inputs
CLOCK INPUT CLK (REFERENCED TO VSSD); note 1
VIL		LOW level input voltage			0	−	0.8	V
VIH		HIGH level input voltage			2.0	−	VDDD	V
IIL		LOW level input current	Vclk	= 0.4 V	−10	−	−	μA
IIH		HIGH level input current	Vclk	= 2.7 V	−	−	10	μA
CI		input capacitance			−	10	−	pF
INPUTS		AND STDBY (REFERENCED TO VSSD); see Tables 2 and 3
	OE
VIL		LOW level input voltage			0	−	0.8	V
VIH		HIGH level input voltage			2.0	−	VDDD	V
IIL		LOW level input current	VIL = 0.4 V		−10	−	−	μA
IIH		HIGH level input current	VIH = 2.7 V		−	−	+10	μA
VI (ANALOG INPUT VOLTAGE REFERENCED TO VSSA)
IIL		LOW level input current	VI = 0 V		−20	−	−	μA
IIH		HIGH level input current	VI = 1.5 V		−	−	+20	μA
ZI		input impedance	fi = 4.43 MHz		−	35	−	kΩ
CI		input capacitance	fi = 4.43 MHz		−	5	−	pF
Reference voltages for the resistor ladder; see Table 1
VRB		reference voltage BOTTOM			0	−	0.15	V
VRT		reference voltage TOP			1.4	−	1.6	V
Vdiff		differential reference voltage VRT − VRB			1.25	1.5	1.6	V
Iref		reference current			−	1.3	−	mA
RLAD		resistor ladder			−	1250	−	Ω
TCRLAD		temperature coefficient of the resistor			−	1	−	Ω/K
		ladder

1996 Feb 21

6