Philips tda8792 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

TDA8792

3.3 V, 25 MHz 8-bit analog-to-digital converter (ADC)

Product speciﬁcation Supersedes data of 1995 Apr 26 File under Integrated Circuits, IC02

1996 Feb 21

Philips Semiconductors Product speciﬁcation

3.3 V, 25 MHz 8-bit analog-to-digital converter (ADC)

FEATURES

• 8-bit resolution

• Sampling rate up to 25 MHz

• 30 MHz input signal bandwidth (full scale)

• High signal-to-noise ratio over a large analog input

frequency range (7.3 effective bits at 4.43 MHz full-scale input at f

• CMOS compatible digital inputs

• External reference voltage regulator

• Power dissipation only 53 mW (typical)

• Standby mode (only 1.2 mW typical)

• Low analog input capacitance, no buffer amplifier

required

• No sample-and-hold circuit required.

QUICK REFERENCE DATA

= 25 MHz)

clk

TDA8792

APPLICATIONS

Analog-to-digital conversion for:

• General purpose

• Hand-held equipment

• Mobile telecommunication

• Instrumentation

• Video.

GENERAL DESCRIPTION

The TDA8792 is a 8-bit analog-to-digital converter (ADC) for low-voltage, portable applications. It operates at 3.3 V and converts the analog input signal into 8-bit binary-coded digital words at a maximum sampling rate of 25 MHz. The output data is valid after a delay of 6 clock cycles.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DDA

V

DDD

V

DDO

I

DDA

I

DDD

I

DDO

analog supply voltage 2.85 3.3 3.6 V digital supply voltage 2.70 3.3 3.6 V output stages supply voltage 2.5 3.3 3.6 V analog supply current − 12 20 mA digital supply current − 36mA output stages supply current f

= 25 MHz; CL= 15 pF;

clk

− 12mA

ramp input INL integral non-linearity f DNL differential non-linearity f f

clk(max)

P

tot

maximum clock frequency 25 −−MHz total power dissipation f

= 25 MHz; ramp input −±0.4 ±0.8 LSB

clk

= 25 MHz; ramp input −±0.3 ±0.75 LSB

clk

= 25 MHz; CL= 15 pF;

clk

− 53 100 mW

ramp input

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

TDA8792M SSOP24 plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1

1996 Feb 21 2

Philips Semiconductors Product speciﬁcation

3.3 V, 25 MHz 8-bit analog-to-digital converter (ADC)

BLOCK DIAGRAM

dbook, full pagewidth

STDBY

1

V

DDD

2

V

SSD2

3

V

SSA1

4

V

I

V

DDA

I

bias

V

RT

5

6

7

8

7 x 8

OFFSET

COMPENSATED

COMPARATORS

DECODER

LATCHES

TDA8792

8

OUTPUT BUFFER

24 23

22

21 D7

D620

D519

D4 18

D317

TDA8792

CLK V

SSO

V

DDO

MSB

data outputs

V

RM

V

RB

SSA2

MLD119 - 1

D2 16

D1 15

D014

LSB

OE 13

9

10

12

REFERENCE

LADDER

DAC

Fig.1 Block diagram.

1996 Feb 21 3

Philips Semiconductors Product speciﬁcation

3.3 V, 25 MHz 8-bit analog-to-digital converter (ADC)

PINNING

SYMBOL PIN DESCRIPTION

STDBY 1 standby input V

DDD

V

SSD2

V

SSA1

V

I

V

DDA

I

bias

V

RT

V

RM

V

RB

n.c. 11 not connected V

SSA2

OE

D0 14 data output; bit 0 (LSB) D1 15 data output; bit 1 D2 16 data output; bit 2 D3 17 data output; bit 3 D4 18 data output; bit 4 D5 19 data output; bit 5 D6 20 data output; bit 6 D7 21 data output; bit 7 (MSB) V

DDO

V

SSO

CLK 24 clock input

2 digital supply voltage (+3.3 V) 3 digital ground 2 4 analog ground 1 5 analog input voltage 6 analog supply voltage (+3.3 V) 7 bias current input 8 reference voltage TOP input 9 reference voltage MIDDLE

10 reference voltage BOTTOM input

12 analog ground 2

output enable input (CMOS level

13

input, active LOW)

positive supply voltage for output

22

stage (+3.3 V)

23 output ground

handbook, halfpage

V

DDD

V

SSD2 SSA1

V

DDA

I

bias

V

RM

V

SSA2

RT

RB

n.c.

1 2 3 4

V

5

I

6

TDA8792

7 8

9 10 11 12



MLD120 - 1

STDBY

V

Fig.2 Pin configuration.

TDA8792

CLK

24

V

23

SSO

22

V

DDO

21

D7

20

D6 D5

19

D4

18 17

D3 D2

16

D1

15

D0

14

OE

13

1996 Feb 21 4

Philips Semiconductors Product speciﬁcation

3.3 V, 25 MHz 8-bit TDA8792

analog-to-digital converter (ADC)

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DDA

V

DDD

V

DDO

∆V

V

I

V

clk(p-p)

I

O

T

stg

T

amb

T

j

DD1

DD2

DD3

analog supply voltage note 1 −0.5 +5.0 V digital supply voltage note 1 −0.5 +5.0 V output stages supply voltage note 1 −0.5 +5.0 V supply voltage differences between

∆V

DD1=VDDA

− V

DDD

supply voltage differences between ∆V

DD2=VDDD

− V

DDO

supply voltage differences between ∆V

DD3=VDDA

− V

DDO

input voltage referenced to V AC input voltage for switching

referenced to V

SSA SSD

−0.3 +0.3 V

−1.0 +1.0 V

−0.5 +5.0 V

− V

DDD

(peak-to-peak value) output current − 10 mA storage temperature −55 +150 °C operating ambient temperature −20 +75 °C junction temperature − +125 °C

V

Note

1. The supply voltages V differences ∆V

DD1

, ∆V

DDA DD2

, V

DDD

and ∆V

and V

DDO

are respected.

DD3

may have any value between −0.5 V and +5.0 V provided that the

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air 119 K/W

1996 Feb 21 5

Philips Semiconductors Product speciﬁcation

3.3 V, 25 MHz 8-bit TDA8792

analog-to-digital converter (ADC)

CHARACTERISTICS

V

DDA=V6

V

SSA,VSSD

VIH=V unless otherwise speciﬁed.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply

V

DDA

V

DDD

V

DDO

I

DDA

I

DDD

I

DDO

Inputs

LOCK INPUT CLK (REFERENCED TO V

C V

IL

V

IH

I

IL

I

IH

C

I

INPUTS OE AND STDBY (REFERENCED TO V V

IL

V

IH

I

IL

I

IH

VI(ANALOG INPUT VOLTAGE REFERENCED TO V I

IL

I

IH

Z

I

C

I

Reference voltages for the resistor ladder; see Table 1 V

RB

V

RT

V

diff

I

ref

R

LAD

TC

DDD

RLAD

to V

; CL= 15 pF; T

= 2.85 to 3.6 V; V

4,12

and V

SSO

DDD=V2

shorted together; V

= 0 to +70 °C; typical values measured at V

amb

to V3and V1= 2.7 to 3.6 V; V

DDA

to V

= −0.15 to +0.15 V; f

DDD

DDO=V22

= 25 MHz; 50% duty factor; VIL=0V;

clk

DDA=VDDD=VDDO

to V23= 2.5 to 3.6 V;

= 3.3 V and T

amb

=25°C;

analog supply voltage 2.85 3.3 3.6 V digital supply voltage 2.7 3.3 3.6 V output stages supply voltage 2.5 3.3 3.6 V analog supply current − 12 20 mA digital supply current − 36mA output stages supply current CL= 15 pF; ramp input − 12mA

); note 1

SSD

LOW level input voltage 0 − 0.8 V HIGH level input voltage 2.0 − V LOW level input current V HIGH level input current V

= 0.4 V −10 −−µA

clk

= 2.7 V −−10 µA

clk

DDD

V

input capacitance − 10 − pF

); see Tables 2 and 3

SSD

LOW level input voltage 0 − 0.8 V HIGH level input voltage 2.0 − V

DDD

V LOW level input current VIL= 0.4 V −10 −−µA HIGH level input current VIH= 2.7 V −−+10 µA

)

SSA

LOW level input current VI=0V −20 −−µA HIGH level input current VI= 1.5 V −−+20 µA input impedance fi= 4.43 MHz − 35 − kΩ input capacitance fi= 4.43 MHz − 5 − pF

reference voltage BOTTOM 0 − 0.15 V reference voltage TOP 1.4 − 1.6 V differential reference voltage VRT− V

RB

1.25 1.5 1.6 V reference current − 1.3 − mA resistor ladder − 1250 −Ω temperature coefﬁcient of the resistor

− 1 −Ω/K ladder

1996 Feb 21 6