Philips TDA8790M-C2, TDA8790M-C1 Datasheet

INTEGRATED CIRCUITS

DATA SHEET

TDA8790

8-bit, 40 Msps 2.7 to 5.5 V universal analog-to-digital converter

Product specification

1996 Feb 21

Supersedes data of 1995 May 08

File under Integrated Circuits, IC02

Philips Semiconductors	Product specification

8-bit, 40 Msps 2.7 to 5.5 V universal

TDA8790

analog-to-digital converter

FEATURES

∙8-bit resolution

∙Operation between 2.7 and 5.5 V

∙Sampling rate up to 40 MHz

∙DC sampling allowed

∙High signal-to-noise ratio over a large analog input frequency range (7.3 effective bits at 4.43 MHz full-scale input at fclk = 40 MHz)

∙CMOS/TTL compatible digital inputs and outputs

∙External reference voltage regulator

∙Power dissipation only 30 mW (typical)

∙Low analog input capacitance, no buffer amplifier required

∙Sleep mode (4 mW)

∙No sample-and-hold circuit required.

QUICK REFERENCE DATA

APPLICATIONS

High-speed analog-to-digital conversion for:

∙Video data digitizing

∙Camera

∙Camcorder

∙Radio communication.

GENERAL DESCRIPTION

The TDA8790 is an 8-bit universal analog-to-digital converter (ADC) for video and general purpose applications. It converts the analog input signal from 2.7 to 5.5 V into 8-bit binary-coded digital words at a

maximum sampling rate of 40 MHz. All digital inputs and outputs are CMOS/TTL compatible. A sleep mode allows reduction of the device power consumption down to 4 mW.

SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
VDDA	analog supply voltage		2.7	3.3	5.5	V
VDDD	digital supply voltage		2.7	3.3	5.5	V
VDDO	output stages supply voltage		2.5	3.3	5.5	V
VDD	supply voltage difference
	VDDA − VDDD		−0.2	−	+0.2	V
	VDDD − VDDO		−0.2	−	+2.25	V
IDDA	analog supply current		−	4	6	mA
IDDD	digital supply current		−	5	8	mA
IDDO	output stages supply current	fclk = 40 MHz; CL = 20 pF;	−	1	2	mA
		ramp input
INL	integral non-linearity	fclk = 40 MHz; ramp input	−	±0.5	±0.75	LSB
DNL	differential non-linearity	fclk = 40 MHz; ramp input	−	±0.25	±0.5	LSB
fclk(max)	maximum clock frequency		40	−	−	MHz
Ptot	total power dissipation	VDDA = VDDD = VDDO = 3.3 V	−	30	53	mW

ORDERING INFORMATION

TYPE		PACKAGE
NUMBER	NAME	DESCRIPTION	VERSION
TDA8790M	SSOP20	plastic shrink small outline package; 20 leads; body width 4.4 mm	SOT266-1

1996 Feb 21

2

Philips Semiconductors	Product specification

8-bit, 40 Msps 2.7 to 5.5 V universal

TDA8790

analog-to-digital converter

BLOCK DIAGRAM

			VDDA		CLK	VDDD
			5		1	3
				CLOCK DRIVER			TDA8790		2		SLEEP
	VRT	10
									19	D7	MSB
			RLAD						18	D6
	V I	9						CMOS	17	D5
analog			ANALOG -TO - DIGITAL		LATCHES				16	D4
voltage input			CONVERTER					OUTPUTS
											data outputs
									15	D3
	VRM
		8							14	D2
									13	D1
									12	D0	LSB
	VRB	7							20		VDDO
			6			11		4
			VSSA			VSSO		VSSD1	MBE502
			analog			output		digital
			ground			ground	ground

Fig.1 Block diagram.

1996 Feb 21

3

Philips Semiconductors	Product specification

8-bit, 40 Msps 2.7 to 5.5 V universal

TDA8790

analog-to-digital converter

PINNING

SYMBOL	PIN	DESCRIPTION
CLK	1	clock input
SLEEP	2	sleep mode input
VDDD	3	digital supply voltage (2.7 to 5.5 V)
VSSD	4	digital ground
VDDA	5	analog supply voltage (2.7 to 5.5 V)
VSSA	6	analog ground
VRB	7	reference voltage BOTTOM input
VRM	8	reference voltage MIDDLE
VI	9	analog input voltage
VRT	10	reference voltage TOP input
VSSO	11	digital output ground
D0	12	data output; bit 0 (LSB)
D1	13	data output; bit 1
D2	14	data output; bit 2
D3	15	data output; bit 3
D4	16	data output; bit 4
D5	17	data output; bit 5
D6	18	data output; bit 6
D7	19	data output; bit 7 (MSB)
VDDO	20	positive supply voltage for output
		stage (2.7 to 5.5 V)

				VDDO
CLK	1		20
SLEEP	2		19	D7
VDDD
	3		18	D6
VSSD
	4		17	D5
VDDA
	5	TDA8790	16	D4
VSSA
	6		15	D3
VRB
	7		14	D2
VRM				D1
	8		13
VI				D0
	9		12
VRT				VSSO
	10		11
		MBE501

Fig.2 Pin configuration.

1996 Feb 21

4

Philips Semiconductors	Product specification

8-bit, 40 Msps 2.7 to 5.5 V universal

TDA8790

analog-to-digital converter

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL	PARAMETER	CONDITIONS	MIN.	MAX.	UNIT
VDDA	analog supply voltage	note 1	−0.3	+7.0	V
VDDD	digital supply voltage	note 1	−0.3	+7.0	V
VDDO	output stages supply voltage	note 1	−0.3	+7.0	V
VDD	supply voltage difference
	VDDA − VDDD		−1.0	+4.0	V
	VDDA − VDDO		−1.0	+4.0	V
	VDDD − VDDO		−1.0	+4.0	V
VI	input voltage	referenced to VSSA	−0.3	+7.0	V
Vclk(p-p)	AC input voltage for switching	referenced to VSSD	−	VDDD	V
	(peak-to-peak value)
IO	output current		−	10	mA
Tstg	storage temperature		−55	+150	°C
Tamb	operating ambient temperature		−20	+75	°C
Tj	junction temperature		−	+150	°C

Note

1. The supply voltages VDDA, VDDD and VDDO may have any value between −0.3 V and +7.0 V provided that the supply voltage VDD remains as indicated.

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL	PARAMETER	VALUE	UNIT
Rth j-a	thermal resistance from junction to ambient in free air	120	K/W

1996 Feb 21

5

Philips Semiconductors	Product specification

8-bit, 40 Msps 2.7 to 5.5 V universal

TDA8790

analog-to-digital converter

CHARACTERISTICS

VDDA = V5 to V6 = 3.3 V; VDDD = V3 to V4 = 3.3 V; VDDO = V20 to V11 = 3.3 V; VSSA, VSSD and VSSO shorted together; Vi(p-p) = 1.84 V; CL = 20 pF; Tamb = 0 to +70 °C; typical values measured at Tamb = 25 °C; unless otherwise specified.

SYMBOL	PARAMETER		CONDITIONS	MIN.	TYP.	MAX.	UNIT
Supply
VDDA	analog supply voltage			2.7	3.3	5.5	V
VDDD	digital supply voltage			2.7	3.3	5.5	V
VDDO	output stages supply voltage			2.5	3.3	5.5	V
VDD	supply voltage difference
	VDDA − VDDD			−0.2	−	+0.2	V
	VDDD − VDDO			−0.2	−	+2.25	V
IDDA	analog supply current			−	4	6	mA
IDDD	digital supply current			−	5	8	mA
IDDO	output stages supply current	fclk = 40 MHz; ramp input;		−	1	2	mA
		CL = 20 pF
Inputs
CLOCK INPUT CLK (REFERENCED TO VSSD); see note 1
VIL	LOW level input voltage			0	−	0.3VDDD	V
VIH	HIGH level input voltage			0.7VDDD	−	VDDD	V
		VDDD ≤ 3.6 V		0.6VDDD	−	VDDD	V
IIL	LOW level input current	Vclk	= 0.3VDDD	−1	0	+1	μA
IIH	HIGH level input current	Vclk	= 0.7VDDD	−	−	5	μA
ZI	input impedance	fclk = 40 MHz		−	4	−	kΩ
CI	input capacitance	fclk = 40 MHz		−	3	−	pF
INPUT SLEEP (REFERENCED TO VSSD); see Table 2
VIL	LOW level input voltage			0	−	0.3VDDD	V
VIH	HIGH level input voltage			0.7VDDD	−	VDDD	V
		VDDD ≤ 3.6 V		0.6VDDD	−	VDDD	V
IIL	LOW level input current	VIL = 0.3VDDD		−1	−	−	μA
IIH	HIGH level input current	VIH = 0.7VDDD		−	−	+1	μA
VI (ANALOG INPUT VOLTAGE REFERENCED TO VSSA)
IIL	LOW level input current	VI = VRB		−	0	−	μA
IIH	HIGH level input current	VI = VRT		−	9	−	μA
ZI	input impedance	fi = 1 MHz		−	20	−	kΩ
CI	input capacitance	fi = 1 MHz		−	2	−	pF
Reference voltages for the resistor ladder; see Table 1
VRB	reference voltage BOTTOM			1.1	1.2	−	V
VRT	reference voltage TOP	VTOP ≤ VDDA		2.7	3.3	VDDA	V
Vdiff	differential reference voltage			1.5	2.1	2.7	V
	VRT − VRB
Iref	reference current			−	0.95	−	mA

1996 Feb 21

6