Philips tda8714 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

TDA8714

8-bit high-speed analog-to-digital
converter

Product specification
Supersedes data of 1996 Jan 31
File under Integrated Circuits, IC02

1997 Oct 29

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDA8714

FEATURES

• 8-bit resolution

• Sampling rate up to 80 MHz

• No missing codes guaranteed

• High signal-to-noise ratio over a large analog input

frequency range (7.7 effective bits at 4.43 MHz
full-scale input at f

= 80 MHz)

clk

• Overflow/underflow 3-state TTL output

APPLICATIONS

High-speed analog-to-digital conversion for:

• video data digitizing

• radar pulse analysis

• transient signal analysis

• high energy physics research

•Σ∆ modulators

• medical imaging.

• TTL compatible digital inputs

• Low-level AC clock input signal allowed

GENERAL DESCRIPTION

• External reference voltage regulator

• Power dissipation only 340 mW (typical)

• Low analog input capacitance, no buffer amplifier

required

• No sample-and-hold circuit required.

The TDA8714 is an 8-bit high-speed Analog-to-Digital
Converter (ADC) for professional video and other
applications. It converts the analog input signal into 8-bit
binary-coded digital words at a maximum sampling rate of
80 MHz. All digital inputs and outputs are TTL compatible,
although a low-level sine wave clock input signal is
allowed.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V
V
V
I

CCA

I

CCD

I

CCO

CCA
CCD
CCO

analog supply voltage 4.75 5.0 5.25 V
digital supply voltage 4.75 5.0 5.25 V
output stages supply voltage 4.75 5.0 5.25 V
analog supply current − 25 30 mA
digital supply current − 27 33 mA

output stages supply current − 16 20 mA
INL DC integral non-linearity −±0.4 ±0.5 LSB
DNL DC differential non-linearity −±0.2 ±0.35 LSB
AINL AC integral non-linearity note 1 −±0.5 ±1.0 LSB
f

clk(max)

maximum clock frequency

TDA8714/7 80 −−MHz
TDA8714/6 60 −−MHz
TDA8714/4 40 −−MHz

P

tot

total power dissipation − 340 435 mW

Note

1. Full-scale sine wave (f

= 4.43 MHz; f

i

= 80 MHz).

clk

1997 Oct 29 2

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDA8714

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

TDA8714T/4 SO24 plastic small outline package; 24 leads;
TDA8714T/6 SO24 SOT137-1 60

body width 7.5 mm

PACKAGE

SAMPLING

FREQUENCY (MHz)

SOT137-1 40

TDA8714T/7 SO24 SOT137-1 80
TDA8714M/4 SSOP24 plastic shrink small outline package; 24 leads;
TDA8714M/6 SSOP24 SOT340-1 60

body width 5.3 mm

SOT340-1 40

TDA8714M/7 SSOP24 SOT340-1 80

BLOCK DIAGRAM

handbook, full pagewidth

V

CCA

7

V

9

RT

CLK
16

CLOCK DRIVER

V

CCD

18

TDA8714

CE
22

analog

voltage input

output ground

V

8

I

V

4

RB

OGND

20

analog ground digital ground

ANALOG -TO-DIGITAL

CONVERTER

6
AGND

17
DGND

OVERFLOW / UNDERFLOW

LATCH

Fig.1 Block diagram.

TTL OUTPUTSLATCHES

TTL OUTPUT

MSA669

12

D7
D6

13

D5

14

D4

15

D3

23
24 D2

1

D1

2

D0
V

19

21

V

11

CCO1

CCO2

MSB

data outputs

LSB

overflow / underflow

output

1997 Oct 29 3

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDA8714

PINNING

SYMBOL PIN DESCRIPTION

D1 1 data output; bit 1
D0 2 data output; bit 0 (LSB)
n.c. 3 not connected
V

RB

n.c. 5 not connected
AGND 6 analog ground
V

CCA

V

I

V

RT

n.c. 10 not connected
O/UF 11 overflow/underflow data output
D7 12 data output; bit 7 (MSB)
D6 13 data output; bit 6
D5 14 data output; bit 5
D4 15 data output; bit 4
CLK 16 clock input
DGND 17 digital ground
V

CCD

V

CCO1

OGND 20 output ground
V

CCO2

CE 22 chip enable input (TTL level input,

D3 23 data output; bit 3
D2 24 data output; bit 2

4 reference voltage BOTTOM input

7 analog supply voltage (+5 V)
8 analog input voltage
9 reference voltage TOP input

18 digital supply voltage (+5 V)
19 supply voltage for output stages 1

(+5 V)

21 supply voltage for output stages 2

(+5 V)

active LOW)

handbook, halfpage

1

D1

2

D0

n.c.

3

V

4

RB

n.c.

5

AGND

6

V

CCA

V

O/UF

V

RT

n.c.

D7

TDA8714

7
8

I

9
10
11
12

MSA667

Fig.2 Pin configuration.

D2

24

D3

23
22

CE
V

21

CCO2

OGND

20

V

19

CCO1

V

18

CCD

DGND

17

CLK

16

D4

15

D5

14

D6

13

1997 Oct 29 4

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDA8714

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CCA

V

CCD

V

CCO

∆V

∆V

∆V

V

I

V

clk(p-p)

I

O

T

stg

T

amb

T

j

CC

CC

CC

analog supply voltage note 1 −0.3 +7.0 V
digital supply voltage note 1 −0.3 +7.0 V
output stages supply voltage note 1 −0.3 +7.0 V
supply voltage differences between

V

and V

CCA

CCD

supply voltage differences between
V

and V

CCO

CCD

supply voltage differences between
V

and V

CCA

CCO

−1.0 +1.0 V

−1.0 +1.0 V

−1.0 +1.0 V

input voltage referenced to AGND −0.3 +7.0 V
AC input voltage for switching

referenced to DGND − V

CCD

V

(peak-to-peak value)
output current − 10 mA
storage temperature −55 +150 °C
operating ambient temperature 0 +70 °C
junction temperature − +150 °C

Note

1. The supply voltages V
between V

CCA

and V

and V

CCA

is between −1 V and +1 V.

CCD

may have any value between −0.3 V and +7.0 V provided the difference

CCD

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air

SOT137-1 75 K/W
SOT340-1 119 K/W

1997 Oct 29 5

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDA8714

CHARACTERISTICS

V

CCA=V7

AGND and DGND shorted together; V
V

CCA

V

CCA=VCCD=VCCO

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supply

V

CCA

V

CCD

V

CCO

I

CCA

I

CCD

I

CCO

Inputs

to V6= 4.75 to 5.25 V; V

to V

= −0.25 to +0.25 V; V

CCO

= 5 V and T

CCD=V18

CCA

i(p-p)

=25°C; unless otherwise specified.

amb

to V17= 4.75 to 5.25 V; V

to V

= 1.75 V; T

= −0.25 to +0.25 V; V

CCD

= 0 to +70 °C; typical values measured at

amb

CCO=V19

to V

CCO

and V21to V20= 4.75 to 5.25 V;

= −0.25 to +0.25 V;

CCD

analog supply voltage 4.75 5.0 5.25 V
digital supply voltage 4.75 5.0 5.25 V
output stages supply voltage 4.75 5.0 5.25 V
analog supply current − 25 30 mA
digital supply current − 27 33 mA
output stages supply current − 16 20 mA

C

LOCK INPUT CLK (REFERENCED TO DGND); note 1

V

IL

V

IH

I

IL

I

IH

Z

I

C

I

LOW level input voltage 0 − 0.8 V
HIGH level input voltage 2.0 − V
LOW level input current V
HIGH level input current V
input impedance f

input capacitance f
INPUT CE (REFERENCED TO DGND); see Table 2
V

IL

V

IH

I

IL

I

IH

LOW level input voltage 0 − 0.8 V

HIGH level input voltage 2.0 − V

LOW level input current VIL= 0.4 V −400 −−µA

HIGH level input current VIH= 2.7 V −−20 µA
VI(ANALOG INPUT VOLTAGE REFERENCED TO AGND)
I

IL

I

IH

Z

I

C

I

LOW level input current VI= 1.2 V − 0 −µA

HIGH level input current VI= 3.5 V 60 130 280 µA

input impedance fi= 4.43 MHz − 10 − kΩ

input capacitance fi= 4.43 MHz − 14 − pF
Reference voltages for the resistor ladder; see Table 1
V

V
V
I

ref

R
TC
V
V
V

RB
RT
diff

LAD

RLAD
osB
osT
i(p-p)

reference voltage BOTTOM 1.2 1.3 1.6 V
reference voltage TOP 3.5 3.6 3.9 V
differential reference voltage VRT− V

RB

reference current − 11.5 − mA
resistor ladder − 200 −Ω
temperature coefficient of the resistor ladder − 0.24 − ppm
offset voltage BOTTOM note 2 275 285 295 mV
offset voltage TOP note 2 305 315 325 mV
analog input voltage (peak-to-peak value) 1.45 1.75 2.15 V

CCD

= 0.4 V −400 −−µA

clk

= 2.7 V −−300 µA

clk

= 80 MHz − 18 − kΩ

clk

= 80 MHz − 1 − pF

clk

CCD

1.9 2.3 2.7 V

V

V

1997 Oct 29 6

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDA8714

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Outputs

DIGITAL OUTPUTS D7 to D0 (REFERENCED TO DGND)
V

OL

V

OH

I

OZ

Switching characteristics

C

LOCK INPUT CLK (note 1; see Fig.3)

f

clk(max)

t

CPH

t

CPL

Analog signal processing

LOW level output voltage IO= 1 mA 0 − 0.4 V
HIGH level output voltage IO= −0.4 mA 2.7 − V

= −1 mA 2.4 − V

I

O

output current in 3-state mode 0.4V<VO<V

CCD

−20 − +20 µA

CCD
CCD

V
V

maximum clock frequency

TDA8714/4 40 −−MHz
TDA8714/6 60 −−MHz

TDA8714/7 80 −−MHz
clock pulse width HIGH 6 −−ns
clock pulse width LOW 6 −−ns

L

INEARITY

INL DC integral non-linearity −±0.4 ±0.5 LSB
DNL DC differential non-linearity −±0.2 ±0.35 LSB
AINL AC integral non-linearity note 3 −±0.5 ±1.0 LSB

B

ANDWIDTH (f

= 40 MHz); note 4

clk

B analog bandwidth full-scale sine wave − 13 − MHz

75% full-scale sine

− 20 − MHz
wave; small signal at
Vi= ±5 LSB, code 128

t

STLH

analog input settling time LOW-to-HIGH full-scale square

− 2.5 3.5 ns
wave; Fig.6; note 5

t

STHL

analog input settling time HIGH-to-LOW full-scale square

− 3.0 4.0 ns
wave; Fig.6; note 5

HARMONICS (f
h

1

h

all

= 40 MHz)

clk

fundamental harmonics (full scale) fi= 4.43 MHz −−0dB
harmonics (full scale);

fi= 4.43 MHz

all components

second harmonics −−64 −60 dB
third harmonics −−58 −55 dB

THD total harmonic distortion f

= 4.43 MHz −−56 − dB

i

SIGNAL-TO-NOISE RATIO (note 6; see Figs 7 and 13)
S/N signal-to-noise ratio (full scale) without harmonics;

= 40 MHz;

f

clk

46 48 − dB

fi= 4.43 MHz

1997 Oct 29 7

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDA8714

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

EFFECTIVE BITS (note 6; see Figs 7 and 13)
EB effective bits

TDA8714/4 f

effective bits

TDA8714/6 f

effective bits

TDA8714/7 f

TWO-TONE (note 7)
TTIR two-tone intermodulation rejection f
BIT ERROR RATE
BER bit error rate f

DIFFERENTIAL GAIN (note 8)
G

diff

differential gain f

DIFFERENTIAL PHASE (note 8)

ϕ

diff

differential phase f

= 40 MHz

clk

f

= 4.43 MHz − 7.75 − bits

i

= 7.5 MHz − 7.6 − bits

f

i

= 60 MHz

clk

= 4.43 MHz − 7.7 − bits

f

i

f

= 7.5 MHz − 7.55 − bits

i

f

= 10 MHz − 7.4 − bits

i

= 80 MHz

clk

f

= 4.43 MHz − 7.7 − bits

i

= 7.5 MHz − 7.5 − bits

f

i

f

= 10 MHz − 7.2 − bits

i

f

= 15 MHz − 6.3 − bits

i

= 40 MHz −−56 − dB

clk

= 40 MHz;

clk

− 10

−11

− times/

fi= 4.43 MHz;
VI= ±16 LSB at
code 128

= 40 MHz;

clk

− 0.6 − %
fi= 4.43 MHz

= 40 MHz;

clk

− 0.8 − deg
fi= 4.43 MHz

samples

Timing (note 9; see Figs 3 and 5; f
t

ds

t

h

t

d

sampling delay time −−2ns
output hold time 5 −−ns
output delay time − 10 11 ns

= 80 MHz)

clk

3-state output delay times (see Fig.4)
t

dZH

t

dZL

t

dHZ

t

dLZ

enable HIGH − 40 44 ns
enable LOW − 12 16 ns
disable HIGH − 50 54 ns
disable LOW − 10 14 ns

1997 Oct 29 8