Philips tda8709a DATASHEETS

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TDA8709A

Video analog input interface

Product specification
Supersedes data of April 1993
File under Integrated Circuits, IC02

Philips Semiconductors

June 1994

Philips Semiconductors Product specification

Video analog input interface TDA8709A

FEATURES

• 8-bit resolution

• Sampling rate up to 32 MHz

• TTL-compatible digital inputs and outputs

• Internal reference voltage regulator

• Low-level AC clock inputs and outputs

• Clamp function with selection for ‘16’ or ‘128’

• No sample-and-hold circuit required

• Three selectable video inputs.

APPLICATIONS

• Video signal processing

• Digital picture processing

• Frame grabbing.

• Colour difference signals (U, V)

• R, G, B signals

• Chrominance signal (C).

QUICK REFERENCE DATA

GENERAL DESCRIPTION

The TDA8709A is an analog input interface for video signal
processing. It includes a an input selector
(one out-of-three video signals), video amplifier with clamp
and external gain control, an 8-bit analog-to-digital
converter (ADC) with a sampling rate of 32 MHz and an
input selector.

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V
V
V
I

CCA

I

CCD

I

CCO

CCA
CCD
CCO

analog supply voltage 4.5 5.0 5.5 V
digital supply voltage 4.5 5.0 5.5 V
TTL output supply voltage 4.2 5.0 5.5 V
analog supply current − 40 47 mA
digital supply current − 24 30 mA

TTL output supply current − 12 16 mA
ILE DC integral linearity error −−±1 LSB
DLE DC differential linearity error −−±0.5 LSB
f

clk(max)

maximum clock frequency 30 32 − MHz
B maximum −3 dB bandwidth (preamplifier) 12 18 − MHz
P

tot

total power dissipation − 380 512 mW

ORDERING INFORMATION

PACKAGE

TYPE NUMBER

PINS PIN POSITION MATERIAL CODE

TDA8709A 28 DIP plastic SOT117-1

TDA8709AT 28 SO28L plastic SOT136-1

June 1994 2

Philips Semiconductors Product specification

Video analog input interface TDA8709A

BLOCK DIAGRAM

handbook, full pagewidth

video input 0
video input 1
video input 2

clamp capacitor

connection

gain control

selection bit 0

input

video input

16
17

SELECTOR

18

24

25

selection

video input
selection bit 1

INPUT

CLAMP

27

clamp

level

LOGIC

VIDEO

AMPLIFIER

26

clamp

pulse

analog

voltage

output

digital V

(+ 5 V)

ADC
input

2014 15

19

AMP.

TDA8709A

CLAMP LEVEL "16"

DIGITAL COMPARATOR

CLAMP LEVEL "128"

DIGITAL COMPARATOR

6

CCD

8

digital

ground

clock
input

decoupling
input

5

8 - bit

ADC

22

analog V

(+ 5 V)

TTL outputs V (+ 5 V)

21 7

TTL

OUTPUTS

23

analog

CCA

ground

9
1

2
3

4
10
11
12
13

28

CCO

fast output

chip enable

D7
D6
D5
D4
D3
D2
D1
D0

output
format

selection

MBB951

June 1994 3

Fig.1 Block diagram.

Philips Semiconductors Product specification

Video analog input interface TDA8709A

PINNING

SYMBOL PIN DESCRIPTION

D7 1 data output; bit 7 (MSB)
D6 2 data output; bit 6
D5 3 data output; bit 5
D4 4 data output; bit 4
CLK 5 clock input
V
V

CCD
CCO

6 digital supply voltage (+5 V)

7 TTL outputs supply voltage (+5 V)
DGND 8 digital ground
FOEN 9 fast output chip enable
D3 10 data output; bit 3
D2 11 data output; bit 2
D1 12 data output; bit 1
D0 13 data output; bit 0 (LSB)
I0 14 video input selection bit 0
I1 15 video input selection bit 1
VIN0 16 video input 0
VIN1 17 video input 1
VIN2 18 video input 2
ANOUT 19 analog voltage output
ADCIN 20 analog-to-digital converter input
DEC 21 decoupling input
V

CCA

22 analog supply voltage (+5 V)
AGND 23 analog ground
CLAMP 24 clamp capacitor connection
GAIN 25 gain control input
CLP 26 clamping pulse
CLS 27 clamping level selection input
OFS 28 output format selection

handbook, halfpage

1

D7

2

D6

3

D5

4

D4

5

CLK

V

6

CCD

V

7

CCO

DGND

FOEN

D3
D2
D1
D0

I0

TDA8709A

8

9
10
11
12
13

MBB950

Fig.2 Pin configuration.

28
27
26
25
24
23
22
21

20
19
18
17
16
1514

OFS
CLS
CLP

GAIN
CLAMP

AGND

V

CCA

DEC
ADCIN
ANOUT
VIN2

VIN1
VIN0

I1

June 1994 4

Philips Semiconductors Product specification

Video analog input interface TDA8709A

FUNCTIONAL DESCRIPTION

TDA8709A is an 8-bit ADC with internal clamping and a
preamplifier with adjustable gain.

The clamping value is switched via pin 27 between

chrominance or colour difference signals). While clamping
pulse at pin 27 is logic 1, the device will adjust the
clamping level to the chosen value. The output format can
be selected between binary and two's complement at
pin 28.

digital 16 (for R, G, B signals) and digital 128 (for

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER MIN. MAX. UNIT

V
V
V
∆V

V
I

O

T
T
T

CCA
CCD
CCO

CC

I

stg
amb
j

analog supply voltage −0.3 +7.0 V
digital supply voltage −0.3 +7.0 V
TTL output supply voltage −0.3 +7.0 V
supply voltage difference between V
supply voltage difference between V
supply voltage difference between V

CCA
CCO
CCA

and V

and V

and V

CCD

CCD

CCO

−0.5 +0.5 V

−0.5 +0.5 V

−1.0 +1.0 V

input voltage −0.3 +7.0 V
output current − +10 mA
storage temperature −55 +150 °C
operating ambient temperature 0 +70 °C
junction temperature 0 +125 °C

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air

SOT117-1 55 K/W
SOT136-1 70 K/W

June 1994 5

Philips Semiconductors Product specification

Video analog input interface TDA8709A

CHARACTERISTICS

V

= V22to V23 = 4.5 to 5.5 V; V

CCA

shorted together; V

= 0 to +70 °C; typical readings taken at V

T

amb

CCA

to V

CCD

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V
V
V
I

CCA

I

CCD

I

CCO

CCA
CCD
CCO

analog supply voltage 4.5 5.0 5.5 V
digital supply voltage 4.5 5.0 5.5 V
TTL output supply voltage 4.2 5.0 5.5 V
analog supply current − 40 47 mA
digital supply current − 24 30 mA
TTL output supply current TTL load (see Fig.7) − 12 16 mA

Preamplifier inputs

TO VIN2 INPUTS

VIN0
V

I(p-p)

| input impedance fi= 6 MHz 10 20 − kΩ

|Z

i

C

I

input voltage (peak-to-peak value) note 1 0.6 − 1.5 V

input capacitance fi = 6 MHz − 1 − pF
I0 AND I1 TTL INPUTS (SEE TABLE 1)
V

IL

V

IH

I

IL

I

IH

LOW level input voltage 0 − 0.8 V

HIGH level input voltage 2.0 − V

LOW level input current VI = 0.4 V −400 −−µA

HIGH level input current VI = 2.7 V −− 20 µA
CLS, OFS AND CLP TTL INPUTS (SEE FIG.5)
V

IL

V

IH

I

IL

I

IH

t

CLP

LOW level input voltage 0 − 0.8 V

HIGH level input voltage 2.0 − V

LOW level input current VI = 0.4 V −400 −−µA

HIGH level input current VI = 2.7 V −− 20 µA

clamp pulse width 2 −−µs
GAIN INPUT (PIN 25)
V

25(min)

V

25(max)

I

I

input voltage for minimum gain see Fig.9 − 1.8 − V

input voltage for maximum gain see Fig.9 − 3.8 − V

input current − 1.0 −µA
CLAMP INPUT (PIN 24)
V

24

I

24

clamp voltage for code 128 output − 3.5 − V

clamp output current see Table 2

= V6to V8 = 4.5 to 5.5 V; V

CCD

= −0.5 to +0.5 V; V

CCA

CCO

= V

to V

CCD

= V7to V8 = 4.2 to 5.5 V; AGND and DGND

CCO

= −0.5 to +0.5 V; V

CCD

= V

= 5 V and T

CCO

to V

CCA

= 25 °C; unless otherwise specified.

amb

= −0.5 to +0.5 V;

CCO

CCD

CCD

V

V

June 1994 6

Philips Semiconductors Product specification

Video analog input interface TDA8709A

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Video amplifier outputs

ANOUT OUTPUT (PIN 19)
V

19(p-p)

AC output voltage

(peak-to-peak value)
I

19

I

O(p-p)

V

19

V

19

Z

19

internal current source RL = ∞ 2.0 2.5 − mA

output current driven by the load V

DC output voltage for black level CLS = logic 1 − V

DC output voltage for black level CLS = logic 0 − V

output impedance − 20 −Ω

Preamplifier dynamic characteristics

α

ct

G

diff

ϕ

diff

crosstalk between VIN inputs V

differential gain V

differential phase V

B −3 dB bandwidth 12 −−MHz
S/N signal-to-noise ratio note 4 60 −−dB
SVRR1 supply voltage ripple rejection note 5 − 45 − dB
∆G gain range see Fig.9 −4.5 − +6.0 dB
G

stab

gain stability as a function of supply

voltage and temperature

VOF = 1.33 V (p-p);

− 1.33 − V

V25= 3.0 V

= 1.33 V (p-p);

ANOUT

−− 1.0 mA

note 2

− 2.02 − V

CCA

− 2.6 − V

CCA

= 4.75 to 5.25 V;

CCA

−−50 −45 dB

note 3

= 1.33 V (p-p);

VIN

− 2 − %

V25= 3.0 V

= 1.33 V (p-p);

VIN

− 0.8 − deg

V25= 3.0 V

see Fig.9 −− 5%

Analog-to-digital converter inputs

CLK

INPUT (PIN 5)

V

IL

V

IH

I

IL

I

IH

| input impedance f

|Z

i

C

I

LOW level input voltage 0 − 0.8 V

HIGH level input voltage 2.0 − V

LOW level input current V

HIGH level input current V

input capacitance f

= 0.4 V −400 −−µA

clk

= 2.7 V −− 100 µA

clk

= 10 MHz − 4 − kΩ

clk

= 10 MHz − 4.5 − pF

clk

FOEN INPUT (SEE TABLE 3)
V

IL

V

IH

I

IL

I

IH

LOW level input voltage 0 − 0.8 V

HIGH level input voltage 2.0 − V

LOW level input current V9= 0.4 V −400 −−µA

HIGH level input current V9= 2.7 V −− 20 µA

June 1994 7

CCD

CCD

V

V

Philips Semiconductors Product specification

Video analog input interface TDA8709A

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

ADCIN INPUT (PIN 20; SEE TABLE 4)
V

20

V

20

V

20(p-p)

input voltage digital output = 00 − V

input voltage digital output = 255 − V

input voltage amplitude

− 1.0 − V

(peak-to-peak value)
I

20

| input impedance fi= 6 MHz − 50 − MΩ

|Z

i

C

I

input current − 1.0 10 µA

input capacitance fi = 6 MHz − 1 − pF

Analog-to-digital converter outputs

D

IGITAL OUTPUTS D0 TO D7

V

OL

V

OH

I

OZ

LOW level output voltage IOL = 2 mA 0 − 0.6 V

HIGH level output voltage IOL = −0.4 mA 2.4 − V

output current in 3-state mode 0.4 V < VO< V

CCD

−20 − +20 µA

Switching characteristics

f

clk(max)

Analog signal processing (f

G

diff

maximum clock input frequency see Fig.5; note 6 30 32 − MHz

= 32 MHz; see Fig.7)

clk

differential gain V20 = 1.0 V (p-p);

− 2 − %

see Fig.6; note 7

ϕ

diff

f

1

f

all

differential phase see Fig.6; note 7 − 2 − deg

fundamental harmonics (full-scale) fi= 4.43 MHz; note 7 −− 0dB

harmonics (full-scale);

fi= 4.43 MHz; note 7 −−55 − dB

all components
SVRR2 supply voltage ripple rejection note 8 − 1 5 %/V

− 2.52 − V

CCA

− 1.52 − V

CCA

CCD

V

Transfer function

ILE DC integral linearity error −− ±1 LSB
DLE DC differential linearity error −− ±0.5 LSB
ILE AC integral linearity error note 9 −− ±2 LSB

Timing (f

IGITAL OUTPUTS (C

D
t

ds

t

h

t

d

t

dEZ

t

dDZ

= 32 MHz; see Figs 5, 6 and 7)

clk

= 15 pF; IOL= 2 mA; RL=2kΩ)

L

sampling delay time − 2 − ns

output hold time − 8 − ns

output delay time − 16 20 ns

3-state delay time; output enable − 16 25 ns

3-state delay time; output disable − 12 25 ns

June 1994 8