Philips TDA8708-C2, TDA8708T-C2, TDA8708AT-C1, TDA8708A-C1 Datasheet

INTEGRATED CIRCUITS

TDA8708A

Video analog input interface

Product specification	June 1994
Supersedes data of April 1993
File under Integrated Circuits, IC02

Philips Semiconductors

Philips Semiconductors	Product specification
Video analog input interface	TDA8708A

FEATURES

∙8-bit resolution

∙Sampling rate up to 32 MHz

∙Binary or two's complement 3-state TTL outputs

∙TTL-compatible digital inputs and outputs

∙Internal reference voltage regulator

∙Power dissipation of 365 mW (typical)

∙Input selector circuit (one out of three video inputs)

∙Clamp and Automatic Gain Control (AGC) functions for CVBS and Y signals

∙No sample-and-hold circuit required.

∙The TDA8708A has white peak control in modes 1 and 2 whereas the TDA8708B has control in mode 1 only.

QUICK REFERENCE DATA

APPLICATIONS

∙Video signal decoding

∙Scrambled TV (encoding and decoding)

∙Digital picture processing

∙Frame grabbing.

GENERAL DESCRIPTION

The TDA8708A is an analog input interface for video signal processing. It includes a video amplifier with clamp and gain control, an 8-bit analog-to-digital converter (ADC) with a sampling rate of 32 MHz and an input selector.

SYMBOL		PARAMETER			MIN.		TYP.	MAX.	UNIT
VCCA		analog supply voltage			4.5		5.0	5.5	V
VCCD		digital supply voltage			4.5		5.0	5.5	V
VCCO		TTL output supply voltage			4.2		5.0	5.5	V
ICCA		analog supply current			−		37	45	mA
ICCD		digital supply current			−		24	30	mA
ICCO		TTL output supply current			−		12	16	mA
ILE		DC integral linearity error			−		−	±1	LSB
DLE		DC differential linearity error			−		−	±0.5	LSB
fclk(max)		maximum clock frequency			30		32	−	MHz
B		maximum −3 dB bandwidth (AGC amplifier)			12		18	−	MHz
Ptot		total power dissipation			−		365	500	mW
ORDERING INFORMATION
TYPE NUMBER				PACKAGE
		PINS		PIN POSITION	MATERIAL			CODE
TDA8708A		28		DIP		plastic		SOT117-1
TDA8708AT		28		SO28L		plastic		SOT136-1

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Philips Semiconductors	Product specification
Video analog input interface	TDA8708A
BLOCK DIAGRAM

				analog
	ndbook, full pagewidth	video input	video input	voltage	ADC	clock	decoupling	TTL outputs VCCO (+ 5 V)
		selection bit 0	selection bit 1	output	input	input	input

14

15

VIDEO

19

20

5

21

7

16

AMPLIFIER

output format/

video input 0

9

17

INPUT

8 - bit

chip enable

video input 1

AMP.

1

(3-state input)

18

SELECTOR

ADC

video input 2

D7

2

D6

clamp capacitor

24

3

D5

connection

TTL

4

D4

AGC capacitor

25

TDA8708A

OUTPUTS

10

connection

D3

11

D2

12

D1

PEAK LEVEL

13

AGC &

D0

DIGITAL COMPARATOR

CLAMP

LOGIC

BLACK LEVEL

&

MODE

DIGITAL COMPARATOR

peak level current

28

SELECTION

SYNC LEVEL

resistor input

DIGITAL COMPARATOR

27

26

6

8

22

23

MBB965

sync level	black level	digital VCCD	digital	analog VCCA	analog
sync pulse	sync pulse	(+ 5 V)	ground	(+ 5 V)	ground

Fig.1 Block diagram.

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Philips Semiconductors	Product specification
Video analog input interface	TDA8708A

PINNING

SYMBOL	PIN	DESCRIPTION
D7	1	data output; bit 7 (MSB)
D6	2	data output; bit 6
D5	3	data output; bit 5
D4	4	data output; bit 4
CLK	5	clock input
VCCD	6	digital supply voltage (+5 V)
VCCO	7	TTL outputs supply voltage (+5 V)
DGND	8	digital ground
OF	9	output format/chip enable
		(3-state input)
D3	10	data output; bit 3
D2	11	data output; bit 2
D1	12	data output; bit 1
D0	13	data output; bit 0 (LSB)
I0	14	video input selection bit 0
I1	15	video input selection bit 1
VIN0	16	video input 0
VIN1	17	video input 1
VIN2	18	video input 2
ANOUT	19	analog voltage output
ADCIN	20	analog-to-digital converter input
DEC	21	decoupling input
VCCA	22	analog supply voltage (+5 V)
AGND	23	analog ground
CLAMP	24	clamp capacitor connection
AGC	25	AGC capacitor connection
GATE B	26	black level synchronization pulse
GATE A	27	sync level synchronization pulse
RPEAK	28	peak level current resistor input

D7		1				28	RPEAK
D6		2				27	GATE A
D5		3				26	GATE B
D4		4				25	AGC
CLK		5				24	CLAMP
VCCD
		6				23	AGND
VCCO
		7	TDA8708A			22	VCCA
DGND		8				21	DEC
OF		9				20	ADCIN
D3		10					ANOUT
						19
							VIN2
D2		11				18
D1		12				17	VIN1
D0
		13				16	VIN0
I0							I1
		14				15
				MBB964

Fig.2 Pin configuration.

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Philips Semiconductors	Product specification
Video analog input interface	TDA8708A

FUNCTIONAL DESCRIPTION

The TDA8708A provides a simple interface for decoding video signals.

The TDA8708A operates in configuration mode 1 (see Fig.4) when the video signals are weak (i.e. when the gain of the AGC amplifier has not yet reached its optimum value). This enables a fast recovery of the synchronization pulses in the decoder circuit. When the pulses at the GATE A and GATE B inputs become distinct (GATE A and GATE B pulses are synchronization pulses occurring during the sync period and rear porch respectively) the TDA8708A automatically switches to configuration mode 2 (see Fig.5).

When the TDA8708A is in configuration mode 1, the gain of the AGC amplifier will be roughly adjusted (sync level to a digital output level of 0 and the peak level to a digital output level of 255).

In configuration mode 2 the digital output of the ADC is compared to internal digital reference levels. The resultant outputs control the charge or discharge current of a capacitor connected to the AGC pin. The voltage across this capacitor controls the gain of the video amplifier. This is the gain control loop.

LIMITING VALUES

The sync level comparator is active during a positive-going pulse at the GATE A input. This means that the sync pulse of the composite video signal is used as an amplitude reference. The bottom of the sync pulse is adjusted to obtain a digital output of logic 0 at the converter output. As the black level is at digital level 64, the sync pulse will have a digital amplitude of 64 LSBs.

The peak-white control loop is always active. If the video signal tends to exceed the digital code of 248, the gain will be limited to avoid any over-range of the converter.

The use of nominal signals will prevent the output from exceeding a digital code of 213 and the peak-white control loop will be non-active.

The clamp level control is accomplished by using the same techniques as used for the gain control. The black-level digital comparator is active during a positive-going pulse at the GATE B input. The clamp capacitor will be charged or discharged to adjust the digital output to code 64.

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL	PARAMETER		MIN.		MAX.		UNIT
VCCA	analog supply voltage		−0.3		+7.0		V
VCCD	digital supply voltage		−0.3		+7.0		V
VCCO	output supply voltage		−0.3		+7.0		V
VCC	supply voltage difference between VCCA and VCCD		−1.0		+1.0		V
	supply voltage difference between VCCO and VCCD		−1.0		+1.0		V
	supply voltage difference between VCCA and VCCO		−1.0		+1.0		V
VI	input voltage		−0.3		VCCA		V
IO	output current	0			+10		mA
Tstg	storage temperature		−55		+150		°C
Tamb	operating ambient temperature	0			+70		°C
Tj	junction temperature	0			+125		°C
THERMAL CHARACTERISTICS
SYMBOL	PARAMETER		VALUE				UNIT
Rth j-a	thermal resistance from junction to ambient in free air
	SOT117-1		55				K/W
	SOT136-1		70				K/W

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Philips Semiconductors	Product specification
Video analog input interface	TDA8708A

CHARACTERISTICS

VCCA = V22 to V23 = 4.5 to 5.5 V; VCCD = V6 to V8 = 4.5 to 5.5 V; VCCO = V7 to V8 = 4.2 to 5.5 V; AGND and DGND shorted together; VCCA to VCCD = −0.5 to +0.5 V; VCCO to VCCD = −0.5 to +0.5 V; VCCA to VCCO = −0.5 to +0.5 V;

Tamb = 0 to +70 °C; typical readings taken at VCCA = VCCD = VCCO = 5 V and Tamb = 25 °C; unless otherwise specified.

SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
Supplies
VCCA	analog supply voltage		4.5	5.0	5.5	V
VCCD	digital supply voltage		4.5	5.0	5.5	V
VCCO	TTL output supply voltage		4.2	5.0	5.5	V
ICCA	analog supply current		−	37	45	mA
ICCD	digital supply current		−	24	30	mA
ICCO	TTL output supply current	TTL load (see Fig.8)	−	12	16	mA
Video amplifier inputs
VIN(0 TO 2) INPUTS
VI(p-p)	input voltage (peak-to-peak value)	AGC load with external	0.6	−	1.5	V
		capacitor; note 1
|Zi|	input impedance	fi = 6 MHz	10	20	−	kΩ
CI	input capacitance	fi = 6 MHz	−	1	−	pF
I0 AND I1 TTL INPUTS (SEE TABLE 1)
VIL	LOW level input voltage		0	−	0.8	V
VIH	HIGH level input voltage		2.0	−	VCCD	V
IIL	LOW level input current	VI = 0.4 V	−400	−	−	μA
IIH	HIGH level input current	VI = 2.7 V	−	−	20	μA
GATE A AND GATE B TTL INPUTS (SEE FIGS 4 AND 5)
VIL	LOW level input voltage		0	−	0.8	V
VIH	HIGH level input voltage		2.0	−	VCCD	V
IIL	LOW level input current	VI = 0.4 V	−400	−	−	μA
IIH	HIGH level input current	VI = 2.7 V	−	−	20	μA
tW	pulse width	see Fig.5	2	−	−	μs
RPEAK INPUT (PIN 28)
I28(min)	minimum peak level current	R28 = 0 Ω	−	80	150	μA
AGC INPUT (PIN 25)
V25(min)	AGC voltage for minimum gain		−	2.8	−	V
V25(max)	AGC voltage for maximum gain		−	4.0	−	V
	AGC output current			see Table 2
CLAMP INPUT (PIN 24)
V24	clamp voltage for code 128 output		−	3.5	−	V
I24	clamp output current			see Table 3

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Philips Semiconductors				Product specification
Video analog input interface				TDA8708A
SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
Video amplifier outputs
ANOUT OUTPUT (PIN 19)
V19(p-p)	AC output voltage	VVIN = 1.33 V (p-p);	−	1.33	−	V
	(peak-to-peak value)	V25 = 3.6 V
I19	internal current source	RL = ∞	2.0	2.5	−	mA
IO(p-p)	output current driven by the load	VANOUT = 1.33 V (p-p);	−	−	1.0	mA
		note 2
V19	DC output voltage for black level	note 3	−	VCCA − 2.24	−	V
Z19	output impedance		−	20	−	Ω
Video amplifier dynamic characteristics
αct	crosstalk between VIN inputs	VCCA = 4.75 to 5.25 V	−	−50	−45	dB
Gdiff	differential gain	VVIN = 1.33 V (p-p);	−	2	−	%
		V25 = 3.6 V
ϕdiff	differential phase	VVIN = 1.33 V (p-p);	−	0.8	−	deg
		V25 = 3.6 V
B	−3 dB bandwidth		12	−	−	MHz
S/N	signal-to-noise ratio	note 4	60	−	−	dB
SVRR1	supply voltage ripple rejection	note 5	−	45	−	dB
G	gain range	see Fig.10	−4.5	−	+6.0	dB
Gstab	gain stability as a function of supply	see Fig.10	−	−	5	%
	voltage and temperature
Analog-to-digital converter inputs
CLK INPUT (PIN 5)
VIL	LOW level input voltage		0	−	0.8	V
VIH	HIGH level input voltage		2.0	−	VCCD	V
IIL	LOW level input current	Vclk = 0.4 V	−400	−	−	μA
IIH	HIGH level input current	Vclk = 2.7 V	−	−	100	μA
|Zi|	input impedance	fclk= 10 MHz	−	4	−	kΩ
CI	input capacitance	fclk = 10 MHz	−	4.5	−	pF
OF INPUT (3-STATE; SEE TABLE 4)
VIL	LOW level input voltage		0	−	0.2	V
VIH	HIGH level input voltage		2.6	−	VCCD	V
V9	input voltage in high impedance state		−	1.15	−	V
IIL	LOW level input current		−370	−300	−	μA
IIH	HIGH level input current		−	300	450	μA

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Philips Semiconductors				Product specification
Video analog input interface				TDA8708A
SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
ADCIN INPUT (PIN 20; SEE TABLE 5)
V20	input voltage	digital output = 00	−	VCCA − 2.42	−	V
V20	input voltage	digital output = 255	−	VCCA − 1.41	−	V
V20(p-p)	input voltage amplitude		−	1.0	−	V
	(peak-to-peak value)
I20	input current		−	1.0	10	μA
|Zi|	input impedance	fi = 6 MHz	−	50	−	MΩ
CI	input capacitance	fi = 6 MHz	−	1	−	pF
Analog-to-digital converter outputs
DIGITAL OUTPUTS D0 TO D7
VOL	LOW level output voltage	IOL = 2 mA	0	−	0.6	V
VOH	HIGH level output voltage	IOL = −0.4 mA	2.4	−	VCCD	V
IOZ	output current in 3-state mode	0.4 V < VO < VCCD	−20	−	+20	μA
Switching characteristics
fclk(max)	maximum clock input frequency	see Fig.6; note 6	30	32	−	MHz
Analog signal processing (fclk = 32 MHz; see Fig.8)
Gdiff	differential gain	V20 = 1.0 V (p-p);	−	2	−	%
		see Fig.3; note 7
ϕdiff	differential phase	see Fig.3; note 7	−	2	−	deg
f1	fundamental harmonics (full-scale)	fi = 4.43 MHz; note 7	−	−	0	dB
fall	harmonics (full-scale);	fi = 4.43 MHz; note 7	−	−55	−	dB
	all components
SVRR2	supply voltage ripple rejection	note 8	−	1	5	%/V
Transfer function (see Fig.8)
ILE	DC integral linearity error		−	−	±1	LSB
DLE	DC differential linearity error		−	−	±0.5	LSB
ILE	AC integral linearity error	note 9	−	−	±2	LSB
Timing (fclk = 32 MHz; see Figs 6, 7 and 8)
DIGITAL OUTPUTS (CL = 15 pF; IOL = 2 mA; RL = 2 kΩ)
tds	sampling delay time		−	2	−	ns
th	output hold time		6	8	−	ns
td	output delay time		−	16	20	ns
tdEZ	3-state delay time; output enable		−	19	25	ns
tdDZ	3-state delay time; output disable		−	14	20	ns

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