Philips tda8708b DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

TDA8708B

Video analog input interface

Product specification
Supersedes data of June 1994
File under Integrated Circuits, IC02

1996 Nov 26

Philips Semiconductors Product specification

Video analog input interface TDA8708B

FEATURES

• 8-bit resolution

• Sampling rate up to 32 MHz

• Binary or two’s complement 3-state TTL outputs

• TTL-compatible digital inputs and outputs

APPLICATIONS

• Video signal decoding

• Scrambled TV (encoding and decoding)

• Digital picture processing

• Frame grabbing.

• Internal reference voltage regulator

• Power dissipation of 365 mW (typical)

• Input selector circuit (one out of three video inputs)

• Clamp and Automatic Gain Control (AGC) functions for

CVBS and Y signals

• No sample-and-hold circuit required

GENERAL DESCRIPTION

The TDA8708B is an analog input interface for video signal
processing. It includes a video amplifier with clamp and
gain control, an 8-bit Analog-to-Digital Converter (ADC)
with a sampling rate of 32 MHz and an input selector.

• The TDA8708B has no white peak control in mode 2
whereas the TDA8708A has control in modes 1 and 2

• In-range output (not TTL levels).

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V
V
V
I

CCA

I

CCD

I

CCO

CCA
CCD
CCO

analog supply voltage 4.5 5.0 5.5 V
digital supply voltage 4.5 5.0 5.5 V
TTL output supply voltage 4.2 5.0 5.5 V
analog supply current − 37 45 mA
digital supply current − 24 30 mA

TTL output supply current − 12 16 mA
ILE DC integral linearity error −−±1 LSB
DLE DC differential linearity error −−±0.5 LSB
f

clk(max)

maximum clock frequency 30 32 − MHz
B maximum −3 dB bandwidth (AGC amplifier) 12 18 − MHz
P

tot

total power dissipation − 365 500 mW

ORDERING INFORMATION

TYPE NUMBER

TDA8708BT SO28 plastic small outline package; 28 leads; body width 7.5 mm SOT136-1

1996 Nov 26 2

PACKAGE

NAME DESCRIPTION VERSION

Philips Semiconductors Product specification

Video analog input interface TDA8708B

BLOCK DIAGRAM

handbook, full pagewidth

video input 0
video input 1
video input 2

clamp capacitor

connection

AGC capacitor

connection

in-range

output

video input

selection bit 0

16
17

SELECTOR

18

24

25

28

sync level

sync pulse

video input
selection bit 1

INPUT

AGC &

CLAMP

LOGIC

&

MODE

SELECTION

27 26

VIDEO

AMPLIFIER

black level
sync pulse

analog

voltage

output

digital V

(+ 5 V)

ADC
input

19 2014 15

AMP.

TDA8708B

PEAK LEVEL

DIGITAL COMPARATOR

BLACK LEVEL

DIGITAL COMPARATOR

SYNC LEVEL

DIGITAL COMPARATOR

6

CCD

8 22

digital

ground

clock

decoupling

input

input

521 7

8 - bit

ADC

analog V

CCA

(+ 5 V)

TTL outputs V (+ 5 V)

TTL

OUTPUTS

23

analog
ground

CCO

9
1

2
3

4
10
11
12
13

output format/

chip enable

(3-state input)

D7
D6
D5
D4
D3
D2
D1
D0

MSA672

1996 Nov 26 3

Fig.1 Block diagram.

Philips Semiconductors Product specification

Video analog input interface TDA8708B

PINNING

SYMBOL PIN DESCRIPTION

D7 1 data output; bit 7 (MSB)
D6 2 data output; bit 6
D5 3 data output; bit 5
D4 4 data output; bit 4
CLK 5 clock input
V
V

CCD
CCO

6 digital supply voltage (+5 V)

7 TTL outputs supply voltage (+5 V)
DGND 8 digital ground
OF 9 output format/chip enable

(3-state input)
D3 10 data output; bit 3
D2 11 data output; bit 2
D1 12 data output; bit 1
D0 13 data output; bit 0 (LSB)
I0 14 video input selection bit 0
I1 15 video input selection bit 1
VIN0 16 video input 0
VIN1 17 video input 1
VIN2 18 video input 2
ANOUT 19 analog voltage output
ADCIN 20 analog-to-digital converter input
DEC 21 decoupling input
V

CCA

22 analog supply voltage (+5 V)
AGND 23 analog ground
CLAMP 24 clamp capacitor connection
AGC 25 AGC capacitor connection
GATE B 26 black level synchronization pulse
GATE A 27 sync level synchronization pulse
IR 28 in-range output

1

D7

2

D6

3

D5

4

D4

5

CLK

V

6

CCD

V

7

CCO

DGND

OF
D3
D2
D1
D0

I0

TDA8708B

8

9
10
11
12
13

MSA671

Fig.2 Pin configuration.

28
27
26
25
24
23
22
21
20
19
18
17
16
1514

IR
GATE A
GATE B

AGC

CLAMP

AGND

V

CCA

DEC
ADCIN
ANOUT
VIN2

VIN1
VIN0

I1

1996 Nov 26 4

Philips Semiconductors Product specification

Video analog input interface TDA8708B

FUNCTIONAL DESCRIPTION

The TDA8708B provides a simple interface for decoding
video signals.

The TDA8708B operates in configuration mode 1
(see Fig.4) when the video signals are weak (i.e. when the
gain of the AGC amplifier has not yet reached its optimum
value). This enables a fast recovery of the synchronization
pulses in the decoder circuit. When the pulses at the
GATE A and GATE B inputs become distinct (GATE A and
GATE B pulses are synchronization pulses occurring
during the sync period and rear porch respectively) the
TDA8708B automatically switches to configuration mode 2
(see Fig.5).

When the TDA8708B is in configuration mode 1, the gain
of the AGC amplifier will be roughly adjusted (sync level to
a digital output level of 0 and the peak level to a digital
output level of 255).

The voltage across the capacitor connected to the AGC
pin controls the gain of the video amplifier. This is the gain
control loop.

The sync level comparator is active during a positive-going
pulse at the GATE A input. This means that the sync pulse
of the composite video signal is used as an amplitude
reference. The bottom of the sync pulse is adjusted to
obtain a digital output of logic 0 at the converter output.
As the black level is at digital level 64, the sync pulse will
have a digital amplitude of 64 LSBs.

The use of nominal signals will prevent the output from
exceeding a digital code of 213.

The clamp level control is accomplished by using the same
techniques as used for the gain control. The black-level
digital comparator is active during a positive-going pulse at
the GATE B input. The clamp capacitor will be charged or
discharged to adjust the digital output to code 64.

In configuration mode 2 the digital output of the ADC is
compared to internal digital reference levels.

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER MIN. MAX. UNIT

V
V
V
∆V

V
I

O

T
T
T

CCA
CCD
CCO

CC

I

stg
amb
j

analog supply voltage −0.3 +7.0 V
digital supply voltage −0.3 +7.0 V
TTL output supply voltage −0.3 +7.0 V
supply voltage differences:

− V

V
V
V

CCA
CCO
CCA

− V

− V

CCD

CCD

CCO

input voltage −0.3 V

−1.0 +1.0 V

−1.0 +1.0 V

−1.0 +1.0 V

CCA

output current 0 +10 mA
storage temperature −55 +150 °C
operating ambient temperature 0 +70 °C
junction temperature 0 +125 °C

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air 70 K/W

V

1996 Nov 26 5

Philips Semiconductors Product specification

Video analog input interface TDA8708B

CHARACTERISTICS

V

CCA=V22

shorted together; V
T

amb

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

CCA

V

CCD

V

CCO

I

CCA

I

CCD

I

CCO

Video amplifier inputs

VIN0
V

I(p-p)

 input impedance fi= 6 MHz 10 20 − kΩ

Z

i

C

i

I0 AND I1 TTL INPUTS (see Table 1)
V

IL

V

IH

I

IL

I

IH

GATE A AND GATE B TTL INPUTS (see Figs 4 and 5)
V

IL

V

IH

I

IL

I

IH

t

W

AGC INPUT (PIN 25)
V

25(min)

V

25(max)

CLAMP
V

24

I

24

to V23= 4.5 to 5.5 V; V

CCA

to V

= −0.5 to +0.5 V; V

CCD

CCD=V6

to V8= 4.5 to 5.5 V; V

= 0 to +70 °C; typical readings taken at V

analog supply voltage 4.5 5.0 5.5 V
digital supply voltage 4.5 5.0 5.5 V
TTL output supply voltage 4.2 5.0 5.5 V
analog supply current − 37 45 mA
digital supply current − 24 30 mA
TTL output supply current TTL load (see Fig.8) − 12 16 mA

TO VIN2 INPUTS

input voltage (peak-to-peak value) AGC load with external

input capacitance fi= 6 MHz − 1 − pF

LOW level input voltage 0 − 0.8 V
HIGH level input voltage 2.0 − V
LOW level input current VI= 0.4 V −400 −−µA
HIGH level input current VI= 2.7 V −− 20 µA

LOW level input voltage 0 − 0.8 V
HIGH level input voltage 2.0 − V
LOW level input current VI= 0.4 V −400 −−µA
HIGH level input current VI= 2.7 V −− 20 µA
pulse width see Fig.5 2 −−µs

AGC voltage for minimum gain − 2.8 − V
AGC voltage for maximum gain − 4.0 − V
AGC output current see Table 2

INPUT (PIN 24)

clamp voltage for code 128 output − 3.5 − V
clamp output current see Table 3

to V

CCO

CCA=VCCD=VCCO

= −0.5 to +0.5 V; V

CCD

capacitor; note 1

CCO=V7

= 5 V and T

to V8= 4.2 to 5.5 V; AGND and DGND

to V

CCA

=25°C; unless otherwise specified.

amb

= −0.5 to +0.5 V;

CCO

0.6 − 1.5 V

CCD

CCD

V

V

1996 Nov 26 6

Philips Semiconductors Product specification

Video analog input interface TDA8708B

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Video amplifier outputs

ANOUT OUTPUT (PIN 19)
V

19(p-p)

AC output voltage
(peak-to-peak value)

I

19

I

O(p-p)

V

19

Z

19

internal current source RL= ∞ 2.0 2.5 − mA
output current driven by the load V

DC output voltage for black level note 3 − V
output impedance − 20 −Ω

Video amplifier dynamic characteristics

α

ct

G

diff

ϕ

diff

crosstalk between VIN inputs V
differential gain V

differential phase V

B −3 dB bandwidth 12 −−MHz
S/N signal-to-noise ratio note 4 60 −−dB
SVRR1 supply voltage ripple rejection note 5 − 45 − dB
∆G gain range see Fig.10 −4.5 − +6.0 dB
G

stab

gain stability as a function of supply
voltage and temperature

V

= 1.33 V (p-p);

VIN

− 1.33 − V

V25= 3.6 V

ANOUT

= 1.33 V (p-p);

−− 1.0 mA

note 2

− 2.24 − V

CCA

= 4.75 to 5.25 V −−50 −45 dB

CCA

= 1.33 V (p-p);

VIN

− 2 − %

V25= 3.6 V

= 1.33 V (p-p);

VIN

− 0.8 − deg

V25= 3.6 V

see Fig.10 −− 5%

Analog-to-digital converter inputs

INPUT (PIN 5)

CLK
V

IL

V

IH

I

IL

I

IH

| input impedance f

|Z

i

C

I

LOW level input voltage 0 − 0.8 V
HIGH level input voltage 2.0 − V
LOW level input current V
HIGH level input current V

input capacitance f
OF INPUT (3-STATE; see Table 4)
V

IL

V

IH

V

9

I

IL

I

IH

LOW level input voltage 0 − 0.2 V

HIGH level input voltage 2.6 − V

input voltage in high impedance state − 1.15 − V

LOW level input current −370 −300 −µA

HIGH level input current − 300 450 µA

CCD

= 0.4 V −400 −−µA

clk

= 2.7 V −− 100 µA

clk

= 10 MHz − 4 − kΩ

clk

= 10 MHz − 4.5 − pF

clk

CCD

V

V

1996 Nov 26 7