INTEGRATED CIRCUITS
TDA8706A
6-bit analog-to-digital converter with multiplexer and clamp
Product specification |
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1996 Jul 30 |
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File under Integrated Circuits, IC02 |
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Philips Semiconductors |
Product specification |
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6-bit analog-to-digital converter
TDA8706A
with multiplexer and clamp
FEATURES
∙6-bit resolution
∙Binary 3-state CMOS outputs
∙CMOS compatible digital inputs
∙3 multiplexed video inputs
∙R, G and B clamps on code 0
∙Single 6-bit ADC operation allowed up to 40 MSPS
∙External control of clamping level
∙Internal reference voltage (external reference allowed)
∙Power dissipation only 36 mW (typical)
∙Operating temperature of −40 to +85 °C
∙Operating between 2.7 and 5.5 V.
APPLICATIONS
∙General purpose video applications
∙R, G and B signals
∙Automotive (car navigation)
∙LCD systems
∙Frame grabber.
GENERAL DESCRIPTION
The TDA8706A is a 6-bit analog-to-digital converter (ADC) with 3 analog multiplexed inputs. Each input has an analog clamp on code 0 for RGB video processing. Clamping level can also be adjusted externally up to code 20. It can also be used as a single 6-bit ADC.
QUICK REFERENCE DATA
SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
TYP. |
MAX. |
UNIT |
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VDDA |
analog supply voltage |
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2.7 |
3.0 |
5.5 |
V |
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VDDD |
digital supply voltage |
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2.7 |
3.0 |
5.5 |
V |
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VDDO |
output stages supply voltage |
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2.7 |
3.0 |
5.5 |
V |
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IDDA |
analog supply current |
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− |
7 |
10 |
mA |
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IDDD |
digital supply current |
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− |
4 |
6 |
mA |
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IDDO |
output stages supply current |
fclk = 40 MHz; ramp input |
− |
1 |
1.5 |
mA |
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INL |
integral non-linearity |
fclk = 40 MHz; ramp input; |
− |
±0.25 |
±0.6 |
LSB |
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Tamb = 25 °C |
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DNL |
differential non-linearity |
fclk = 40 MHz; ramp input; |
− |
±0.20 |
±0.5 |
LSB |
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Tamb = 25 °C |
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fclk(max) |
maximum clock frequency |
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40 |
− |
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MHz |
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Ptot |
total power dissipation |
fclk = 40 MHz; ramp input |
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3 V supplies |
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36 |
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mW |
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5.5 V supplies |
− |
− |
96 |
mW |
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ORDERING INFORMATION |
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TYPE |
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PACKAGE |
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NUMBER |
NAME |
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DESCRIPTION |
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VERSION |
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TDA8706AM |
SSOP24 |
plastic shrink small outline package; 24 leads; body width 5.3 mm |
SOT340-1 |
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1996 Jul 30 |
2 |
Philips Semiconductors |
Product specification |
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6-bit analog-to-digital converter
TDA8706A
with multiplexer and clamp
BLOCK DIAGRAM
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VCLPR |
VCLPB |
VCLPG |
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CLK |
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11 |
12 |
13 |
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24 |
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CLAMP |
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20 |
D5 |
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4 |
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CLP |
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19 |
D4 |
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8 |
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18 |
D3 |
RED |
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digital |
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6-BIT |
CMOS |
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voltage |
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MULTIPLEXER |
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ADC |
OUTPUTS |
17 |
outputs |
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D2 |
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GREEN |
9 |
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16 |
D1 |
BLUE |
10 |
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15 |
D0 |
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TDA8706A |
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VSSD |
22 |
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VDDA |
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REGULATOR |
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21 |
5 |
23 |
1 |
2 |
3 |
6 |
7 |
14 |
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MGD133 |
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VDDO |
VDDA |
VDDD |
SR |
SG |
SB |
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VRB |
V |
SSO |
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select |
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VSSA |
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inputs |
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Fig.1 |
Block diagram. |
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1996 Jul 30 |
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3 |
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Philips Semiconductors |
Product specification |
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6-bit analog-to-digital converter
TDA8706A
with multiplexer and clamp
PINNING
SYMBOL |
PIN |
DESCRIPTION |
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SR |
1 |
select input RED |
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SG |
2 |
select input GREEN |
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SB |
3 |
select input BLUE |
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CLP |
4 |
clamping pulse input (positive pulse) |
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VDDA |
5 |
analog supply voltage |
VRB |
6 |
reference voltage BOTTOM input |
VSSA |
7 |
analog ground |
RED |
8 |
RED input |
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GREEN |
9 |
GREEN input |
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BLUE |
10 |
BLUE input |
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VCLPR |
11 |
RED clamping voltage level input |
VCLPB |
12 |
BLUE clamping voltage level input |
VCLPG |
13 |
GREEN clamping voltage level input |
VSSO |
14 |
digital output ground |
D0 |
15 |
digital voltage output; bit 0 (LSB) |
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D1 |
16 |
digital voltage output; bit 1 |
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D2 |
17 |
digital voltage output; bit 2 |
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D3 |
18 |
digital voltage output; bit 3 |
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D4 |
19 |
digital voltage output; bit 4 |
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D5 |
20 |
digital voltage output; bit 5 |
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VDDO |
21 |
supply voltage for output stage |
VSSD |
22 |
digital ground |
VDDD |
23 |
digital supply voltage |
CLK |
24 |
clock input |
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handbook, halfpage |
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SR |
1 |
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24 |
CLK |
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SG |
2 |
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23 |
VDDD |
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SB |
3 |
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22 |
VSSD |
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CLP |
4 |
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21 |
VDDO |
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VDDA |
5 |
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20 |
D5 |
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VRB |
6 |
TDA8706A |
19 |
D4 |
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VSSA |
7 |
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18 |
D3 |
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RED |
8 |
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17 |
D2 |
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GREEN |
9 |
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16 |
D1 |
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BLUE |
10 |
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15 |
D0 |
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VCLPR |
11 |
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14 |
VSSO |
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VCLPB |
12 |
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13 |
VCLPG |
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MGD132 |
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Fig.2 Pin configuration.
1996 Jul 30 |
4 |
Philips Semiconductors |
Product specification |
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|
6-bit analog-to-digital converter
TDA8706A
with multiplexer and clamp
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL |
PARAMETER |
MIN. |
MAX. |
UNIT |
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VDDA |
analog supply voltage |
−0.3 |
+7.0 |
V |
VDDD |
digital supply voltage |
−0.3 |
+7.0 |
V |
VDD |
supply voltage difference |
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VDDA − VDDD |
−1.0 |
+1.0 |
V |
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VDDA − VDDO |
−1.0 |
+1.0 |
V |
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VDDD − VDDO |
−1.0 |
+1.0 |
V |
VI |
input voltage |
−0.3 |
+7.0 |
V |
IO |
output current |
− |
10 |
mA |
Tstg |
storage temperature |
−55 |
+150 |
°C |
Tamb |
operating ambient temperature |
−40 |
+85 |
°C |
Tj |
junction temperature |
− |
+150 |
°C |
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL |
PARAMETER |
VALUE |
UNIT |
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Rth j-a |
thermal resistance from junction to ambient in free air |
119 |
K/W |
1996 Jul 30 |
5 |
Philips Semiconductors |
Product specification |
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6-bit analog-to-digital converter
TDA8706A
with multiplexer and clamp
CHARACTERISTICS
VDDA = V5 to V7 = 2.7 to 5.5 V; VDDD = V23 to V22 = 2.7 to 5.5 V; VDDO = V21 to V14 = 2.7 to 5.5 V;
VSSA, VSSD and VSSO shorted together; Vi(p-p) = 0.7 V; Tamb = −40 to +85 °C; typical values measured at VDDA = VDDD = VDDO = 3 V and Tamb = 25 °C; unless otherwise specified.
SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
TYP. |
MAX. |
UNIT |
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Supply |
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VDDA |
analog supply voltage |
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2.7 |
3.0 |
5.5 |
V |
VDDD |
digital supply voltage |
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2.7 |
3.0 |
5.5 |
V |
VDDO |
output stages supply |
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2.7 |
3.0 |
5.5 |
V |
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voltage |
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VDD |
supply voltage difference |
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VDDA − VDDD |
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−0.3 |
− |
+0.3 |
V |
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VDDA − VDDO |
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−0.3 |
− |
+0.3 |
V |
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VDDD − VDDO |
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−0.3 |
− |
+0.3 |
V |
IDDA |
analog supply current |
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− |
7 |
10 |
mA |
IDDD |
digital supply current |
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− |
4 |
6 |
mA |
IDDO |
output stages supply current |
fclk = 40 MHz; ramp input |
− |
1 |
1.5 |
mA |
Inputs |
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CLOCK INPUT CLK (REFERENCED TO VSSD); note 1 |
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VIL |
LOW level input voltage |
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0 |
− |
VDDD × 0.3 |
V |
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VDDD < 3.3 V |
0 |
− |
VDDD × 0.2 |
V |
VIH |
HIGH level input voltage |
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VDDD × 0.7 |
− |
VDDD |
V |
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VDDD < 3.3 V |
VDDD × 0.8 |
− |
VDDD |
V |
IIL |
LOW level input current |
Vclk = VDDD × 0.2 |
−1 |
0 |
+1 |
μA |
IIH |
HIGH level input current |
Vclk = VDDD × 0.8 |
− |
2 |
10 |
μA |
Zi |
input impedance |
fclk = 40 MHz |
− |
4 |
− |
kΩ |
CI |
input capacitance |
fclk = 40 MHz |
− |
3 |
− |
pF |
INPUTS SR, SG, SB, CLP (REFERENCED TO VSSD) |
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VIL |
LOW level input voltage |
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0 |
− |
VDDD × 0.3 |
V |
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VDDD < 3.3 V |
0 |
− |
VDDD × 0.2 |
V |
VIH |
HIGH level input voltage |
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VDDD × 0.7 |
− |
VDDD |
V |
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VDDD < 3.3 V |
VDDD × 0.8 |
− |
VDDD |
V |
IIL |
LOW level input current |
VIL = VDDD × 0.2 |
−1 |
− |
− |
μA |
IIH |
HIGH level input current |
VIH = VDDD × 0.8 |
− |
− |
+1 |
μA |
INPUTS VCLPR, VCLPG AND VCLPB (REFERENCED TO VSSA); see Tables 1 and 2 |
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VCLP |
input voltage for clamping |
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Vcode −9 |
− |
Vcode 20 |
V |
ICLP |
input current |
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− |
− |
30 |
μA |
1996 Jul 30 |
6 |