Philips tda8703 DATASHEETS
INTEGRATED CIRCUITS
DATA SH EET
TDA8703
8-bit high-speed analog-to-digital
converter
Product specification
Supersedes data of April 1993
File under Integrated Circuits, IC02
1996 Aug 26
Philips Semiconductors Product specification
8-bit high-speed analog-to-digital
converter
FEATURES
• 8-bit resolution
• Sampling rate up to 40 MHz
• High signal-to-noise ratio over a large analog input
frequency range (7.1 effective bits at 4.43 MHz
full-scale input)
• Binary or two's complement 3-state TTL outputs
• Overflow/underflow 3-state TTL output
• TTL compatible digital inputs
• Low-level AC clock input signal allowed
• Internal reference voltage generator
• Power dissipation only 290 mW (typical)
• Low analog input capacitance, no buffer amplifier
required
• No sample-and-hold circuit required.
ORDERING INFORMATION
TDA8703
APPLICATIONS
• General purpose high-speed analog-to-digital
conversion
• Digital TV, IDTV
• Subscriber TV decoder
• Satellite TV decoders
• Digital VCR.
GENERAL DESCRIPTION
The TDA8703 is an 8-bit high-speed Analog-to-Digital
Converter (ADC) for video and other applications.
It converts the analog input signal into 8-bit binary-coded
digital words at a maximum sampling rate of 40 MHz.
All digital inputs and outputs are TTL compatible, although
a low-level AC clock input signal is allowed.
TYPE
NUMBER
TDA8703 DIP24 plastic dual in-line package; 24 leads (600 mil) SOT101-1
TDA8703T SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
NAME DESCRIPTION VERSION
PACKAGE
1996 Aug 26 2
Philips Semiconductors Product specification
8-bit high-speed analog-to-digital converter TDA8703
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
CCA
V
CCD
V
CCO
I
CCA
I
CCD
I
CCO
ILE DC integral linearity error −−±1 LSB
DLE DC differential linearity error −−±1/2 LSB
AILE AC integral linearity error note1 −−±2 LSB
B −3 dB bandwidth note 2; f
f
CLK/fCLK
P
tot
analog supply voltage 4.5 5.0 5.5 V
digital supply voltage 4.5 5.0 5.5 V
output stages supply voltage 4.2 5.0 5.5 V
analog supply current − 28 36 mA
digital supply current − 19 25 mA
output stages supply current − 11 14 mA
= 40 MHz − 19.5 − MHz
CLK
maximum conversion rate note 3 40 −−MHz
total power dissipation − 290 415 mW
Notes
1. Full-scale sinewave (f
= 4.4 MHz; f
i
CLK
; f
CLK
= 27 MHz).
2. The −3 dB bandwidth is determined by the 3 dB reduction in the reconstructed output (full-scale signal at input).
3. The circuit has two clock inputs CLK and CLK. There are four modes of operation:
a) TTL (mode 1); CLK decoupled to DGND by a capacitor. CLK input is TTL threshold voltage of 1.5 V and sampling
on the LOW-to-HIGH transition of the input clock signal.
b) TTL (mode 2); CLK decoupled to DGND by a capacitor.CLK input is TTL threshold voltage of 1.5 V and sampling
on the HIGH-to-LOW transition of the input clock signal.
c) AC drive modes (modes 3 and 4); When driving the CLK input directly and with any AC signal of 0.5 V
(peak-to-peak value) imposed on a DC level of 1.5 V, sampling takes place on the LOW-to-HIGH transition of the
clock signal. When driving the CLK input with such a signal, sampling takes place on the HIGH-to-LOW transition.
d) If one of the clock inputs is not driven, then it is recommended to decouple this input to DGND with a 100 nF
capacitor.
1996 Aug 26 3
Philips Semiconductors Product specification
8-bit high-speed analog-to-digital converter TDA8703
BLOCK DIAGRAM
clock inputs
handbook, full pagewidth
V
RT
analog
voltage input
V
RB
V
CCA
7
STABILIZER
5DEC
CLK
CLOCK DRIVER
CLK
V
181716
CCD
TC CE
21 22
TDA8703
TDA8703T
12
D7
MSB
D6
13
D5
14
D4
89VI
4
ANALOG - TO - DIGITAL
CONVERTER
3
AGND
20
DGND
LATCHES
OVERFLOW / UNDERFLOW
LATCH
TTL OUTPUTS
TTL OUTPUT
15
23
24 D2
19
11
MGA015
data outputs
D3
1
D1
2
D0
LSB
V
CCO
overflow /
underflow
output
analog ground digital ground
Fig.1 Block diagram.
1996 Aug 26 4
Philips Semiconductors Product specification
8-bit high-speed analog-to-digital converter TDA8703
PINNING
SYMBOL PIN DESCRIPTION
D1 1 data output; bit 1
D0 2 data output; bit 0 (LSB)
AGND 3 analog ground
V
RB
DEC 5 decoupling input (internal stabilization
n.c. 6 not connected
V
CCA
VI 8 analog voltage input
V
RT
n.c. 10 not connected
O/UF 11 overflow/underflow data output
D7 12 data output; bit7 (MSB)
D6 13 data output; bit6
D5 14 data output; bit5
D4 15 data output; bit4
CLK 16 clock input
CLK 17 complementary clock input
V
CCD
V
CCO
DGND 20 digital ground
TC 21 input for two's complement output (TTL
CE 22 chip enable input (TTL level input,
D3 23 data output; bit 3
D2 24 data output; bit 2
4 reference voltage bottom (decoupling)
loop decoupling)
7 positive supply voltage for analog
circuits (+5 V)
9 reference voltage top (decoupling)
18 positive supply voltage for digital
circuits (+5 V)
19 positive supply voltage for output
stages (+5 V)
level input, active LOW)
active LOW)
handbook, halfpage
1
D1
2
D0
V
RB
DEC
n.c.
CCA
V
RT
n.c.
O/UF
D7
VI
3
4
5
6
TDA8703/
TDA8703T
7
8
9
10
11
12
MLB034
AGND
V
Fig.2 Pin configuration.
24
D2
D3
23
22
CE
TC
21
DGND
20
V
CCO
19
V
CCD
18
17
CLK
CLK
16
D4
15
D5
14
D6
13
1996 Aug 26 5
Philips Semiconductors Product specification
8-bit high-speed analog-to-digital converter TDA8703
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
CCA
V
CCD
V
CCO
V
CCA
V
CCO
V
CCA
V
VI
V
CLK/VCLK
I
O
T
stg
T
amb
T
j
− V
− V
− V
analog supply voltage −0.3 +7.0 V
digital supply voltage −0.3 +7.0 V
output stages supply voltage −0.3 +7.0 V
supply voltage differences −1.0 +1.0 V
CCD
supply voltage differences −1.0 +1.0 V
CCD
supply voltage differences −1.0 +1.0 V
CCO
input voltage range referenced to AGND −0.3 +7.0 V
AC input voltage for switching
note 1; referenced to DGND − 2.0 V
(peak-to-peak value)
output current − +10 mA
storage temperature −55 +150 °C
operating ambient temperature 0 +70 °C
junction temperature − +125 °C
Notes
1. The circuit has two clock inputs CLK and
CLK. There are four modes of operation:
a) TTL (mode 1); CLK decoupled to DGND by a capacitor. CLK input is TTL threshold voltage of 1.5 V and sampling
on the LOW-to-HIGH transition of the input clock signal.
b) TTL (mode 2); CLK decoupled to DGND by a capacitor.CLK input is TTL threshold voltage of 1.5 V and sampling
on the HIGH-to-LOW transition of the input clock signal.
c) AC drive modes (modes 3 and 4); When driving the CLK input directly and with any AC signal of 0.5 V
(peak-to-peak value) imposed on a DC level of 1.5 V, sampling takes place on the LOW-to-HIGH transition of the
clock signal. When driving the CLK input with such a signal, sampling takes place on the HIGH-to-LOW transition.
d) If one of the clock inputs is not driven, then it is recommended to decouple this input to DGND with a 100 nF
capacitor.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL RESISTANCE
SYMBOL PARAMETER VALUE UNIT
R
th j-a
from junction to ambient in free air
SOT101-1 55 K/W
SOT137-1 75 K/W
1996 Aug 26 6
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