Philips TDA8358J-N1 Datasheet

DATA SH EET

Product specification
File under Integrated Circuits, IC02

1999 Dec 22

INTEGRATED CIRCUITS

TDA8358J

Fullbridgeverticaldeflectionoutput
circuit in LVDMOS with east-west
amplifier

1999 Dec 22 2

Philips Semiconductors Product specification

Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier

TDA8358J

FEATURES

• Few external components required

• High efficiency fully DC coupled vertical bridge output

circuit

• Vertical flyback switch with short rise and fall times

• Built-in guard circuit

• Thermal protection circuit

• Improved EMC performance due to differential inputs

• East-west output stage.

GENERAL DESCRIPTION

The TDA8358J is a power circuit for use in 90° and 110°
colour deflection systems for 25 to 200 Hz field
frequencies, and for 4 : 3 and 16 : 9picturetubes. The IC
contains a vertical deflection output circuit, operating as a
high efficiency class G system. The full bridge output
circuit allows DC coupling of the deflection coil in
combination with single positive supply voltages.

The east-west output stage is able to supply the sink
current for a diode modulator circuit.

The IC is constructed in a Low Voltage DMOS (LVDMOS)
process that combines bipolar, CMOS and DMOS
devices. DMOS transistors are used in the output stage
because of absence of second breakdown.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

P

supply voltage 7.5 12 18 V

V

FB

flyback supply voltage 2V

P

45 66 V

I

q(P)(av)

average quiescent supply current during scan − 10 15 mA

I

q(FB)(av)

average quiescent flyback supply current during scan −−10 mA

P

EW

east-west power dissipation −−4W

P

tot

total power dissipation −−15 W

Inputs and outputs

V

i(dif)(p-p)

differential input voltage (peak-to-peak value) − 1000 1500 mV

I

o(p-p)

output current (peak-to-peak value) −−3.2 A

Flyback switch

I

o(peak)

maximum (peak) output current t ≤ 1.5 ms −−±1.8 A

East-west amplifier

V

o

output voltage −−68 V

V

I(bias)

input bias voltage 2 − 3.2 V

I

o

output current −−750 mA

Thermal data; in accordance with IEC 747-1

T

stg

storage temperature −55 − +150 °C

T

amb

ambient temperature −25 − +75 °C

T

j

junction temperature −−150 °C

1999 Dec 22 3

Philips Semiconductors Product specification

Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier

TDA8358J

ORDERING INFORMATION

BLOCK DIAGRAM

TYPE

NUMBER

PACKAGE

NAME DESCRIPTION VERSION

TDA8358J DBS13P plastic DIL-bent-SIL power package; 13 leads (lead length 12 mm) SOT141-6

handbook, full pagewidth

MGL866

INPUT

AND

FEEDBACK

CIRCUIT

GUARD

CIRCUIT

TDA8358J

12

10

4

67

2

85

1

11 93

INA

INB

INEW

VGND EWGND

GUARD

V

P

V

FB

V

I(bias)

V

i(p-p)

V

I(bias)

0

V

i(p-p)

0

OUTB

OUTEW

OUTA

FEEDB

COMP.

CIRCUIT

13

COMP

I

I(av)

I

i(p-p)

0

M5

M2

M4

M1

M3

M6

D2

D3

D1

Fig.1 Block diagram.

1999 Dec 22 4

Philips Semiconductors Product specification

Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier

TDA8358J

PINNING FUNCTIONAL DESCRIPTION

Vertical output stage

The vertical driver circuit has a bridge configuration.
The deflection coil is connected between the
complimentary driven output amplifiers. The differential
input circuit is voltage driven. The input circuit is specially
designed for direct connection to driver circuits delivering
a differential signal but it is also suitable for single-ended
applications. The output currents of the driver device are
converted to voltages by the conversion resistors
R

CV1

and R

CV2

(see Fig.3) connected to pins INA
and INB. The differential input voltage is compared with
the voltage across the measuring resistor RM, providing
internal feedback information. The voltage across RM is
proportional with the output current. The relationship
between the differential input current and the output
current is defined by:

2 × I

i(dif)(p-p)

× RCV=I

o(p-p)

× R

M

The output current should measure 0.5 to 3.2 A (p-p) and
is determined by the value of RMand RCV. The allowable
input voltage range is 100 mV to 1.6 V for each input. The
formula given does not include internal bondwire
resistances.DependingonthevalueofRMandtheinternal
bondwireresistance (typical value 50 mΩ) the actualvalue
of the current in the deflection coil will be about 5% lower
than calculated.

Flyback supply

The flyback voltage is determined by the flyback supply
voltage VFB.The principle of two supply voltages (class G)
allows to use an optimum supply voltage VP for scan and
an optimum flyback supply voltage VFB for flyback, thus
very high efficiency is achieved. The available flyback
output voltage across the coil is almost equal to VFB, due
to the absence of a coupling capacitor which is not
required in a bridge configuration. The very short
rise and fall times of the flyback switch are determined
mainly by the slew-rate value of more than 300 V/µs.

Protection

The output circuit contains protection circuits for:

• Too high die temperature

• Overvoltage of output A.

SYMBOL PIN DESCRIPTION

INA 1 input A
INB 2 input B
V

P

3 supply voltage
OUTB 4 output B
INEW 5 east-west input
VGND 6 vertical ground
EWGND 7 east-west ground
OUTEW 8 east-west output
V

FB

9 flyback supply voltage
OUTA 10 output A
GUARD 11 guard output
FEEDB 12 feedback input
COMP 13 compensation input

handbook, halfpage

TDA8358J

MGL867

1
2
3
4
5
6
7
8

9
10
11
12
13

INA
INB

V

P

OUTB

INEW

VGND

EWGND

OUTEW

V

FB

OUTA

GUARD

FEEDB

COMP

Fig.2 Pin configuration.

Thedie hasbeen glued to the metal block ofthe package.If the metal
block is not insulated from the heatsink, the heatsink shall only be
connected directly to pin VGND.

1999 Dec 22 5

Philips Semiconductors Product specification

Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier

TDA8358J

Guard circuit

A guard circuit with output pin GUARD is provided.
The guard circuit generates a HIGH-level during the

flyback period. The guard circuit is also activated for one
of the following conditions:

• During thermal protection (Tj≈ 170 °C)

• During an open-loop condition.

The guard signal can be used for blanking the picture tube
and signalling fault conditions. The vertical
synchronization pulses of the guard signal can be used by
an On Screen Display (OSD) microcontroller.

Damping resistor compensation

HF loop stability is achieved by connecting a damping
resistor RD1 (see Fig.4) across the deflection coil.
The current values in RD1 during scan and flyback are
significantly different. Both the resistor current and the
deflection coil current flow into measuring resistor RM,
resulting in a too low deflection coil current at the start of
the scan.

The difference in the damping resistor current values
during scan and flyback have to be externally
compensated in order to achieve a short settling time.

For that purpose a compensation resistor R

CMP

is
connected between pins OUTA and COMP. The value of
R

CMP

is calculated by:

where:

• R

coil

is the coil resistance

• V

loss(FB)

isthe voltage loss between pins VFBand OUTA

at flyback.

East-west amplifier

The east-west amplifier is a current driver sinking the
current of a diode modulator circuit. A feedback
resistor R

EWF

(see Fig.4) has to be connected between
the input and output of the inverting east-west amplifier in
order to convert the east-west correction input current into
an output voltage. The output voltage of the east-west
circuit at pin OUTEW is given by:

Vo≈ Ii× R

EWF+Vi

The maximum output voltage is V

o(max)

= 68 V, while the

maximum output current of the circuit is I

o(max)

= 750 mA.

R

CMP

VFBV

loss FB()

– V

P

–()R

D1

× RS300+()×

V

FBVloss FB()

– I

coil peak()

R

coil

×–()R

M

×

-------------------------------------------------------------------------------------------------------------

=

1999 Dec 22 6

Philips Semiconductors Product specification

Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier

TDA8358J

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Notes

1. When the voltage at pin OUTA supersedes 70 V the circuit will limit the voltage.

2. Equivalent to 200 pF capacitance discharge through a 0 Ω resistor.

3. Equivalent to 100 pF capacitance discharge through a 1.5 kΩ resistor.

4. For repetitive time durations of t < 0.1 ms or a non repetitive time duration of t < 5 ms the maximum (peak) east-west
power dissipation P

EW(peak)

=15W.

5. Internally limited by thermal protection at Tj≈ 170 °C.

THERMAL CHARACTERISTICS

In accordance with IEC 747-1.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

P

supply voltage − 18 V

V

FB

flyback supply voltage − 68 V

∆V

VGND-EWGND

voltage difference between
pins VGND and EWGND

− 0.3 V

V

n

DC voltage

pins OUTA and OUTEW note 1 − 68 V
pin OUTB − V

P

V

pins INA, INB, INEW, GUARD,
FEEDB, and COMP

−0.5 V

P

V

I

n

DC current

pins OUTA and OUTB during scan (p-p) − 3.2 A
pins OUTA and OUTB at flyback (peak); t ≤ 1.5 ms −±1.8 A
pins INA, INB, INEW, GUARD,

FEEDB, and COMP

−20 +20 mA

pin OUTEW − 750 mA

I

lu

latch-up current input current into any pin;

pin voltage is 1.5 × VP; Tj= 150 °C

− +200 mA

input current out of any pin;
pin voltage is −1.5 × V

P

; Tj= 150 °C

−200 − mA

V

es

electrostatic handling voltage machine model; note 2 −300 +300 V

human body model; note 3 −2000 +2000 V

P

EW

east-west power dissipation note 4 − 4W

P

tot

total power dissipation − 15 W

T

stg

storage temperature −55 +150 °C

T

amb

ambient temperature −25 +75 °C

T

j

junction temperature note 5 − 150 °C

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-c)

thermal resistance from junction to case 4 K/W

R

th(j-a)

thermal resistance from junction to ambient in free air 40 K/W