Philips TDA8358J Datasheet

INTEGRATED CIRCUITS

DATA SH EET

TDA8358J

Fullbridgeverticaldeflectionoutput circuit in LVDMOS with east-west amplifier

Product speciﬁcation File under Integrated Circuits, IC02

1999 Dec 22

Philips Semiconductors Product speciﬁcation

Full bridge vertical deﬂection output circuit

TDA8358J

in LVDMOS with east-west ampliﬁer

FEATURES

• Few external components required

• High efficiency fully DC coupled vertical bridge output

circuit

• Vertical flyback switch with short rise and fall times

• Built-in guard circuit

• Thermal protection circuit

• Improved EMC performance due to differential inputs

• East-west output stage.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

q(P)(av)

q(FB)(av)

tot

supply voltage 7.5 12 18 V ﬂyback supply voltage 2V average quiescent supply current during scan − 10 15 mA average quiescent ﬂyback supply current during scan −−10 mA east-west power dissipation −−4W total power dissipation −−15 W

Inputs and outputs

i(dif)(p-p)

o(p-p)

differential input voltage (peak-to-peak value) − 1000 1500 mV output current (peak-to-peak value) −−3.2 A

Flyback switch

o(peak)

maximum (peak) output current t ≤ 1.5 ms −−±1.8 A

East-west ampliﬁer

V V I

o I(bias)

output voltage −−68 V input bias voltage 2 − 3.2 V output current −−750 mA

Thermal data; in accordance with IEC 747-1

stg

amb

storage temperature −55 − +150 °C ambient temperature −25 − +75 °C junction temperature −−150 °C

GENERAL DESCRIPTION

The TDA8358J is a power circuit for use in 90° and 110° colour deflection systems for 25 to 200 Hz field frequencies, and for 4 : 3 and 16 : 9picturetubes. The IC contains a vertical deflection output circuit, operating as a high efficiency class G system. The full bridge output circuit allows DC coupling of the deflection coil in combination with single positive supply voltages.

The east-west output stage is able to supply the sink current for a diode modulator circuit.

The IC is constructed in a Low Voltage DMOS (LVDMOS) process that combines bipolar, CMOS and DMOS devices. DMOS transistors are used in the output stage because of absence of second breakdown.

45 66 V

1999 Dec 22 2

Philips Semiconductors Product speciﬁcation

Full bridge vertical deﬂection output circuit

TDA8358J

in LVDMOS with east-west ampliﬁer

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

TDA8358J DBS13P plastic DIL-bent-SIL power package; 13 leads (lead length 12 mm) SOT141-6

BLOCK DIAGRAM

handbook, full pagewidth

I(bias)

COMP

COMP.

CIRCUIT

i(p-p)

INA

i(p-p)

FEEDBACK

CIRCUIT

GUARD

CIRCUIT

INPUT

AND

PACKAGE

11 93

OUTA

FEEDB

I(bias)

I(av)

i(p-p)

INB

INEW

Fig.1 Block diagram.

1999 Dec 22 3

TDA8358J

VGND EWGND

OUTB

OUTEW

MGL866

Philips Semiconductors Product speciﬁcation

Full bridge vertical deﬂection output circuit in LVDMOS with east-west ampliﬁer

PINNING FUNCTIONAL DESCRIPTION

SYMBOL PIN DESCRIPTION

INA 1 input A INB 2 input B V

3 supply voltage OUTB 4 output B INEW 5 east-west input VGND 6 vertical ground EWGND 7 east-west ground OUTEW 8 east-west output V

9 ﬂyback supply voltage OUTA 10 output A GUARD 11 guard output FEEDB 12 feedback input COMP 13 compensation input

handbook, halfpage

EWGND

OUTEW

GUARD

FEEDB

Thedie hasbeen glued to the metal block ofthe package.If the metal block is not insulated from the heatsink, the heatsink shall only be connected directly to pin VGND.

INA INB

OUTB

INEW

VGND

OUTA

COMP

1 2 3 4 5 6

TDA8358J

7 8

9 10 11 12 13

MGL867

Vertical output stage

The vertical driver circuit has a bridge configuration. The deflection coil is connected between the complimentary driven output amplifiers. The differential input circuit is voltage driven. The input circuit is specially designed for direct connection to driver circuits delivering a differential signal but it is also suitable for single-ended applications. The output currents of the driver device are converted to voltages by the conversion resistors R

CV1

and R

(see Fig.3) connected to pins INA

CV2

and INB. The differential input voltage is compared with the voltage across the measuring resistor RM, providing internal feedback information. The voltage across RM is proportional with the output current. The relationship between the differential input current and the output current is defined by:

2 × I

i(dif)(p-p)

× RCV=I

o(p-p)

× R

The output current should measure 0.5 to 3.2 A (p-p) and is determined by the value of RMand RCV. The allowable input voltage range is 100 mV to 1.6 V for each input. The formula given does not include internal bondwire resistances.DependingonthevalueofRMandtheinternal bondwireresistance (typical value 50 mΩ) the actualvalue of the current in the deflection coil will be about 5% lower than calculated.

Flyback supply

The flyback voltage is determined by the flyback supply voltage VFB.The principle of two supply voltages (class G) allows to use an optimum supply voltage VP for scan and an optimum flyback supply voltage VFB for flyback, thus very high efficiency is achieved. The available flyback output voltage across the coil is almost equal to VFB, due to the absence of a coupling capacitor which is not required in a bridge configuration. The very short rise and fall times of the flyback switch are determined mainly by the slew-rate value of more than 300 V/µs.

Protection

The output circuit contains protection circuits for:

• Too high die temperature

• Overvoltage of output A.

TDA8358J

Fig.2 Pin configuration.

1999 Dec 22 4

Philips Semiconductors Product speciﬁcation

Full bridge vertical deﬂection output circuit in LVDMOS with east-west ampliﬁer

Guard circuit

A guard circuit with output pin GUARD is provided. The guard circuit generates a HIGH-level during the

flyback period. The guard circuit is also activated for one of the following conditions:

• During thermal protection (Tj≈ 170 °C)

• During an open-loop condition.

The guard signal can be used for blanking the picture tube and signalling fault conditions. The vertical synchronization pulses of the guard signal can be used by an On Screen Display (OSD) microcontroller.

Damping resistor compensation

HF loop stability is achieved by connecting a damping resistor RD1 (see Fig.4) across the deflection coil. The current values in RD1 during scan and flyback are significantly different. Both the resistor current and the deflection coil current flow into measuring resistor RM, resulting in a too low deflection coil current at the start of the scan.

The difference in the damping resistor current values during scan and flyback have to be externally compensated in order to achieve a short settling time.

TDA8358J

For that purpose a compensation resistor R connected between pins OUTA and COMP. The value of R

is calculated by:

CMP

VFBV

CMP

– V

------------------------------------------------------------------------------------------------------------V

loss FB()

– I

FBVloss FB()

–()R

× RS300+()×

coil peak()

×–()R

where:

• R

is the coil resistance

coil

• V

isthe voltage loss between pins VFBand OUTA

loss(FB)

at flyback.

East-west ampliﬁer

The east-west amplifier is a current driver sinking the current of a diode modulator circuit. A feedback resistor R

(see Fig.4) has to be connected between

EWF

the input and output of the inverting east-west amplifier in order to convert the east-west correction input current into an output voltage. The output voltage of the east-west circuit at pin OUTEW is given by:

Vo≈ Ii× R The maximum output voltage is V

EWF+Vi

= 68 V, while the

o(max)

maximum output current of the circuit is I

CMP

coil

o(max)

= 750 mA.

1999 Dec 22 5

Philips Semiconductors Product speciﬁcation

Full bridge vertical deﬂection output circuit

TDA8358J

in LVDMOS with east-west ampliﬁer

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

∆V

VGND-EWGND

tot

stg

amb

supply voltage − 18 V ﬂyback supply voltage − 68 V voltage difference between

− 0.3 V

pins VGND and EWGND DC voltage

pins OUTA and OUTEW note 1 − 68 V pin OUTB − V pins INA, INB, INEW, GUARD,

−0.5 V

P P

FEEDB, and COMP

DC current

pins OUTA and OUTB during scan (p-p) − 3.2 A pins OUTA and OUTB at ﬂyback (peak); t ≤ 1.5 ms −±1.8 A pins INA, INB, INEW, GUARD,

−20 +20 mA

FEEDB, and COMP pin OUTEW − 750 mA

latch-up current input current into any pin;

− +200 mA

pin voltage is 1.5 × VP; Tj= 150 °C input current out of any pin;

pin voltage is −1.5 × V

; Tj= 150 °C

−200 − mA

electrostatic handling voltage machine model; note 2 −300 +300 V

human body model; note 3 −2000 +2000 V east-west power dissipation note 4 − 4W total power dissipation − 15 W storage temperature −55 +150 °C ambient temperature −25 +75 °C junction temperature note 5 − 150 °C

V V

Notes

1. When the voltage at pin OUTA supersedes 70 V the circuit will limit the voltage.

2. Equivalent to 200 pF capacitance discharge through a 0 Ω resistor.

3. Equivalent to 100 pF capacitance discharge through a 1.5 kΩ resistor.

4. For repetitive time durations of t < 0.1 ms or a non repetitive time duration of t < 5 ms the maximum (peak) east-west power dissipation P

EW(peak)

=15W.

5. Internally limited by thermal protection at Tj≈ 170 °C.

THERMAL CHARACTERISTICS

In accordance with IEC 747-1.

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R R

th(j-c) th(j-a)

thermal resistance from junction to case 4 K/W thermal resistance from junction to ambient in free air 40 K/W

1999 Dec 22 6

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