Philips TDA8357J Datasheet

INTEGRATED CIRCUITS

DATA SH EET

TDA8357J

Fullbridgeverticaldeflectionoutput circuit in LVDMOS

Preliminary speciﬁcation File under Integrated Circuits, IC02

1999 Nov 10

Philips Semiconductors Preliminary speciﬁcation

Full bridge vertical deﬂection outputcircuit

TDA8357J

in LVDMOS

FEATURES

• Few external components required

• High efficiency fully DC coupled vertical bridge output

circuit

• Vertical flyback switch with short rise and fall times

• Built-in guard circuit

• Thermal protection circuit

• Improved EMC performance due to differential inputs.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

q(P)(av)

q(FB)(av)

tot

supply voltage 7.5 12 18 V ﬂyback supply voltage 2V average quiescent supply current during scan − 10 15 mA average quiescent ﬂyback supply current during scan −−10 mA total power dissipation −−8W

Inputs and outputs

i(dif)(p-p)

o(p-p)

differential input voltage (peak-to-peak value) − 1000 1500 mV output current (peak-to-peak value) −−2.0 A

Flyback switch

o(peak)

maximum (peak) output current t ≤ 1.5 ms −−±1.2 A

Thermal data; in accordance with IEC 747-1

stg

amb

storage temperature −55 − +150 °C ambient temperature −25 − +75 °C junction temperature −−150 °C

GENERAL DESCRIPTION

The TDA8357J is a power circuit for use in 90° and 110° colour deflection systems for 25 to 200 Hz field frequencies, and for 4 : 3 and 16 : 9 picturetubes. The IC contains a vertical deflection output circuit, operating as a high efficiency class G system. The full bridge output circuit allows DC coupling of the deflection coil in combination with single positive supply voltages.

The IC is constructed in a Low Voltage DMOS (LVDMOS) process that combines bipolar, CMOS and DMOS devices. DMOS transistors are used in the output stage because of absence of second breakdown.

45 66 V

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

TDA8357J DBS9P plastic DIL-bent-SIL power package; 9 leads (lead length

12/11 mm); exposed die pad

1999 Nov 10 2

SOT523-1

Philips Semiconductors Preliminary speciﬁcation

Full bridge vertical deﬂection output circuit in LVDMOS

BLOCK DIAGRAM

handbook, full pagewidth

I(bias)

i(p-p)

INA

i(p-p)

INB

GUARD

863

GUARD

CIRCUIT

INPUT

AND

FEEDBACK

CIRCUIT

TDA8357J

OUTA

FEEDB

OUTB

PINNING

SYMBOL PIN DESCRIPTION

INA 1 input A INB 2 input B V

3 supply voltage OUTB 4 output B GND 5 ground V

6 ﬂyback supply voltage OUTA 7 output A GUARD 8 guard output FEEDB 9 feedback input

GND

Fig.1 Block diagram.

handbook, halfpage

TDA8357J

INA INB

OUTB

GND

OUTA

GUARD

FEEDB

MGS803

1 2 3 4 5

TDA8357J

6 7 8 9

MGS804

1999 Nov 10 3

The exposed die pad is connected to pin GND.

Fig.2 Pin configuration.

Philips Semiconductors Preliminary speciﬁcation

Full bridge vertical deﬂection output circuit in LVDMOS

FUNCTIONAL DESCRIPTION Vertical output stage

The vertical driver circuit has a bridge configuration. The deflection coil is connected between the complimentary driven output amplifiers. The differential input circuit is voltage driven. The input circuit is specially designed for direct connection to driver circuits delivering a differential signal but it is also suitable for single-ended applications. The output currents of the driver device are converted to voltages by the conversion resistors R

and R

CV1

and INB. The differential input voltage is compared with the voltage across the measuring resistor RM, providing internal feedback information. The voltage across RM is proportional with the output current. The relationship between the differential input current and the output current is defined by:

2 × I

i(dif)(p-p)

The output current should measure 0.5 to 2.0 A (p-p) and is determined by the value of RMand RCV. The allowable input voltage range is 100 mV to 1.6 V for each input. The formula given does not include internal bondwire resistances. Depending on the values of RM and the internal bondwire resistance (typical value of 50 mΩ) the actual value of the current in the deflection coil will be about 5% lower than calculated.

Flyback supply

The flyback voltage is determined by the flyback supply voltage VFB.Theprincipleoftwosupplyvoltages(class G) allows to use an optimum supply voltage VP for scan and an optimum flyback supply voltage VFB for flyback, thus very high efficiency is achieved. The available flyback output voltage across the coil is almost equal to VFB, due to the absence of a coupling capacitor which is not required in a bridge configuration. The very short rise and fall times of the flyback switch are determined mainly by the slew-rate value of more than 300 V/µs.

(see Fig.3) connected to pins INA

CV2

× RCV=I

o(p-p)

× R

TDA8357J

Guard circuit

A guard circuit with output pin GUARD is provided. The guard circuit generates a HIGH-level during the

flyback period. The guard circuit is also activated for one of the following conditions:

• During thermal protection (Tj≈ 170 °C)

• During an open-loop condition.

The guard signal can be used for blanking the picture tube and signalling fault conditions. The vertical synchronization pulses of the guard signal can be used by an On Screen Display (OSD) microcontroller.

Damping resistor compensation

HF loop stability is achieved by connecting a damping resistor RD1across the deflection coil. The current values in RD1 during scan and flyback are significantly different. Boththeresistorcurrentandthe deflection coil current flow intomeasuringresistor RM,resultinginatoolowdeflection coil current at the start of the scan.

The difference in the damping resistor current values during scan and flyback have to be externally compensated in order to achieve a short settling time. For that purpose a compensation resistor R with a zener diode is connected between pins OUTA and INA(see Fig.4). The zener diode voltage value should be equal to VP. The value of R

VFBV

– V

CMP

-----------------------------------------------------------------------------------------------------------V

FBVloss FB()

loss FB()

– I

is calculated by:

CMP

–()R

× R

coil peak()

×–()R

where:

• V

is the voltage loss between pins VFBand OUTA

loss(FB)

at flyback

• R

is the deflection coil resistance

coil

• VZ is the voltage of zener diode D5.

in series

CMP

CV1

coil

Protection

The output circuit contains protection circuits for:

• Too high die temperature

• Overvoltage of output A.

1999 Nov 10 4

Philips Semiconductors Preliminary speciﬁcation

Full bridge vertical deﬂection output circuit

TDA8357J

in LVDMOS

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

tot

stg

amb

supply voltage − 18 V ﬂyback supply voltage − 68 V DC voltage

pin OUTA note 1 − 68 V pin OUTB − V pins INA, INB, GUARD and FEEDB −0.5 V

DC current

pins OUTA and OUTB during scan (p-p) − 2.0 A pins OUTA and OUTB at ﬂyback (peak); t ≤ 1.5 ms −±1.2 A pins INA, INB, GUARD and FEEDB −20 +20 mA

latch-up current current into any pin; pin voltage

− +200 mA

is 1.5 × VP; note 2 current out of any pin; pin voltage

is −1.5 × V

; note 2

−200 − mA

electrostatic handling voltage machine model; note 3 −300 +300 V

human body model; note 4 −2000 +2000 V total power dissipation − 8W storage temperature −55 +150 °C ambient temperature −25 +75 °C junction temperature note 5 − 150 °C

Notes

1. When the voltage at pin OUTA supersedes 70 V the circuit will limit the voltage.

2. At T

j(max)

3. Equivalent to 200 pF capacitance discharge through a 0 Ω resistor.

4. Equivalent to 100 pF capacitance discharge through a 1.5 kΩ resistor.

5. Internally limited by thermal protection at Tj≈ 170 °C.

THERMAL CHARACTERISTICS

In accordance with IEC 747-1.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

R R

th(j-c) th(j-a)

thermal resistance from junction to case −−6 K/W thermal resistance from junction to ambient in free air −−65 K/W

1999 Nov 10 5

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