Philips tda4671 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

TDA4671

Picture Signal Improvement (PSI)
circuit

Product specification
Supersedes data of June 1993
File under Integrated Circuits, IC02

1996 Dec 11

Philips Semiconductors Product specification

Picture Signal Improvement (PSI) circuit TDA4671

FEATURES

• Luminance signal delay from 20 to 1100 ns (minimum
step 45 ns)

• Luminance signal peaking with symmetrical overshoots
selectable

• Selectable 2.6 or 5 MHz peaking centre frequency and
degree of peaking (−3, 0, +3 and +6 dB)

• Selectable noise reduction by coring

• Handles negative as well as positive colour-difference

signals

• Selectable Colour Transient Improvement (CTI) to
decrease the colour-difference signal transient times to
those of the high frequency luminance signals

• Selectable 5 or 12 V sandcastle input voltage

2

• All controls selected via the I

C-bus

• Timing pulse generation for clamping and delay time
control synchronized by sandcastle pulse

• Automatic luminance signal delay correction using a
control loop

• Luminance and colour-difference input signal clamping
with coupling capacitor

• 4.5 to 8.8 V supply voltage range

• Minimum of external components.

GENERAL DESCRIPTION

The TDA4671 delays the luminance signal and improves
colour-difference signal transients. The luminance signal
can also be improved by peaking and noise reduction
(coring).

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V

P

I

P(tot)

t

d(Y)

V

i(VBS)(p-p)

supply voltage (pins 1 and 5) 4.5 5 8.8 V
total supply current 31 41 52 mA
Y signal delay time 20 − 1130 ns
composite Y input signal (peak-to-peak value,

− 450 640 mV

pin 16)

V

i(CD)(p-p)

colour-difference input signal
(peak-to-peak value)

±(R − Y) on pin 3 − 1.05 1.48 V
±(R − Y) on pin 7 − 1.33 1.88 V

G

Y

G

CD

T

amb

gain of Y channel −−1−dB
gain of colour-difference channel − 0 − dB
operating ambient temperature 0 − 70 °C

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

TDA4671 DIP18 plastic dual in-line package; 18 leads (300 mil) SOT102-1

1996 Dec 11 2

Philips Semiconductors Product specification

Picture Signal Improvement (PSI) circuit TDA4671

BLOCK DIAGRAM

nF

100 nF

15

1

= 5 to 8 V

P1

V

SCL

ref

V

GENERATION

degree of

peaking

peaking

frequency

coring

on/off

ref

V

CORING

+

−0.5

5 MHz

90

2.6 MHz

ns

100

11

CORING

−0.5

5 MHz

C-BUS

2

I

2.6 MHz

PEAKING

C-BUS

2

I

BLACK

+

+1

LEVEL

100

CLAMP

ns

Y

12

TDA4671

analog switch

capacitors

comparator

−(B − Y)
6

MED746

analog switch

= 5 to 8 V

P2

V

−(R − Y)
4

storage

C-BUS

2

I

T

V

9 10

SDA

100 nF

2

sandcastle

pulse

17

CTI

on/off

C-BUS RECEIVER

2

I

ref

5 V/12 V

V

sandcastle

Y delay

ref

CONTROL

V

DELAY TIME

C-BUS

2

I

BK, H + V

BK

DETECTOR

SANDCASTLE PULSE

ns

100

ref

V

CLAMP

BLACK LEVEL

16

control signal

ns

90

ns

45

ns

90

ns

180

LEVEL

BLACK

ns

180

ns

450

CLAMP

V

FILTER

HIGH-PASS

8 18 5

handbook, full pagewidth

Fig.1 Block diagram.

RECTIFIER

FULL-WAVE

ref

V

CLAMP

14

BLACK LEVEL

3

ref

RECTIFIER

FULL-WAVE

DIFFERENTIATOR

DIFFERENTIATOR

BK

BLACK LEVEL

7

CLAMP

ref

V

100 nF

Y

1996 Dec 11 3

100 nF13100 nF

−(R − Y)

10 nF

10 nF

−(B − Y)

Philips Semiconductors Product specification

Picture Signal Improvement (PSI) circuit TDA4671

PINNING

SYMBOL PIN DESCRIPTION

V

P1

C

DL

V

i(R − Y)

V

o(R − Y)

V

P2

V

o(B − Y)

V

i(B − Y)

GND2 8 ground 2 (0 V)
SDA 9 I
SCL 10 I
C

COR

V

oY

C

CLP1

C

CLP2

C

ref

V

iY

SAND 17 sandcastle pulse input
GND1 18 ground 1 (0 V)

1 positive supply voltage 1
2 capacitor of delay time control
3 ±(R − Y) colour-difference input signal

±(R − Y) colour-difference output

4

signal

5 positive supply voltage 2

±(B − Y) colour-difference output

6

signal

7 ±(B − Y) colour-difference input signal

2

C-bus serial data input/output

2

C-bus serial clock input
11 coring capacitor
12 delayed luminance output signal
13 black level clamping capacitor 1
14 black level clamping capacitor 2
15 capacitor of reference voltage
16 luminance input signal

handbook, halfpage

V

1

P1

C

2

DL

V

i(R − Y)

V

o(R − Y)

V

o(B − Y)

V

i(B − Y)

V

P2

GND2

SDA

3
4
5
6
7
8
9

TDA4671

Fig.2 Pin configuration.

MED747

GND1

18

SAND

17

V

16

iY

C

15

ref

C

14

CLP2

C

13

CLP1

V

12

oY

C

11

COR

SCL

10

1996 Dec 11 4

Philips Semiconductors Product specification

Picture Signal Improvement (PSI) circuit TDA4671

FUNCTIONAL DESCRIPTION

The TDA4671 contains luminance signal processing and
colour-difference signal processing. The luminance signal
section comprises a variable, integrated luminance delay
line with luminance signal peaking and a noise reduction
by coring.

The colour-difference section consists of a transient
improvement circuit to decrease the rise and fall times of
the colour-difference signal transients. All functions and
parameters are controlled via the I2C-bus.

Y-signal path

The video and blanking signal is AC-coupled to the input
pin 16. Its black porch is clamped to a DC reference
voltage to ensure the correct operating range of the
luminance delay stage.

The luminance delay line consists of all-pass filter sections
with delay times of 45, 90, 100, 180 and 450 ns
(see Fig.1). The luminance signal delay is controlled via

2

the I

C-bus in steps of 45 ns in the range of 20 to 1100 ns,
this ensures that the maximum delay difference between
the luminance and colour-difference signals is ±22.5 ns.

An automatic luminance delay time adjustment in an
internal control loop (with the horizontal frequency as a
reference) is used to correct changes in the delay time,
due to component tolerances. The control loop is
automatically enabled between the burst key pulses of
lines 16 (330) and 17 (331) during the vertical blanking
interval. The control voltage is stored in capacitor C

DL

connected to pin 2.
The peaking section is using a transversal filter circuit with

selectable centre frequencies of 2.6 and 5.0 MHz.

The output buffer stage ensures a low-ohmic VBS output
signal on pin 12 (<160 Ω). The gain of the luminance
signal path from pin 16 to pin 12 is unity.

An oscillation signal of the delay time control loop is
present on output pin 12 instead of the VBS signal. It is
present during the vertical blanking interval of the burst key
pulses in lines 16 (330) to 18 (332). This sync should not
be applied for synchronization.

Colour-difference signal paths

The colour-difference input signals (on pins 3 and 7) are
clamped to a reference voltage.

Each colour-difference signal is fed to a transient detector
and to an analog signal switch with an attached voltage
storage stage.

The transient detectors consist of differentiators and
full-wave rectifiers. The output voltages of both transient
detectors are added and then compared. The comparator
controls both following analog signal switches
simultaneously.

The analog signal switches are in open position at a
certain value of transient time; the held value (held by
capacitors) is then applied to the outputs. The switches
close to rapidly accept the actual signal levels at the end
of these transients. The improved transient time is
approximately 100 ns long independent of the input
transient time.

Colour-difference paths are independent of the input
signal polarity and have a nominal unity gain.

2

The CTI functions are switched on and off via the I

C-bus.

It provides selectable degrees of peaking of −3, 0, +3 and
+6 dB and noise reduction by coring, which attenuates the
high-frequency noise introduced by peaking.

1996 Dec 11 5