Philips TDA1386T Datasheet

INTEGRATED CIRCUITS

DATA SH EET

TDA1386T

Noise shaping filter DAC

Product specification
Supersedes data of 1995 Dec 11
File under Integrated Circuits, IC01

1998 Jan 06

Philips Semiconductors Product specification

Noise shaping filter DAC TDA1386T

FEATURES
General

• Double-speed mode

• Digital volume control

• Soft mute function

• 12 dB attenuation

• Low power dissipation

• Digital de-emphasis

Easy application

• Voltage output

• Only 1st-order analog post-filtering required

• Operational amplifiers and digital filter integrated

• 256fs system clock (f

• I2S-bus or 16, 18 or 20 bits LSB fixed serial input format

• Single rail supply.

High performance

• Superior signal-to-noise ratio

• Wide dynamic range

• No zero crossing distortion

• Inherently monotonic

• Continuous calibration digital-to-analog conversion

combined with noise shaping technique.

.

)

sys

GENERAL DESCRIPTION

The TDA1386T is a dual CMOS digital-to-analog converter
with up-sampling filter and noise shaper. The combination
of oversampling up to 4f
calibration conversion ensures that only simple 1st order
analog post filtering is required.

The TDA1386T supports the I2S-bus data input mode with
word lengths of up to 20 bits and the LSB fixed serial data
input format with word lengths of 16, 18 or 20 bits.
Two cascaded IIR filters increase the sampling rate
4 times.

The DACs are of the continuous calibration type and
incorporate a special data coding. This ensures a high
signal-to-noise ratio, wide dynamic range and immunity to
process variation and component ageing.

Two on-board operational amplifiers convert the
digital-to-analog current to an output voltage.

, noise shaping and continuous

s

ORDERING INFORMATION

TYPE NUMBER

NAME DESCRIPTION VERSION

TDA1386T SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1

1998 Jan 06 2

PACKAGE

Philips Semiconductors Product specification

Noise shaping filter DAC TDA1386T

QUICK REFERENCE DATA

All power supply pins V

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V
V
V

DDD
DDA
DDO

digital supply voltage 4.5 5.0 5.5 V
analog supply voltage 4.5 5.0 5.5 V
operational amplifier supply

voltage

I

DDD

I

DDA

I

DDO

digital supply current V

analog supply current V

operational amplifier supply
current

Analog signals

V

FS(rms)

full-scale output voltage
(RMS value)

R

L

output load resistance 5 −−kΩ

DAC performance

(THD + N)/S total harmonic distortion

plus noise-to-signal ratio

S/N signal-to-noise ratio no signal; A-weighted −−108 −96 dB
BR input bit rate at data input f

f

sys

T

amb

clock frequency 6.4 − 18.432 MHz
operating ambient

temperature

and GND must be connected to the same external supply unit.

DD

4.5 5.0 5.5 V

DDD

=5 V;

− 58mA

at code 00000H

DDA

=5 V;

− 35mA

at code 00000H
V

DDO

=5 V;

− 24mA

at code 00000H

V

DDD=VDDA=VDDO

=5V;

0.935 1.1 1.265 V

ROL>5kΩ

at 0 dB signal level;
fi= 1 kHz

at −60 dB signal level;
fi= 1 kHz

= 44.1 kHz; normal speed −−2.822 bits

s

f

= 44.1 kHz; double speed −−5.645 bits

s

−−70 − dB

− 0.032 − %

−−42 −32 dB

− 0.8 2.5 %

−40 − +85 °C

1998 Jan 06 3

Philips Semiconductors Product specification

Noise shaping filter DAC TDA1386T

BLOCK DIAGRAM

Fig.1 Block diagram.

1998 Jan 06 4

Philips Semiconductors Product specification

Noise shaping filter DAC TDA1386T

PINNING

SYMBOL PIN DESCRIPTION

V

DDA

AGND 2 analog ground
TEST1 3 test input 1; pin should be

BCK 4 bit clock input
WS 5 word select input
DATA 6 data input
CKSL1 7 format selection 1
CKSL2 8 format selection 2
DGND 9 digital ground
V

DDD

TEST2 11 test input 2; pin should be

SYSCLK 12 system clock 256f
APP3 13 application mode 3 input
APPL 14 application mode selection input
APP2 15 application mode 2 input
APP1 16 application mode 1 input
APP0 17 application mode 0 input
VOL 18 left channel output
FILTCL 19 capacitor for left channel 1st-order

FIL TCR 20 capacitor for right channel 1st-order

VOR 21 right channel output
V

ref

OGND 23 operational amplifier ground
V

DDO

1 analog supply voltage

connected to DGND

10 digital supply voltage

connected to DGND

s

filter function, should be connected
between pins 19 and 18

filter function, should be connected
between pins 20 and 21

22 internal reference voltage for output

channels (0.5V

DDO

typ.)

24 operational amplifier supply voltage

Fig.2 Pin configuration.

1998 Jan 06 5

Philips Semiconductors Product specification

Noise shaping filter DAC TDA1386T

FUNCTIONAL DESCRIPTION

The TDA1386T CMOS DAC incorporates an up-sampling
filter, a noise shaper, continuous calibrated current
sources and operational amplifiers.

System clock and data input format

The TDA1386T accommodates slave mode only
consequently, in all applications, the system devices must
provide the 256f

system clock.

s

Table 1 Data input format and system clock

CKSL1 CKSL2 DATA INPUT FORMAT

2

00I

S-bus 256f
0 1 LSB fixed 16 bits 256f
1 0 LSB fixed 18 bits 256f
1 1 LSB fixed 20 bits 256f

Device operation

When the APPL pin is held HIGH and APP3 is held LOW,
pins APP0, APP1 and APP2 form a microcontroller
interface. When the APPL pin is held LOW, pins APP0,
APP1, APP2 and APP3 form pseudo-static application
pins (TDA1305T pin compatible).

The TDA1386T supports the following data input modes:

2

• I

S-bus with data word length of up to 20 bits.

• LSB fixed serial format with data word length of 16, 18
or 20 bits. As this format idles on the MSB it is necessary
to know how many bits are being transmitted.

The data input formats are illustrated in Fig.7. Left and
right data-channel words are time multiplexed.

SYSTEM CLOCK

NORMAL SPEED DOUBLE SPEED

s
s
s
s

128f
128f
128f
128f

s
s
s
s

In the pseudo-static application mode the TDA1386T is pin
compatible with the TDA1305T slave mode. The
correspondence between TDA1386T pin number,
TDA1386T pin name, TDA1305T pin name and a
description of the effects is given in Table 2.

P

SEUDO-STATIC APPLICATION MODE (APPL = LOGIC 0)

In this mode, the device operation is controlled by
pseudo-static application pins (APP0: attenuation mode
control; APP1: double-speed mode control; APP2: mute
mode control and APP3: de-emphasis mode control).

Table 2 Pseudo-static application mode

PIN NAME PIN NUMBER

TDA1305T

FUNCTION

LOGIC

VALUE

DESCRIPTION

APP0 17 ATSB 0 12 dB attenuation (from full scale) activated

(only if MUSB = 1)

1 full scale (only if MUSB = 1)

APP1 16 DSMB 0 double-speed mode

1 normal-speed mode

APP2 15 MUSB 0 samples decrease to mute level

1 level in accordance with ATSB

APP3 13 DEEM1 0 de-emphasis OFF (44.1 kHz)

1 de-emphasis ON (44.1 kHz)

1998 Jan 06 6

Philips Semiconductors Product specification

Noise shaping filter DAC TDA1386T

MICROCONTROLLER APPLICATION MODE
(APPL = LOGIC 1, APP3 = LOGIC 0)

In this mode, the device operation is controlled by a set of
flags in an 8-bit mode control register. The 8-bit mode
control register is written by a microprocessor interface
(pin APPL = 1, APP0 = Data, APP1 = Clock, APP2 = RAB
and APP3 = 0).

The correspondence between serial to parallel conversion,
mode control flags and a summary of the effect of the
control flags is given in Table 3. Figures 3 and 4 illustrate
the mode set timing.

M

ICROCONTROLLER WRITE OPERATION SEQUENCE

• APP2 is held LOW by the microcontroller.

• Microprocessor data is clocked into the internal shift

register on the LOW-to-HIGH transition at pin APP1.

• Data D(7 to 0) is latched into the appropriate control
register on the LOW-to-HIGH transition of pin APP2
(with APP1 HIGH).

• If more data is clocked into the TDA1386T before the
LOW-to-HIGH transition on pin APP2 then only the last
8 bits are used.

• If less data is clocked into the TDA1386T unpredictable
operation will result.

• If the LOW-to-HIGH transition of pin APP2 occurs with
APP1 LOW, the command will be disregarded.

Fig.3 Microcontroller timing.

1998 Jan 06 7

Philips Semiconductors Product specification

Noise shaping filter DAC TDA1386T

MICROCONTROLLER WRITE OPERATION SEQUENCE;

REPEAT MODE

The same command can be repeated several times
(e.g. for fade function) by applying APP2 pulses as shown
in Fig.4.

It should be noted that APP1 must stay HIGH between
APP2 pulses. A minimum pause of 22 µs is necessary
between any two step-up or step-down commands.

Fig.4 Microcontroller timing; repeat mode.

Table 3 Microcontroller mode control register

BIT POSITION FUNCTION DESCRIPTION ACTIVE LEVEL

D7 ATSB 12 dB attenuation (from full scale) LOW
D6 DSMB double speed LOW
D5 MUSB mute LOW
D4 DEEM de-emphasis HIGH
D3 FS full scale HIGH
D2 INCR increment HIGH
D1 DECR decrement HIGH
D0 − reserved −

1998 Jan 06 8