INTEGRATED CIRCUITS
DATA SH EET
TDA1381
DCC write amplifier (WRITE3)
Preliminary specification
File under Integrated Circuits, IC01
Philips Semiconductors
September 1994
Philips Semiconductors Preliminary specification
DCC write amplifier (WRITE3) TDA1381
FEATURES
• Single 3 V power supply
• Low standby current consumption
• 20 bidirectional current outputs (2 × nine heads)
• Single point main data and auxiliary current setting
• Reduction of power consumption between write pulses
• Soft switching of output currents
• Serial data input
• Timing is compatible with TDA1319T
• Uncommitted operational amplifier available.
GENERAL DESCRIPTION
The TDA1381 has been designed to drive an 18-channel
inductive recording head which is suitable for the DCC
(Digital Compact Cassette) system. The bidirectional
current outputs are controlled by a two-wire serial bus. The
amplitude of the write current pulses can be set by either
voltage or current control. The circuit can be switched to
standby mode to minimize supply current consumption.
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
DD
I
DD
I
DD(av)
I
stb
I
WDAT(max)
supply voltage 2.7 3.0 4.0 V
supply current note 1 − 912mA
average supply current note 2 − 26.5 − mA
total standby current − 0.1 0.3 mA
maximum write current for main data
note 3 100 −−mA
channels 0 to 7
I
WAUX(max)
I
EAUX(max)
P
d(av)
T
amb
maximum write current for auxiliary channel note 3 115 −−mA
maximum erase current for auxiliary channel note 3 153 −−mA
average power dissipation note 2 − 80 − mW
operating ambient temperature −30 − +85 °C
Notes
1. No head connected; all outputs unloaded; V
2. In the auxiliary and data write mode; writing DCC data; I
f
= 3.072 MHz. Data channels resistively loaded with 6 Ω, auxiliary channel resistively loaded with 4 Ω between
clk
DD
=3V.
= 60 mA; VDD=3V;
WDAT
pins 23 and 24, and 37 and 38.
3. Resistors connected in accordance with test circuit of Fig.7.
ORDERING INFORMATION
TYPE
NUMBER
NAME DESCRIPTION VERSION
TDA1381H TQFP48
Note
1. When using IR reflow soldering it is recommended that the Drypack instructions in the
(order number 9398 510 63011) are followed.
September 1994 2
PACKAGE
(1)
plastic thin quad flat package; 48 leads; body 7 × 7 × 1.4 mm SOT313-1
“Quality Reference Handbook”
Philips Semiconductors Preliminary specification
DCC write amplifier (WRITE3) TDA1381
BLOCK DIAGRAM
September 1994 3
Fig.1 Block diagram.
Philips Semiconductors Preliminary specification
DCC write amplifier (WRITE3) TDA1381
PINNING
SYMBOL PIN DESCRIPTION
V
DD
V
DD
AMP(pos) 3 operational amplifier non-inverting input
WCLK 4 write clock input
WDATA 5 write data input
V
SS
STANDBY 7 standby mode control input
AB 8 tape sector A or B select input
AMPO 9 operational amplifier output
AMP(neg) 10 operational amplifier inverting input
V
DD
V
DD
BJ 13 sector B write pulse output J
BI 14 sector B write pulse output I
n.c. 15 not connected
BH 16 sector B write pulse output H
BG 17 sector B write pulse output G
BF 18 sector B write pulse output F
BE 19 sector B write pulse output E
BD 20 sector B write pulse output D
BC 21 sector B write pulse output C
n.c. 22 not connected
BB 23 sector B write pulse output B
BA 24 sector B write pulse output A
V
DD
V
DD
V
SET
V
CNTR
V
SS
I
SET
V
SS
V
ref
R
BIAS
V
DD
V
DD
n.c. 36 not connected
AA 37 sector A write pulse output A
AB 38 sector A write pulse output B
n.c. 39 not connected
AC 40 sector A write pulse output C
1 supply voltage
2 supply voltage
6 ground
11 supply voltage
12 supply voltage
25 supply voltage
26 supply voltage
27 control voltage input
28 voltage-to-current conversion setting input
29 ground
30 control current input
31 ground
32 reference voltage output
33 bias current resistor
34 supply voltage
35 supply voltage
September 1994 4
Philips Semiconductors Preliminary specification
DCC write amplifier (WRITE3) TDA1381
SYMBOL PIN DESCRIPTION
AD 41 sector A write pulse output D
AE 42 sector A write pulse output E
AF 43 sector A write pulse output F
AG 44 sector A write pulse output G
AH 45 sector A write pulse output H
n.c. 46 not connected
AI 47 sector A write pulse output I
AJ 48 sector A write pulse output J
September 1994 5
Fig.2 Pin configuration.
Philips Semiconductors Preliminary specification
DCC write amplifier (WRITE3) TDA1381
FUNCTIONAL DESCRIPTION
The TDA1381 is designed to drive the elements of an
18-channel recording head, containing nine elements for
tape sector A and nine elements for sector B. A brief
functional description of each block (see Fig.1) is given
below.
Decoder
The IC is controlled by the 32-bit wide serial data word
which is clocked in at WDATA (pin 5). The clock frequency
(WCLK, pin 4) is 3.072 MHz with a clock period of 325 ns.
The write pulses are made available at the outputs
AA to AJ when tape sector A is selected (pin 8 HIGH) or at
the outputs BA to BJ when tape sector B is selected
(pin 8 LOW). The principle of connection of the recording
head to the IC is illustrated in Fig.4.
The timing sequence of the write pulses is shown in Fig.5.
The operating mode of the IC can be set by the first 3 bits
of WDATA. The signals TCH0 to TCH7 and TCHAUX
determine the direction of the write current. When TCH
HIGH, the current flows as indicated in Fig.4. When TCH
is LOW current flows in the opposite direction. The various
modes of operation are given in Table 1. The standby
mode can also be forced by setting the STANDBY input
(pin 7) HIGH.
Current control
The write current at the outputs is regulated by the current
control circuit. The principle of this circuit is shown in Fig.3.
The value of the current I
voltage V
, connected between pin 27 and VSS. In this
SET
can be set using an external
WDAT
configuration, pin 28 has to be resistively loaded to
another voltage source or V
(see Fig.7). The current
SS
control circuit regulates the voltage between pins 27 and
28 to zero. When a resistor R
is
n
pin 28 and V
as: G
SS
I
WDAT
=
-------------------- -
if
V
------------- R
SET
SET
, a current gain factor (Gif) can be defined
is connected between
set
Table 1 Modes of operation.
MODE WRITE CURRENT CONTROL BIT
MAIN DATA
CHANNELS
AUXILIARY
CHANNEL
MAIN DATA
CHANNELS
AUXILIARY
CHANNEL
(3)
PLAYBACK)
TDAPLB
CHANNEL
(DATA
(2)
TAUPLB
(AUXILIARY
CHANNEL
PLAYBACK)
Read read off off 1 1 X
Write read I
Write write I
Write erase I
WDAT
WDAT
WDAT
Read write off AW × I
Read erase off AE × I
off 0 1 X
AW × I
AE × I
WDAT
WDAT
WDAT
WDAT
000
001
100
101
(1)
(2)
n
TERAUX
(AUXILIARY
CHANNEL
ERASE)
Notes
1. Where 0 = LOW, 1 = HIGH and X = don't care.
2. When both TDAPLB and TAUPLB are HIGH, the IC is set to the standby mode.
and AE are multiplication factors (see Section “Current control”).
3. A
W
September 1994 6