Philips TDA1373H-N2, TDA1373H-N1 Datasheet

DATA SH EET

Product speciﬁcation Supersedes data of 1995 Aug 28 File under Integrated Circuits, IC01

1996 Jul 17

INTEGRATED CIRCUITS

TDA1373H

General Digital Input (GDIN)

1996 Jul 17 2

Philips Semiconductors Product speciﬁcation

General Digital Input (GDIN) TDA1373H

FEATURES

• Four operating modes: – Sample Rate Conversion (SRC) mode – AD/DA mode – SLAVE-VCO mode – SLAVE-VCXO mode

• Full digital sample rate conversion over a wide range of input sample rates

• Fast and automatic detection and locking to the input sample rate with continuous tracking

• Digital Phase-Locked Loop (PLL) with adaptive bandwidth which removes jitter on the digital audio input

• Audio outputs (soft) muted during loop acquisition

• Full linear phase processing based on all-FIR filtering

• Integrated full digital IEC 958 demodulator for digital

input signals (AES/EBU or SPDIF format) with intelligent error handling

• Extended input sample frequency range

• IEC 958 Channel Status (CS) and User Channel (UC)

outputs

• On-chip CS and/or UC demodulation and buffering (consumer and professional format)

• Dedicated subcode processing for Compact Disc (CD)

• Final output quantization to 16, 18 or 20 bits with

optional in-audio-band noise shaping

• Bitstream input and output for coupling with 1-bit analog-to-digital conversion (ADC) and digital-to-analog conversion (DAC)

• I

S and Japanese serial input formats supported for

SRC and DAC functions

• I2S and Japanese serial output formats supported for SRC and ADC functions

• I2S and Japanese 4× oversampled serial output available for SRC and ADC functions

• 8-bit digital gain/attenuation control

• Switchable Digital Signal Processor (DSP)-interface

(I2S input and output) for additional audio processing

• Additional clock outputs available at 768, 384, 256 and 128f

• 3-line serial microcontroller interface, compatible with the Philips CD I.C. protocol (HCL)

• 5 V power supply

• 0.7 µm double metal Complementary Metal Oxide

Semiconductor (CMOS)

• SRC THD + N: – −113 dB over the 0 to 20 kHz band (1 kHz, 20 bits

input and output) (see Fig.3)

– −95 dB over the 0 to 20 kHz band (1 kHz, 16 bits

input and output)

• Pass band ripple smaller than ±0.004 dB for up-sampling and down-sampling filters

• Stop band suppression: – selectable between 70 dB and 50 dB for 64×

up-sampling filters

– 80 dB for 128× down-sampling filters

• Microcontroller operated and stand-alone mode.

APPLICATIONS

• Professional audio equipment for: – mixing – recording – editing – broadcasting

• CD-Recordable (CD-R)

• Digital Speaker Systems (DSS)

• Digital Compact Cassette recorders (DCC)

• Digital Audio Tape (DAT) and MD recorders

• Digital amplifiers

• Jitter killers.

1996 Jul 17 3

Philips Semiconductors Product speciﬁcation

General Digital Input (GDIN) TDA1373H

GENERAL DESCRIPTION

The TDA1373H is a General Digital Input (GDIN) device for audio signals which is able to perform a high-quality sample rate conversion of digital audio signals (SRC mode). The device reads several serial input formats and signals in the IEC 958 digital audio format (also known as AES/EBU or SPDIF signals). For this purpose a full Audio Digital Input Circuit (ADIC) is present in the device.

An internal digital PLL results in extensive jitter removal from incoming digital audio signals without any analog loop electronics. The standard 20 bit output word length can be limited to 16 or 18 bits by means of ‘in-audio-band noise shaping’.

The GDIN digital filters can also be reused for Bitstream ADC and DAC conversion (AD/DA mode). The internal digital PLL can be reconfigured to operate the GDIN in a slave mode, where the output sample frequency of the device is locked to the incoming sample rate (SLAVE-VCO and SLAVE-VCXO modes).

The combination of an ADIC function, sample rate conversion and Bitstream ADC and DAC results in a device with a highly versatile functionality and large replacement value in consumer and professional audio sets.

QUICK REFERENCE DATA

All inputs and outputs CMOS compatible; unless otherwise speciﬁed.

ORDERING INFORMATION

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

supply voltage fso> 44.1 kHz 4.75 5 5.5 V

≤ 44.1 kHz 4.5 5 5.5 V

DD(tot)

total supply current fso= 44.1 kHz − 155 − mA

tot

total power dissipation fso= 44.1 kHz − 775 − mW

= 49 kHz;

VDD= 5.5 V

− 1030 − mW

IEC 958 input DI1S (high-sensitivity IEC input)

i(p-p)

AC input voltage (peak-to-peak value)

0.2 − V

Clock and timing

so(max)

maximum output sample frequency VDD= 4.75 V 49 55 − kHz

Temperature

amb

operating ambient temperature 0 70 °C

TYPE

NUMBER

PACKAGE

NAME DESCRIPTION VERSION

TDA1373H QFP64 Plastic quad flat package; 64 leads (lead length 1.95 mm);

body 14 × 20 × 2.7 mm; high stand-off height

SOT319-1

1996 Jul 17 4

Philips Semiconductors Product speciﬁcation

General Digital Input (GDIN) TDA1373H

BLOCK DIAGRAM

Fig.1 Block diagram.

Switches MM1 and MM0 are controlled indirectly via the mode selection. All other switches can be controlled directly by the user.

handbook, full pagewidth

MLC334 - 2

ADIC

(IEC 958

DECODER)

DATA

SLICER

4 x

UP-

SAMPLING

44 37 48 43 62

MU EM

LOCK

SA DI1D DI1O

CHANNEL

STATUS

EXTRACTION

USER

CHANNEL

EXTRACTION

PHASE

DETECTOR

LOOP

FILTER

HOLD VCO

GENERAL CONTROL

CLOCK

SHOP

CRYSTAL

OSCILLATOR

768fso384fso256fso128f

23 27 28 30 312221 19 204645473536345239 14327

CLO4CLO3CLO2CLO1CLIXTLOXTLIDA

DDA4

SSA4

LDCLCENCUSBS

DDD

DDDVDDDVDDD

DDDVDDD

MICRO-

CONTROLLER

INTERFACE/

STAND-ALONE

CONTROL

16 x UP-

SAMPLING

VARIABLE

HOLD

FIFO AND GAIN

I S OUT

I S IN

I S

OUT

I S

OUT

IN-BAND

NOISE

SHAPER

32 x

DOWN-

SAMPLING

4 x

DOWN-

SAMPLING

64f

HOLD

ATTENUATOR

BITSTREAM

DIGITAL

FILTER

DAC

OUTPUT

SSD

13 24

SSD

SSDVSSD

TDA1373H

DI2C

DI2W

DI2D

FOW

FOC

FOD

AIL

AIR

RST

TST1

TST2

stereo

FOS

DI2

DI1S

DDA1

SSA1

FSL

DO2D

DO2W

DO2C

DO1D

DO1W

DO1C

AOL1

AOR1

CLD

AOS

DNI

DSO

INS

DO2

MM0

DI2

DI1

MM1

PV C

WS PO

1996 Jul 17 5

Philips Semiconductors Product speciﬁcation

General Digital Input (GDIN) TDA1373H

PINNING

SYMBOL PIN DESCRIPTION TYPE

DI1S 1 IEC 958 digital audio input ‘S’ (200 mV peak-to-peak value) E036A V

SSA1

2 IEC 958 slicer analog ground E038A

DDA1

3 IEC 958 slicer analog supply voltage E037A AIL 4 Bitstream audio input left HPP01 AIR 5 Bitstream audio input right HPP01 DO2C 6 serial digital audio output 2; bit clock output (192f

) OPF40

DDD

7 digital supply voltage; note 1 − V

SSD

8 digital ground; note 2 − AOL1 9 Bitstream audio output left OPF40 DO2D 10 DLO = 0; serial digital audio output 2; data;

DLO = 1; Bitstream audio output left inverted (

AOL1); note 3

OPF40

DDD

11 digital supply voltage; note 1 −

SSD

12 digital ground; note 2 −

SSD

13 digital ground; note 2 −

DDD

14 digital supply voltage; note 1 − AOR1 15 Bitstream audio output right OPF40 DO2W 16 DLO = 0; serial digital audio output 2; word select output (4f

);

DLO = 1; Bitstream audio output right inverted (AOR1); note 3

OPF40

SSD

17 digital ground; note 2 − CLD 18 Bitstream DAC clock (192 or 128f

) OPF43

DDA4

19 oscillator analog supply voltage E037A V

SSA4

20 oscillator analog ground E038A XTLI 21 crystal input 768f

OSX01 XTLO 22 crystal output OSX01 CLI 23 external VCO input (SLAVE-VCO mode only) HPP01 V

SSD

24 digital ground; note 2 −

FSL 25 SA = 0 (microcontroller operated) external VCO output (slave modes

only); SA = 1 (stand-alone control) DI11 control line; note 4

HOF21

SSD

26 digital ground; note 2 −

CLO1 27 clock output 768f

OPF40 CLO2 28 clock output 384f

OPF40 V

SSD

29 digital ground; note 2 −

CLO3 30 clock output 256f

OPF40 CLO4 31 clock output 128f

; OPF40

DDD

32 digital supply voltage; note 1 −

SSD

33 digital ground; note 2 − BS 34 block sync; channel status/user channel/CD subcode OPF40 CEN 35 data enable; channel status/user channel/CD subcode OPF40 CUS 36 data bit; channel status/user channel/CD subcode OPF40 EM 37 IEC 958 source pre-emphasis ﬂag OPF20

1996 Jul 17 6

Philips Semiconductors Product speciﬁcation

General Digital Input (GDIN) TDA1373H

Notes

1. All V

DDD

pins are internally connected.

2. All V

SSD

pins are internally connected.

3. DLO is a command flag from register 4 (see Section “Command registers”).

4. SA is the stand-alone/microcontroller operated pin (pin 43). DI11, NSD, DI2, QU1, QU0 and MS0 are command flags to control the operation of the device. For more information see Section “Controlling the GDIN”.

RST 38 power-on reset input (active LOW) HPP07 V

DDD

39 digital supply voltage; note 1 −

SSD

40 digital ground; note 2 − TST2 41 test pin 2 (LOW for normal operation) HPP01 TST1 42 test pin 1 (LOW for normal operation) HPP01 SA 43 Stand-alone/microcontroller operated selection;

SA = 1 for stand-alone operation

HPP01

MU 44 mute ﬂag (active HIGH) OPF40 LD 45 SA = 0 (microcontroller operated) microcontroller interface; load

(read/write); SA = 1 (stand-alone control) NSD control line; note 4

HPP01

DA 46 SA = 0 (microcontroller operated) microcontroller interface (data);

SA = 1 (stand-alone control) DI2 control line; note 4

HOF41

CL 47 SA = 0 (microcontroller operated) microcontroller interface (clock);

SA = 1 (stand-alone control) QU1/QU0 control line; note 4

HPP01

LOCK 48 ADIC lock ﬂag (active HIGH) OPF40 DO1W 49 serial digital audio output 1; word select input/output (f

) HOF41 DO1D 50 serial digital audio output 1; data OPF43 DO1C 51 serial digital audio output 1; bit clock input/output (48f

) HOF41

DDD

52 digital supply voltage; note 1 −

SSD

53 digital ground; note 2 − FOW 54 serial digital audio feature output; word select OPF43 FOD 55 serial digital audio feature output; data OPF43 FOC 56 serial digital audio feature output; bit clock (64f

) OPF43 DI2D 57 serial digital audio input 2; data HPP01 V

SSD

58 digital ground; note 2 − DI2W 59 serial digital audio input 2; word select HOF21 DI2C 60 serial digital audio input 2; bit clock output HOF21 V

SSD

61 digital ground; note 2 − DI1D 62 SA = 0 (microcontroller operated) IEC 958 digital audio input ‘D’ (CMOS

level); SA = 1 (stand-alone control) MSO control line; note 4

HPP01

DI1O 63 IEC 958 digital audio input ‘O’ (CMOS level) HPP01 V

SSD

64 digital ground; note 2 −

SYMBOL PIN DESCRIPTION TYPE

1996 Jul 17 7

Philips Semiconductors Product speciﬁcation

General Digital Input (GDIN) TDA1373H

handbook, full pagewidth

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19

51 50 49

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

MLB955 - 2

TDA1373H

LOCK

DI1O

DI1D

CLO4

CLO3

CLO2

CLO1

CLI

XTLO

XTLI

DA LD

CEN

CUS

DDD

SSD

SSA4

SSD

DI2C

DI2W

DI2D

FOW

FOC

FOD

AIL

AIR

RST

TST1 TST2

DI1S

DDA1

DDD

DDA4

DDD

SSA1

FSL

DO2D

DO2W

DO2C

DO1D DO1W

DO1C

AOL1

AOR1

CLD

Fig.2 Pin configuration.

1996 Jul 17 8

Philips Semiconductors Product speciﬁcation

General Digital Input (GDIN) TDA1373H

FUNCTIONAL DESCRIPTION Operating modes

AMPLE RATE CONVERSION (SRC) MODE

The output sample rate is determined by a crystal and can be chosen up to 49 kHz. The range of input sample rates for a given output sample rate is given in Table 1. A pitch variation (‘Varispeed’) of ±12% around the nominal input sample rate can be tracked.

Table 1 Input sample rates

OUTPUT SAMPLE RATE

(kHz)

S INPUT (kHz)

0.3 to 1.7f

IEC 958 INPUT (kHz)

0.35 to 1.45f

48 13 to 83 16 to 68

44.1 12 to 76 15 to 62 32 9to55 12to45

Data path

(see Fig.4)

The input signal at sample frequency fsi comes in via one of the DI1 inputs (IEC 958) or via the serial input DI2X. The signal passes through the FIFO/GAIN part and is interpolated in the up-sampling filters. The actual sample rate conversion takes place in the variable hold block. The down-sampling filters decimate the sample frequency to fso and after in-band noise shaping, the output signal is present at serial output DO1. Additionally the converted signal is available at the ‘analog’ Bitstream outputs AOL, AOR and at the serial digital output DO2 (4f

handbook, full pagewidth

160

MLB956

140

120

100

THD N

(dB)

f (Hz)

Fig.3 Total harmonic distortion plus noise as a function of frequency.

Measurement done with ‘Audio Precision’. SRC mode; 48 to 44.1 kHz; 20-bit output.

1996 Jul 17 9

Philips Semiconductors Product speciﬁcation

General Digital Input (GDIN) TDA1373H

handbook, full pagewidth

MLC335

ADIC

(IEC 958

DECODER)

FIFO

&

GAIN

4 x AND 16 x

UP-SAMPLING

32 x AND 4 x

DOWN-

SAMPLING

IN-BAND

NOISE

SHAPER

BITSTREAM

DIGITAL

FILTER

HOLD

CLOCK SHOP

MICROCONTROLLER

INTERFACE

GENERAL CONTROL

DIGITAL PLL

CS AND UC

EXTRACTION

DO1C

DO1D

DO1W

DO2C

DO2D

DO2W

AOL

AOR

FOC

FOD

FOW

TST2TST1CLIXTLIXTLOLOCKEMCUSCENBSFSL

CLD

Main path.

Example of

additional path.

CLO4CLO3CLO2CLO1RSTSAMUDALDCL

DI1S

DI1O

DI1D

AIL

AIR

DI2C

DI2D

DI2W

TDA1373H

768f

BITSTREAM

DAC

e.g. TDA1547

analog output

digital output

fsoI S

digital input

fsiAES/EBU or I S

TDA1373H

AOS

INS

DO2

DSO

DI2

FOS

DI1

DNI

VARIABLE

HOLD

Fig.4 Standard data path in the SRC mode.

1996 Jul 17 10

Philips Semiconductors Product speciﬁcation

General Digital Input (GDIN) TDA1373H

SLAVE-VCO AND SLAVE-VCXO MODES In the SLAVE-VCO and SLAVE-VCXO modes, the GDIN

can pass an exact copy of the incoming samples to the output, e.g. for storage on a digital medium such as CD-R. The output sample rate tracks any input sample rate within the frequency range of the external VC(X)O (fso=fsi).

In the SLAVE-VCO mode a pitch variation of ±12.5% around the nominal sample frequency can be tolerated.

Data path

(see Fig.5)

The signal at input sample frequency fsi comes in via one of the DI1 inputs (IEC 958).

The ADIC signal passes through the FIFO/GAIN block and can be fed through the IN-BAND NOISE SHAPER to the serial output DO1. Additionally, the signal is present at DO2 (4fso) and at the Bitstream outputs AOL and AOR.

Exact copies for digital use (e.g. write to a disk) from the input signal can be retrieved at output FO (this signal might be affected by jitter since it has not passed through the FIFO/GAIN block). By means of data path switch DSO, this direct output of the ADIC block can also be fed to output DO1. Note that in this event the DO1 serial format becomes equal to the FO format (see Table 3).

AD/DA

MODE

In this mode, the GDIN supports an economic realization of analog-to-digital and digital-to-analog conversion, in accordance with the Bitstream principle. This requires a Bitstream sigma-delta modulator and a Bitstream DAC, since the up-sampling and down-sampling filters of the sample rate convertor are reused. ADC and DAC can be simultaneously performed.

Data path DA conversion

(see Fig.6)

The signal at sample frequency fso comes in via serial input DI2X or via one of the DI1 inputs (IEC 958). The signal passes through the FIFO/GAIN part and is interpolated in the up-sampling filters. A Bitstream digital filter converts this signal into a Bitstream signal at outputs AOL and AOR, after which it can be filtered by a Bitstream DAC like the TDA1547.

Data path AD conversion

(see Fig.6)

The Bitstream signal from the sigma-delta modulator enters the GDIN at inputs AIL and AIR. The down-sampling filters decimate this signal to fso and after in-band noise shaping (selectable), the output signal is present at serial output DO1.

1996 Jul 17 11

Philips Semiconductors Product speciﬁcation

General Digital Input (GDIN) TDA1373H

handbook, full pagewidth

MLC336

ADIC

(IEC 958

DECODER)

FIFO

&

GAIN

4 x AND 16 x

UP-SAMPLING

32 x AND 4 x

DOWN-

SAMPLING

IN-BAND

NOISE

SHAPER

BITSTREAM

DIGITAL

FILTER

HOLD

CLOCK SHOP

MICROCONTROLLER

INTERFACE

GENERAL CONTROL

DIGITAL PLL

CS AND UC

EXTRACTION

VARIABLE

HOLD

DO1C

DO1D

DO1W

DO2C

DO2D

DO2W

AOL

AOR

FOC

FOD

FOW

TST2TST1CLIXTLIXTLOLOCKEMCUSCENBSFSL

CLD

Main path.

Example of

additional path.

CLO4CLO3CLO2CLO1RSTSAMUDALDCL

AIL

AIR

DI2C

DI2D

DI2W

TDA1373H

BITSTREAM

DAC e.g.TDA1547

analog output

digital output

fsiI S

digital input

fsiAES/EBU or I S

VCO

768f

TDA1373H

BITSTREAM

DAC e.g.TDA1547

analog output

digital output

fsiI S

digital input

fsiAES/EBU or I S

AOS

DO2

DSO

DNI

DI2

FOS

DI1S

DI1O

DI1D

DI1

INS

Fig.5 Standard data path in the SLAVE-VCO and SLAVE-VCXO modes.

1996 Jul 17 12

Philips Semiconductors Product speciﬁcation

General Digital Input (GDIN) TDA1373H

handbook, full pagewidth

MLC337

ADIC

(IEC 958

DECODER)

FIFO

&

GAIN

4 x AND 16 x

UP-SAMPLING

32 x AND 4 x

DOWN-

SAMPLING

IN-BAND

NOISE

SHAPER

BITSTREAM

DIGITAL

FILTER

HOLD

CLOCK SHOP

MICROCONTROLLER

INTERFACE

GENERAL CONTROL

DIGITAL PLL

CS AND UC

EXTRACTION

VARIABLE

HOLD

DO1C

DO1D

DO1W

DO2C

DO2D

DO2W

AOL

AOR

FOC

FOD

FOW

TST2TST1CLIXTLIXTLOLOCKEMCUSCENBSFSL

CLD

Main path.

Example of

additional path.

CLO4CLO3CLO2CLO1RSTSAMUDALDCL

AIL

AIR

DI2C

DI2D

DI2W

TDA1373H

768f

BITSTREAM

DAC

e.g. TDA1547

analog output

digital output

fsoI S

digital input

fsoAES/EBU or I S

TDA1373H

AD IN

DA IN

AD OUT

DA OUT

AOS

DO2

DSO

INS

DNI

DI2

FOS

analog input

BITSTREAM

ADC

e.g. SAA7360

DI1S

DI1O

DI1D

DI1

Fig.6 Standard data paths in the AD/DA mode.

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