www.freeservicemanuals.info
INTEGRATED CIRCUITS
TDA1373H
General Digital Input (GDIN)
Product specification |
1996 Jul 17 |
Supersedes data of 1995 Aug 28
File under Integrated Circuits, IC01
www.freeservicemanuals.info
Philips Semiconductors |
Product specification |
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General Digital Input (GDIN) |
TDA1373H |
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FEATURES
∙Four operating modes:
–Sample Rate Conversion (SRC) mode
–AD/DA mode
–SLAVE-VCO mode
–SLAVE-VCXO mode
∙Full digital sample rate conversion over a wide range of input sample rates
∙Fast and automatic detection and locking to the input sample rate with continuous tracking
∙Digital Phase-Locked Loop (PLL) with adaptive bandwidth which removes jitter on the digital audio input
∙Audio outputs (soft) muted during loop acquisition
∙Full linear phase processing based on all-FIR filtering
∙Integrated full digital IEC 958 demodulator for digital input signals (AES/EBU or SPDIF format) with intelligent error handling
∙Extended input sample frequency range
∙IEC 958 Channel Status (CS) and User Channel (UC) outputs
∙On-chip CS and/or UC demodulation and buffering (consumer and professional format)
∙Dedicated subcode processing for Compact Disc (CD)
∙Final output quantization to 16, 18 or 20 bits with optional in-audio-band noise shaping
∙Bitstream input and output for coupling with 1-bit analog-to-digital conversion (ADC) and digital-to-analog conversion (DAC)
∙I2S and Japanese serial input formats supported for SRC and DAC functions
∙I2S and Japanese serial output formats supported for SRC and ADC functions
∙I2S and Japanese 4× oversampled serial output available for SRC and ADC functions
∙8-bit digital gain/attenuation control
∙Switchable Digital Signal Processor (DSP)-interface (I2S input and output) for additional audio processing
∙Additional clock outputs available at 768, 384, 256 and 128fso
∙3-line serial microcontroller interface, compatible with the Philips CD I.C. protocol (HCL)
∙5 V power supply
∙0.7 μm double metal Complementary Metal Oxide Semiconductor (CMOS)
∙SRC THD + N:
–−113 dB over the 0 to 20 kHz band (1 kHz, 20 bits input and output) (see Fig.3)
–−95 dB over the 0 to 20 kHz band (1 kHz, 16 bits input and output)
∙Pass band ripple smaller than ±0.004 dB for up-sampling and down-sampling filters
∙Stop band suppression:
–selectable between 70 dB and 50 dB for 64× up-sampling filters
–80 dB for 128× down-sampling filters
∙Microcontroller operated and stand-alone mode.
APPLICATIONS
∙Professional audio equipment for:
–mixing
–recording
–editing
–broadcasting
∙CD-Recordable (CD-R)
∙Digital Speaker Systems (DSS)
∙Digital Compact Cassette recorders (DCC)
∙Digital Audio Tape (DAT) and MD recorders
∙Digital amplifiers
∙Jitter killers.
1996 Jul 17 |
2 |
www.freeservicemanuals.info
Philips Semiconductors |
Product specification |
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General Digital Input (GDIN) |
TDA1373H |
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GENERAL DESCRIPTION
The TDA1373H is a General Digital Input (GDIN) device for audio signals which is able to perform a high-quality sample rate conversion of digital audio signals (SRC mode). The device reads several serial input formats and signals in the IEC 958 digital audio format (also known as AES/EBU or SPDIF signals). For this purpose a full Audio Digital Input Circuit (ADIC) is present in the device.
An internal digital PLL results in extensive jitter removal from incoming digital audio signals without any analog loop electronics. The standard 20 bit output word length can be limited to 16 or 18 bits by means of ‘in-audio-band noise shaping’.
QUICK REFERENCE DATA
The GDIN digital filters can also be reused for Bitstream ADC and DAC conversion (AD/DA mode). The internal digital PLL can be reconfigured to operate the GDIN in a slave mode, where the output sample frequency of the device is locked to the incoming sample rate (SLAVE-VCO and SLAVE-VCXO modes).
The combination of an ADIC function, sample rate conversion and Bitstream ADC and DAC results in a device with a highly versatile functionality and large replacement value in consumer and professional audio sets.
All inputs and outputs CMOS compatible; unless otherwise specified.
SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
TYP. |
MAX. |
UNIT |
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Supply |
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VDD |
supply voltage |
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fso > 44.1 kHz |
4.75 |
5 |
5.5 |
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fso ≤ 44.1 kHz |
4.5 |
5 |
5.5 |
V |
IDD(tot) |
total supply current |
fso = 44.1 kHz |
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155 |
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Ptot |
total power dissipation |
fso = 44.1 kHz |
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775 |
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mW |
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fso = 49 kHz; |
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1030 |
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IEC 958 input DI1S (high-sensitivity IEC input) |
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Vi(p-p) |
AC input voltage |
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Clock and timing |
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fso(max) |
maximum output sample frequency |
VDD = 4.75 V |
49 |
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kHz |
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Temperature |
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Tamb |
operating ambient temperature |
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ORDERING INFORMATION |
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PACKAGE |
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DESCRIPTION |
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TDA1373H |
QFP64 |
Plastic quad flat package; 64 leads (lead length 1.95 mm); |
SOT319-1 |
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body 14 × 20 × 2.7 mm; high stand-off height |
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1996 Jul 17 |
3 |
www.freeservicemanuals.info
Philips Semiconductors |
Product specification |
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General Digital Input (GDIN) |
TDA1373H |
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BLOCK DIAGRAM |
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VDDD VDDD VDDD |
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VSSA4 |
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VDDA4 |
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VDDD VDDD VDDD |
BS CUS |
CEN |
CL LD DA XTLI |
XTLO CLI CLO1 CLO2 CLO3 CLO4 |
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32 |
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MICRO- |
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MU |
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USER |
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CRYSTAL |
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U |
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INTERFACE/ |
OSCILLATOR |
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EXTRACTION |
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EM |
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CONTROL |
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CLOCK |
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LOCK |
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PV |
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ADIC |
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SHOP |
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MM1 |
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SA |
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(IEC 958 |
C |
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CHANNEL |
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DECODER) |
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WS |
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STATUS |
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DI1D |
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GENERAL |
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PO |
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EXTRACTION |
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64fso |
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63 |
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CONTROL |
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DI1O |
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DI1 |
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DI1S |
1 |
DATA |
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SLICER |
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DI2 |
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VDDA1 |
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PHASE |
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LOOP |
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HOLD |
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VCO |
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2 |
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DETECTOR |
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FILTER |
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FSL |
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VSSA1 |
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MM0 |
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FIFO |
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4 x |
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VARIABLE |
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AND |
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UP- |
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HOLD |
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GAIN |
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SAMPLING |
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SAMPLING |
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DO2 |
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DO2D |
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OUT |
DO2W |
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DO2C |
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50 |
TST1 |
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DSO |
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DO1D |
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I2 S |
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INS |
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DO1C |
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RST |
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DNI |
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32 x |
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NOISE |
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4 |
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SHAPER |
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5 |
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SAMPLING |
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SAMPLING |
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AIR |
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stereo |
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FOS |
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DI2 |
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AOS |
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BITSTREAM |
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AOL1 |
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ATTENUATOR |
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DAC |
15 |
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DIGITAL |
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AOR1 |
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OUTPUT |
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FILTER |
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18 |
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CLD |
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HOLD |
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TDA1373H |
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I2S OUT |
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I 2S IN |
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55 |
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8 |
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MLC334 - 2 |
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FOD FOC FOW DI2D DI2W DI2C |
VSSD |
VSSD |
VSSD |
VSSD |
VSSD |
VSSD |
VSSD |
VSSD |
VSSD |
VSSD |
VSSD |
VSSD |
VSSD |
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Switches MM1 and MM0 are controlled indirectly via the mode selection. All other switches can be controlled directly by the user.
Fig.1 Block diagram.
1996 Jul 17 |
4 |
www.freeservicemanuals.info
Philips Semiconductors |
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Product specification |
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General Digital Input (GDIN) |
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TDA1373H |
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PINNING |
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SYMBOL |
PIN |
DESCRIPTION |
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TYPE |
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DI1S |
1 |
IEC 958 digital audio input ‘S’ (200 mV peak-to-peak value) |
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E036A |
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VSSA1 |
2 |
IEC 958 slicer analog ground |
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E038A |
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VDDA1 |
3 |
IEC 958 slicer analog supply voltage |
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E037A |
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AIL |
4 |
Bitstream audio input left |
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HPP01 |
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AIR |
5 |
Bitstream audio input right |
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HPP01 |
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DO2C |
6 |
serial digital audio output 2; bit clock output (192fso) |
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OPF40 |
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VDDD |
7 |
digital supply voltage; note 1 |
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− |
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VSSD |
8 |
digital ground; note 2 |
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− |
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AOL1 |
9 |
Bitstream audio output left |
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OPF40 |
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DO2D |
10 |
DLO = 0; serial digital audio output 2; data; |
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OPF40 |
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DLO = 1; Bitstream audio output left inverted |
(AOL1); |
note 3 |
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VDDD |
11 |
digital supply voltage; note 1 |
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− |
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VSSD |
12 |
digital ground; note 2 |
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− |
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VSSD |
13 |
digital ground; note 2 |
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− |
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VDDD |
14 |
digital supply voltage; note 1 |
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− |
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AOR1 |
15 |
Bitstream audio output right |
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OPF40 |
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DO2W |
16 |
DLO = 0; serial digital audio output 2; word select output (4fso); |
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OPF40 |
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DLO = 1; Bitstream audio output right inverted |
(AOR1); |
note 3 |
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VSSD |
17 |
digital ground; note 2 |
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− |
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CLD |
18 |
Bitstream DAC clock (192 or 128fso) |
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OPF43 |
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VDDA4 |
19 |
oscillator analog supply voltage |
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E037A |
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VSSA4 |
20 |
oscillator analog ground |
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E038A |
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XTLI |
21 |
crystal input 768fso |
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OSX01 |
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XTLO |
22 |
crystal output |
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OSX01 |
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CLI |
23 |
external VCO input (SLAVE-VCO mode only) |
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HPP01 |
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VSSD |
24 |
digital ground; note 2 |
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− |
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FSL |
25 |
SA = 0 (microcontroller operated) external VCO output (slave modes |
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HOF21 |
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only); SA = 1 (stand-alone control) DI11 control line; note 4 |
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VSSD |
26 |
digital ground; note 2 |
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− |
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CLO1 |
27 |
clock output 768fso |
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OPF40 |
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CLO2 |
28 |
clock output 384fso |
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OPF40 |
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VSSD |
29 |
digital ground; note 2 |
|
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− |
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CLO3 |
30 |
clock output 256fso |
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OPF40 |
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CLO4 |
31 |
clock output 128fso; |
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OPF40 |
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VDDD |
32 |
digital supply voltage; note 1 |
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− |
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VSSD |
33 |
digital ground; note 2 |
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− |
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BS |
34 |
block sync; channel status/user channel/CD subcode |
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OPF40 |
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CEN |
35 |
data enable; channel status/user channel/CD subcode |
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OPF40 |
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CUS |
36 |
data bit; channel status/user channel/CD subcode |
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OPF40 |
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EM |
37 |
IEC 958 source pre-emphasis flag |
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OPF20 |
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1996 Jul 17 |
5 |
www.freeservicemanuals.info
Philips Semiconductors |
|
Product specification |
||||
|
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|
|
General Digital Input (GDIN) |
TDA1373H |
||||
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SYMBOL |
PIN |
DESCRIPTION |
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TYPE |
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38 |
power-on reset input (active LOW) |
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HPP07 |
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RST |
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VDDD |
39 |
digital supply voltage; note 1 |
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− |
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VSSD |
40 |
digital ground; note 2 |
|
− |
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TST2 |
41 |
test pin 2 (LOW for normal operation) |
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HPP01 |
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TST1 |
42 |
test pin 1 (LOW for normal operation) |
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HPP01 |
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SA |
43 |
Stand-alone/microcontroller operated selection; |
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HPP01 |
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SA = 1 for stand-alone operation |
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MU |
44 |
mute flag (active HIGH) |
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OPF40 |
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LD |
45 |
SA = 0 (microcontroller operated) microcontroller interface; load |
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HPP01 |
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(read/write); SA = 1 (stand-alone control) NSD control line; note 4 |
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DA |
46 |
SA = 0 (microcontroller operated) microcontroller interface (data); |
|
HOF41 |
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SA = 1 (stand-alone control) DI2 control line; note 4 |
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CL |
47 |
SA = 0 (microcontroller operated) microcontroller interface (clock); |
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HPP01 |
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SA = 1 (stand-alone control) QU1/QU0 control line; note 4 |
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LOCK |
48 |
ADIC lock flag (active HIGH) |
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OPF40 |
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DO1W |
49 |
serial digital audio output 1; word select input/output (fso) |
|
HOF41 |
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DO1D |
50 |
serial digital audio output 1; data |
|
OPF43 |
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DO1C |
51 |
serial digital audio output 1; bit clock input/output (48fso) |
|
HOF41 |
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VDDD |
52 |
digital supply voltage; note 1 |
|
− |
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VSSD |
53 |
digital ground; note 2 |
|
− |
||
FOW |
54 |
serial digital audio feature output; word select |
|
OPF43 |
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FOD |
55 |
serial digital audio feature output; data |
|
OPF43 |
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FOC |
56 |
serial digital audio feature output; bit clock (64fso) |
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OPF43 |
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DI2D |
57 |
serial digital audio input 2; data |
|
HPP01 |
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VSSD |
58 |
digital ground; note 2 |
|
− |
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DI2W |
59 |
serial digital audio input 2; word select |
|
HOF21 |
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DI2C |
60 |
serial digital audio input 2; bit clock output |
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HOF21 |
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VSSD |
61 |
digital ground; note 2 |
|
− |
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DI1D |
62 |
SA = 0 (microcontroller operated) IEC 958 digital audio input ‘D’ (CMOS |
HPP01 |
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level); SA = 1 (stand-alone control) MSO control line; note 4 |
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DI1O |
63 |
IEC 958 digital audio input ‘O’ (CMOS level) |
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HPP01 |
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VSSD |
64 |
digital ground; note 2 |
|
− |
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Notes
1.All VDDD pins are internally connected.
2.All VSSD pins are internally connected.
3.DLO is a command flag from register 4 (see Section “Command registers”).
4.SA is the stand-alone/microcontroller operated pin (pin 43). DI11, NSD, DI2, QU1, QU0 and MS0 are command flags to control the operation of the device. For more information see Section “Controlling the GDIN”.
1996 Jul 17 |
6 |
www.freeservicemanuals.info
Philips Semiconductors |
Product specification |
|
|
General Digital Input (GDIN) |
TDA1373H |
|
|
DI1S 1
VSSA1 2 VDDA1 3 AIL 4 AIR 5 DO2C 6 VDDD 7 VSSD 8
AOL1 9
DO2D 10 VDDD 11
VSSD 12
VSSD 13 VDDD 14 AOR1 15 DO2W 16 VSSD 17
CLD 18 VDDA4 19
SSD |
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DI1O |
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DI1D |
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SSD |
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DI2C |
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DI2W |
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SSD |
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DI2D |
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FOC |
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FOD |
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FOW |
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SSD |
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DDD |
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V |
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V |
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V |
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V |
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V |
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64 |
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63 |
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62 |
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61 |
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60 |
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59 |
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58 |
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57 |
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56 |
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55 |
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54 |
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53 |
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52 |
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TDA1373H
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20 |
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21 |
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22 |
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23 |
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24 |
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25 |
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26 |
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27 |
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28 |
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29 |
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30 |
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31 |
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32 |
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SSA4 |
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XTLI |
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XTLO |
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CLI |
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SSD |
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FSL |
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SSD |
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CLO1 |
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CLO2 |
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SSD |
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CLO3 |
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CLO4 |
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DDD |
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V |
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V |
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V |
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V |
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V |
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51 |
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DO1C |
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50 |
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DO1D |
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49 |
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DO1W |
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48 |
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LOCK |
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47 |
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CL |
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46 |
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DA |
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45 |
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LD |
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44 |
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MU |
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43 |
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SA |
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42 |
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TST1 |
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41 |
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TST2 |
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40 |
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VSSD |
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39 |
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VDDD |
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38 |
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RST |
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37 |
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EM |
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36 |
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CUS |
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35 |
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CEN |
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34 |
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BS |
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33 |
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VSSD |
||
|
||||
MLB955 - 2
Fig.2 Pin configuration.
1996 Jul 17 |
7 |
www.freeservicemanuals.info
Philips Semiconductors |
Product specification |
|
|
General Digital Input (GDIN) |
TDA1373H |
|
|
FUNCTIONAL DESCRIPTION
Operating modes
SAMPLE RATE CONVERSION (SRC) MODE
The output sample rate is determined by a crystal and can be chosen up to 49 kHz. The range of input sample rates for a given output sample rate is given in Table 1. A pitch variation (‘Varispeed’) of ±12% around the nominal input sample rate can be tracked.
Table 1 Input sample rates
Data path (see Fig.4)
The input signal at sample frequency fsi comes in via one of the DI1 inputs (IEC 958) or via the serial input DI2X. The signal passes through the FIFO/GAIN part and is interpolated in the up-sampling filters. The actual sample rate conversion takes place in the variable hold block. The down-sampling filters decimate the sample frequency to fso and after in-band noise shaping, the output signal is present at serial output DO1. Additionally the converted signal is available at the ‘analog’ Bitstream outputs AOL, AOR and at the serial digital output DO2 (4fso).
OUTPUT SAMPLE RATE |
I2S INPUT (kHz) |
IEC 958 INPUT (kHz) |
(kHz) |
0.3 to 1.7fso |
0.35 to 1.45fso |
48 |
13 to 83 |
16 to 68 |
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44.1 |
12 to 76 |
15 to 62 |
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32 |
9 to 55 |
12 to 45 |
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MLB956
60 handbook, full pagewidth
THD 
N (dB)
80 |
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100 |
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120 |
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140 |
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160 |
10 2 |
10 3 |
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4 |
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10 5 |
10 |
10 |
(Hz) |
||||
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f |
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Measurement done with ‘Audio Precision’.
SRC mode; 48 to 44.1 kHz; 20-bit output.
Fig.3 Total harmonic distortion plus noise as a function of frequency.
1996 Jul 17 |
8 |
1996 |
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Jul |
digital input |
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digital output |
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17 |
fsi |
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fso |
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AES/EBU or I2S |
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TDA1373H |
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I2S |
|||||
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BITSTREAM |
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analog output |
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DAC |
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e.g. TDA1547 |
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768fso |
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FSL |
BS |
CEN |
CUS |
EM |
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LOCK |
XTLO |
XTLI |
CLI |
TST1 |
TST2 |
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DO1C |
DI1S |
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FOS |
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INS |
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DSO |
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DI1 |
ADIC |
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DNI |
32 x AND 4 x |
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|||
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FIFO |
4 x AND 16 x |
VARIABLE |
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IN-BAND |
DO1D |
||||||
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DI2 |
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||||||||
DI1O |
(IEC 958 |
|
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& |
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DOWN- |
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NOISE |
||||||
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UP-SAMPLING |
HOLD |
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||||||||
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DECODER) |
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GAIN |
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SAMPLING |
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SHAPER |
DO1W |
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DI1D |
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DO2C |
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TDA1373H |
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DO2D |
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DO2 |
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AIL |
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Main path. |
pagewidthfullhandbook, |
Example of |
|
additional path. |
||
|
Fig.4 Standard data path in the SRC mode.
(GDIN) Input Digital General
TDA1373H
Semiconductors Philips |
freeservicemanuals.www |
|
info. |
specification Product
www.freeservicemanuals.info
Philips Semiconductors |
Product specification |
|
|
General Digital Input (GDIN) |
TDA1373H |
|
|
SLAVE-VCO AND SLAVE-VCXO MODES |
AD/DA MODE |
In the SLAVE-VCO and SLAVE-VCXO modes, the GDIN can pass an exact copy of the incoming samples to the output, e.g. for storage on a digital medium such as CD-R. The output sample rate tracks any input sample rate within the frequency range of the external VC(X)O (fso = fsi).
In the SLAVE-VCO mode a pitch variation of ±12.5% around the nominal sample frequency can be tolerated.
Data path (see Fig.5)
The signal at input sample frequency fsi comes in via one of the DI1 inputs (IEC 958).
The ADIC signal passes through the FIFO/GAIN block and can be fed through the IN-BAND NOISE SHAPER to the serial output DO1. Additionally, the signal is present at DO2 (4fso) and at the Bitstream outputs AOL and AOR.
Exact copies for digital use (e.g. write to a disk) from the input signal can be retrieved at output FO (this signal might be affected by jitter since it has not passed through the FIFO/GAIN block). By means of data path switch DSO, this direct output of the ADIC block can also be fed to
output DO1. Note that in this event the DO1 serial format becomes equal to the FO format (see Table 3).
In this mode, the GDIN supports an economic realization of analog-to-digital and digital-to-analog conversion, in accordance with the Bitstream principle. This requires a Bitstream sigma-delta modulator and a Bitstream DAC, since the up-sampling and down-sampling filters of the sample rate convertor are reused. ADC and DAC can be simultaneously performed.
Data path DA conversion (see Fig.6)
The signal at sample frequency fso comes in via serial input DI2X or via one of the DI1 inputs (IEC 958). The signal passes through the FIFO/GAIN part and is interpolated in the up-sampling filters. A Bitstream digital filter converts this signal into a Bitstream signal at outputs AOL and AOR, after which it can be filtered by a Bitstream DAC like the TDA1547.
Data path AD conversion (see Fig.6)
The Bitstream signal from the sigma-delta modulator enters the GDIN at inputs AIL and AIR. The down-sampling filters decimate this signal to fso and after in-band noise shaping (selectable), the output signal is present at serial output DO1.
1996 Jul 17 |
10 |
17 Jul 1996
11
digital input fsi
AES/EBU or I2S 
digital input fsi
AES/EBU or I2S 
digital output fsi
TDA1373H |
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I2S |
BITSTREAM |
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analog output |
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DAC e.g.TDA1547 |
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VCO |
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digital output |
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fsi |
TDA1373H |
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I2S |
BITSTREAM |
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analog output |
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DAC e.g.TDA1547 |
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768fso
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FSL |
BS |
CEN |
CUS |
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EM |
LOCK |
XTLO |
XTLI |
CLI |
TST1 |
TST2 |
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DO1C |
DI1S |
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INS |
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DSO |
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DECODER) |
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AIL |
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CL |
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pagewidth |
SA |
RST |
CLO1 CLO2 CLO3 CLO4 |
CLD |
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Main path. |
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Example of |
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handbook, full |
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additional path. |
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Fig.5 Standard data path in the SLAVE-VCO and SLAVE-VCXO modes. |
|
|
|
|||||
(GDIN) Input Digital General
TDA1373H
Semiconductors Philips |
freeservicemanuals.www |
|
info. |
specification Product
17 Jul 1996
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digital output |
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fso |
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BITSTREAM |
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analog input |
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ADC |
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TDA1373H |
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I2S |
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e.g. SAA7360 |
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digital input |
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BITSTREAM |
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analog output |
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DAC |
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fso |
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AES/EBU or I2S |
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FSL |
BS |
CEN |
CUS |
EM |
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XTLI |
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TST1 |
TST2 |
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DI1S |
DI1 |
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INS |
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AD OUT |
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VARIABLE |
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DI1O |
(IEC 958 |
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& |
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NOISE |
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UP-SAMPLING |
HOLD |
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DECODER) |
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GAIN |
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SHAPER |
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DO2D |
AIL |
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DO2 |
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DI2C |
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DIGITAL PLL |
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FOC |
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DI2D |
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DI2W |
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GENERAL CONTROL |
EXTRACTION |
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MLC337 |
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CL |
LD |
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DA |
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MU |
SA |
RST |
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CLO1 |
CLO2 |
CLO3 |
CLO4 |
CLD |
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Main path. |
Example of additional path.
handbook, full pagewidth
Fig.6 Standard data paths in the AD/DA mode.
(GDIN) Input Digital General
TDA1373H
Semiconductors Philips |
freeservicemanuals.www |
|
info. |
specification Product
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