Philips TDA1306T-N1, TDA1306T-N2 Datasheet

INTEGRATED CIRCUITS

DATA SHEET

TDA1306T

Noise shaping filter DAC

Product specification

1998 Jan 06

Supersedes data of September 1994

File under Integrated Circuits, IC01

Philips Semiconductors	Product specification
Noise shaping filter DAC	TDA1306T

FEATURES

General

∙Double-speed mode

∙Digital volume control

∙Soft mute function

∙12 dB attenuation

∙Low power dissipation

∙Digital de-emphasis

∙TDA1305T pin compatible.

Easy application

∙Voltage output

∙Only 1st-order analog post-filtering required

∙Operational amplifiers and digital filter integrated

∙Selectable system clock (fsys) 256fs or 384fs

∙I2S-bus (fsys = 256fs) or 16, 18 or 20 bits LSB fixed serial input format (fsys = 384fs)

∙Single rail supply.

High performance

∙Superior signal-to-noise ratio

∙Wide dynamic range

∙No zero crossing distortion

∙Inherently monotonic

∙Continuous calibration digital-to-analog conversion combined with noise shaping technique.

ORDERING INFORMATION

GENERAL DESCRIPTION

The TDA1306T is a dual CMOS digital-to-analog converter with up-sampling filter and noise shaper.

The combination of oversampling up to 4fs, noise shaping and continuous calibration conversion ensures that only simple 1st-order analog post-filtering is required.

The TDA1306T supports the I2S-bus data input mode

(fsys = 256fs) with word lengths of up to 20 bits and the LSB fixed serial data input format (fsys = 384fs) with word

lengths of 16, 18 or 20 bits. Two cascaded IIR filters increase the sampling rate 4 times.

The DACs are of the continuous calibration type and incorporate a special data coding. This ensures a high signal-to-noise ratio, wide dynamic range and immunity to process variation and component ageing.

Two on-board operational amplifiers convert the digital-to-analog current to an output voltage.

	TYPE NUMBER		PACKAGE
		NAME	DESCRIPTION	VERSION
	TDA1306T	SO24	plastic small outline package; 24 leads; body width 7.5 mm.	SOT137−1

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Philips Semiconductors					Product specification
Noise shaping filter DAC					TDA1306T
QUICK REFERENCE DATA
All power supply pins VDD and VSS must be connected to the same external supply unit.
SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
Supply
VDDD	digital supply voltage		4.5	5.0	5.5	V
VDDA	analog supply voltage		4.5	5.0	5.5	V
VDDO	operational amplifier		4.5	5.0	5.5	V
	supply voltage
IDDD	digital supply current	VDDD = 5 V;	−	5	8	mA
		at code 00000H
IDDA	analog supply current	VDDA = 5 V;	−	3	5	mA
		at code 00000H
IDDO	operational amplifier	VDDO = 5 V;	−	2	4	mA
	supply current	at code 00000H
Analog signals
VFS(rms)	full-scale output voltage	VDDD = VDDA = VDDO = 5 V;	0.935	1.1	1.265	V
	(RMS value)	RL > 5 kΩ
RL	output load resistance		5	−	−	kΩ
DAC performance
(THD + N)/S	total harmonic distortion	at 0 dB signal level;	−	−70	−	dB
	plus noise-to-signal ratio	fi = 1 kHz;
			−	0.032	−	%
		at −60 dB signal level;	−	−42	−32	dB
		fi = 1 kHz;
			−	0.8	2.5	%
S/N	signal-to-noise ratio	no signal; A-weighted	−	−108	−96	dB
BR	input bit rate at data input	fs = 44.1 kHz;	−	−	2.822	Mbits/s
		normal speed
		fs = 44.1 kHz;	−	−	5.645	Mbits/s
		double speed
fsys	system clock frequency		6.4	−	18.432	MHz
	(pin 12)
Tamb	operating ambient		−40	−	+85	°C
	temperature

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Philips Semiconductors	Product specification
Noise shaping filter DAC	TDA1306T

BLOCK DIAGRAM

Fig.1	Block diagram.
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Philips Semiconductors	Product specification

	Noise shaping filter DAC				TDA1306T
	PINNING
	SYMBOL	PIN	DESCRIPTION
	VDDA	1	analog supply voltage (+5 V)
	VSSA	2	analog ground
	TEST1	3	test input 1; pin should be connected
			to ground
	BCK	4	bit clock input
	WS	5	word select input
	DATA	6	data input
	CLKS1	7	clock and format selection 1 input
	CLKS2	8	clock and format selection 2 input
	VSSD	9	digital ground
	VDDD	10	digital supply voltage (+5 V)
	TEST2	11	test input 2; pin should be connected
			to ground
	SYSCLK	12	system clock input 256fs or 384fs
	APP3	13	application mode 3 input
	APPL	14	application mode selection input
	APP2	15	application mode 2 input
	APP1	16	application mode 1 input
	APP0	17	application mode 0 input
	VOL	18	left channel output
	FILTCL	19	capacitor for left channel 1st order
			filter function; should be connected
			between pins 19 and 18
	FILTCR	20	capacitor for right channel 1st order
			filter function; should be connected
			between pins 20 and 21
	VOR	21	right channel output
	Vref	22	internal reference voltage for output
			channels; 0.5VDDO (typ.)
	VSSO	23	operational amplifier ground	Fig.2	Pin configuration.
	VDDO	24	operational amplifier supply voltage

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Philips Semiconductors	Product specification
Noise shaping filter DAC	TDA1306T

FUNCTIONAL DESCRIPTION

The TDA1306T CMOS DAC incorporates an up-sampling filter, a noise shaper, continuous calibrated current sources and operational amplifiers.

System clock and data input format

The TDA1306T accommodates slave mode only. Consequently, in all applications, the system devices must provide the system clock. The system frequency is selectable at pins CLKS1 and CLKS2 (see Table 1).

The TDA1306T supports the following data input modes:

∙I2S-bus with data word length of up to 20 bits (fsys = 256fs)

∙LSB fixed serial format with data word length of 16, 18

or 20 bits (fsys = 384fs). As this format idles on the MSB it is necessary to know how many bits are being transmitted.

The input formats are illustrated in Fig.9. Left and right data channel words are time multiplexed.

Table 1 Data input format and system clock

	CLKS1	CLKS2	DATA INPUT FORMAT	SYSTEM CLOCK
				NORMAL SPEED	DOUBLE SPEED
	0	0	I2S-bus	256fs	128fs
	0	1	LSB fixed 16 bits	384fs	192fs
	1	0	LSB fixed 18 bits	384fs	192fs
	1	1	LSB fixed 20 bits	384fs	192fs

Device operation

When the APPL pin is held HIGH and APP3 is held LOW, pins APP0, APP1 and APP2 form a microcontroller interface. When the APPL pin is held LOW, pins APP0, APP1, APP2 and APP3 form a pseudo-static application (TDA1305T pin compatible).

PSEUDO-STATIC APPLICATION MODE (APPL = LOGIC 0)

In this mode, the device operation is controlled by pseudo-static application pins where:

APP0 = attenuation mode control

APP1 = double-speed mode control

APP2 = mute mode control

APP3 = de-emphasis mode control.

In the pseudo-static application mode the TDA1306T is pin compatible with the TDA1305T slave mode.

The correspondence between TDA1306T pin number, TDA1306T pin name, TDA1305T pin mnemonic and a description of the effects is given in Table 2.

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Philips Semiconductors					Product specification
Noise shaping filter DAC					TDA1306T
Table 2 Pseudo-static application mode
PIN	PIN NUMBER		TDA1305T	VALUE	DESCRIPTION
MNEMONIC			FUNCTION
APP0	17		ATSB	0	12 dB attenuation (from full scale) activated
					(only if MUSB = logic 1)
				1	full scale (only if MUSB = logic 1)
APP1	16		DSMB	0	double-speed mode
				1	normal-speed mode
APP2	15		MUSB	0	samples decrease to mute level
				1	level according to ATSB
APP3	13		DEEM1	0	de-emphasis OFF (44.1 kHz)
				1	de-emphasis ON (44.1 kHz)

MICROCONTROLLER APPLICATION MODE (APPL = LOGIC

1 AND APP3 = LOGIC 0)

In this mode, the device operation is controlled by a set of flags in an 8-bit mode control register. The 8-bit mode control register is written by a microcontroller interface where:

APPL = logic 1

APP0 = Data

APP1 = Clock

APP2 = RAB

APP3 = logic 0.

The correspondence between serial-to-parallel conversion, mode control flags and a summary of the effect of the control flags is given in Table 3.

Figures 3 and 4 illustrate the mode set timing.

MICROCONTROLLER WRITE OPERATION SEQUENCE

The microcontroller write operation follows the following sequence:

∙APP2 is held LOW by the microcontroller

∙Microcontroller data is clocked into the internal shift register on the LOW-to-HIGH transition on pin APP1

∙Data D7 to D0 is latched into the appropriate control register on the LOW-to-HIGH transition of pin APP2 (APP1 = HIGH)

∙If more data is clocked into the TDA1306T before the LOW-to-HIGH transition on pin APP2 then only the last 8 bits are used

∙If less data is clocked into the TDA1306T unpredictable operation will result

∙If the LOW-to-HIGH transition of pin APP2 occurs when APP1 = LOW, the command will be disregarded.

Fig.3 Microcontroller timing.

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Philips Semiconductors	Product specification
Noise shaping filter DAC	TDA1306T

MICROCONTROLLER WRITE OPERATION SEQUENCE (REPEAT

MODE)

The same command can be repeated several times (e.g. for fade function) by applying APP2 pulses as shown in Fig.4. It should be noted that APP1 must stay HIGH

between APP2 pulses. A minimum pause of 22 μs is necessary between any two step-up or step-down commands.

Fig.4 Microcontroller timing (repeat mode).

Table 3 Microcontroller mode control register

BIT POSITION	FUNCTION	DESCRIPTION	ACTIVE LEVEL
D7	ATSB	12 dB attenuation	LOW
		(from full scale)
D6	DSMB	double speed	LOW
D5	MUSB	mute	LOW
D4	DEEM	de-emphasis	HIGH
D3	FS	full scale	HIGH
D2	INCR	increment	HIGH
D1	DECR	decrement	HIGH
D0	not applicable	reserved	not applicable

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