TECHNICAL NOTE
VERTICAL DEFLECTION CIRCUITS FOR TV & MONITOR
By Alessandro MESSI
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INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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RAMP GENERATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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BLANKING GENERATOR AND CRT PROTECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . |
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POWER AMPLIFIER STAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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THERMAL PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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FLYBACK BEHAVIOUR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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CURRENT - VOLTAGE CHARACTERISTICS OF THE RECIRCULATING DIODES . . |
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CALCULATION PROCEDURE OF THE FLYBACK DURATION . . . . . . . . . . . . . . . . . . |
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APPLICATION INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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SUPPLY VOLTAGE CALCULATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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CALCULATION OF MIDPOINT AND GAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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MONITOR APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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POWER DISSIPATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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BLANKING PULSE DURATION ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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LINEARITY ADJUSTMENT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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FACILITIES AND IMPROVEMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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GENERAL APPLICATION AND LAYOUT HINTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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VERTICAL DEFLECTION CIRCUITS FOR TV & MONITOR
1 - INTRODUCTION
In a general way we can define vertical stages circuits able to deliver a current ramp suitable to drive the vertical deflection yoke.
In Figure 1 is represented the more general possible block diagram of a device performing the vertical deflection.
Such a device will be called ºcomplete vertical stageº because it can be simply driven by a synchronization pulse and it comprises all the circuitry necessary to perform the vertical deflection that is : oscillator, voltage ramp generator, blanking gene-
tor, output power and flyback generator.
At the right side of the dotted line in Figure 1 is represented the circuitry characterizing a ºvertical output stageº. This kind of device comprises only
the power stages and it has to be driven by a voltage sawtooth generated by a previous circuit (for example a horizontal and vertical synchronization stage.
In the first class there are the following devices : TDA1170D, TDA1170N, TDA1170S, TDA1175, TDA1670A, TDA1675, TDA1770A, TDA1872A, TDA8176.
In thesecond class there are : TDA2170, TDA2270, TDA81 70, TDA8172, TDA8173, TDA8175, TDA8178, TDA8179.
There is also a thrid class of vertical stages compraising the voltage ramp generator but without the oscillator; these circuits must be driven by an already synchronized pulse. In this third class there are : TDA1771 and TDA8174.
Figure 1 : Block Diagram of a General Deflection Stage
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2 - OSCILLATOR
There are two different kinds of oscillator stages used in SGS-THOMSON complete vertical deflections, one is used in TDA1170D, TDA1170N, TDA1170S, TDA1175 and TDA8176, the other in TDA1670A, TDA1675, TDA1170Aand TDA1872A.
The principle of the first kind of oscillator is represented in Figure 2.
The following explanations will be the more general possible; we shall inform the reader when we refer to a particular device.
When the switches T1 and T2 are opened the CO capacitor charges exponentially through RO to the value V+(MAX) determined by the integrated resistors R1, R2, R3 and R4. At this point the switches are closed, short-circuiting R3 and R4, so the voltage at thenon-inverting input becomes V+(MIN). The capacitor CO discharges to this value through the
Figure 2 : First Kind of Oscillator Stage
integrated resistor R5.
The free running frequency can be easily calculated resulting in :
TO = RO CO log VR − V+(MIN) |
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VR − V+(MAX) |
fO = |
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(1) |
TO |
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+ R5 CO log |
V (MAX) |
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V (MIN) |
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with RO = 360 kΩ and CO = 100 nF, it results in 43.7Hz.
The oscillator synchronization is obtained reducing the superior threshold V+(MAX) short-circuiting the R4 resistor when a vertical synchronization pulse occurs.
The second kind of oscillator is represented in Figure 3.
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Figure 3 : Second Kind of Oscillator Stage
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VERTICAL DEFLECTION CIRCUITS FOR TV & MONITOR
When the switch T is in position 2, a constant current ICO = V - / RO flows through CO charging it with a voltage ramp. When the voltage VO reaches
VO(MAX), T passes in position 1, so a constant current ICO = ( VB - V - ) / RO discharges the capaci-
tor causing the inversion of the voltage ramp slope at the output VO ( t ). The discharges stops when VO reaches the value VO(MIN) and the cycle takes place again.
It is possible to calculate the free runningfrequency fO with the following formula :
( VO(MAX) − VO(MIN) ) RO CO
TO = V−
(2)
(VO(MAX) − VO(MIN) ) RO CO
+VB − V−
with VO(MAX) - VO(MIN) = 3.9V, VB = 6.5V, V- = 0.445V, RO = 7.5kΩ and CO = 330nF it results in : fO = 43.8Hz.
The oscillator synchronization is still obtained in the above mentioned way.
In order to guarantee a minimum pull-in range of 14Hz the threshold value has been chosen in VP = 4.3V.
The spread of the free running frequency in this kind of oscillator is very low because it mainly depends from the thresholdvalues VO(MAX), VO(MIN) and V - that are determined by resistor rates that can be done very precise.
3 - RAMP GENERATOR
The ramp generatoris conceptually represented in Figure 4.
The Voltage ramp is obtained charging the group R1, C1 and C2 with a constant current IX.
It is easy to calculate the voltage VRAMP Thatresults in :
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(3) |
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R1 C + R1 IX |
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VRAMP (t) = (V(MIN) − R1 IX) e |
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where V(MIN) is the voltage in A when the charge starts and C is the series of C1 and C2.
The resistorR1 is necessaryto give a ºC correctionº to the voltage ramp. The ramp amplitude is determined by IX = VREG / P1 ,so the potentiometer P1 is
necessary to perform the height control.
The voltage ramp is then transferred on a low impedence in B through a buffer stage.
The P2 potentiometer connected between D and B performs the ramp linearity control or ºS correctionº that is necessary to have a correct reproduction of the images on the TV set.
The voltage ramp in B grows up until the switch T1 is closed by a clock pulse coming from the oscillator; in this way the capacitors discharge fastly to V(MIN) that is dependent upon the saturation voltage of the transistor that realizes the switch.
At this point the exponential charge takes place again.
4 - BLANKING GENERATOR AND CRT PROTECTION
This circuit senses the presence of the clock pulse coming from the oscillator stage and the flyback pulse on the yoke. If both of them are present a blanking pulse is generated able to blank the CRT during the retrace period. The duration of this pulse is the same of the one coming from the oscillator.
If for any reason the vertical deflection would fail, for instance for a short circuit or an open circuit of the yoke, the absence of the flyback pulse puts the circuit in such a condition that a continuous vertical blanking is generated in order to protect the CRT against eventual damages.
This circuit is available only in the following devices :TDA1670A, TDA1675, TDA1770A and TDA1872A.
The stages we will consider starting from this point are common both to complete vertical stages and vertical output stages.
5 - POWER AMPLIFIER STAGE
This stage can be divided into two distinct parts : the amplifier circuit and the output power.
The amplifier is realized with a differential circuit; a schematic diagram is represented in Figure 5.
The open-loop gain of the circuit is variable from 60dB to 90dB for the different integrated circuits.
The compensation capacitor C determines the dominant pole of the amplifier. In order to obtain a dominant pole in the range of 400Hz, the capacitor must be of about 10pF.
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VERTICAL DEFLECTION CIRCUITS FOR TV & MONITOR
Figure 4 : Ramp Generator
Figure 5 : Amplifier Stage
As an example in Figure 6 is represented the boole |
Figure 7 : Power Stage |
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diagram of the amplifier open loop gain for |
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TDA8172. |
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Figure 6 : Amplifier Open Loop Gain and Phase |
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(dB)GAIN |
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FREQUENCY, f (Hz) |
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The output power stage is designed in order to deliver to the yoke a vertical deflection current from 1 to 2 Apeak, dependingupon the different devices, and able to support flyback voltages up to 60V. A typical output stage is depicted in Figure 7.
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VERTICAL DEFLECTION CIRCUITS FOR TV & MONITOR
The upper power transistor Q1 conductsduring the first part of the scanning period when the vertical deflection current is flowing from the supply voltage into the yoke; when the current becomes negative, that is it comes out of the yoke, it flows through the lower power transistor Q2.The circuit connected between the two output transistors is necessary to avoid distortion of the current at the crossing of zero, when Q1 is turned off and Q2 is turned on.
When the flyback begins, Q2 is switched-off by Q3 in order to make it able to support the high voltage of the flyback pulse.
The circuit behaviour during flyback is explained in chapter 7.
6 - THERMAL PROTECTION
The thermalprotectionis available in all the devices except the TDA1170 family and the TDA8176.
This circuit is usefull to avoid damages at the integrated circuit due to a too high junction temperature caused by an incorrect working condition.
It is possible to sense the silicon temperature because the transistor VBE varies of - 2 mV/ oC, so a
Figure 8 : Output Power and Flyback Stages
temperature variation can be reconducted to a voltage variation.
If the temperature increases and it is reaching 150oC, the integrated circuit output is shut down by putting off the current sources of the power stage.
7 - FLYBACK BEHAVIOUR
In order to obtain sufficiently short flyback times, a voltage greather than the scanning voltage must be applied to the deflection yoke.
By using a flyback generator, the yoke is only supplied with a voltage close to double the supply during flyback.
Thus, the power dissipated is reduced to approximately one third and the flyback time is halfed.
The flyback circuit is shown in Figure 8 together with the power stage.
Figure 9 shows the circuit behaviuor, to show operation clearly. The graphs are not drawn to scale. Certain approximations are made in the analysis in order to eliminate electrical parameters that do not significantly influence circuit operations.
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VERTICAL DEFLECTION CIRCUITS FOR TV & MONITOR
Figure 9 : Current in the Yoke and Voltage Drop on The Yoke during Vertical Deflection
a) Scan period (t6 - t7) : Figure 10
During scanning Q3, Q4 and Q5 are off and this causes Q6 to saturate.
A current from the voltage supply to ground flows through DB, CB and Q6 charging the CB capacitor up to :
VCB = VS - VDB - VQ6SAT |
(4) |
At the end of this period the scan current has reached its peak value (IP) and it is flowing from the yoke to the device. At the same time VA has reached its minimum value.
In Figures 11 and 12 are depicted the voltage drop
Figure 11 : Voltage Drop on the Yoke and Current Flowing through DB
V = 10V/div. - I = 0.5A/div. t = 2ms/div.
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on the yoke and the currents flowing through DB and the yoke.
Figure 10 : Circuit involved during Scan Period
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Figure 12 : Voltage Drop on the Yoke and Current Flowing through the Yoke
V = 10V/div. - I = 1A/div. t = 5ms/div.
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VERTICAL DEFLECTION CIRCUITS FOR TV & MONITOR
b) Flyback starting (t0 - t1) : Figure 13 |
Figure 14 : Voltage Drop on the Yoke and Cur- |
Q8, that was conducting the - IP current, is turned |
rent Flowing through the Boucherot |
off by the buffer stage. |
Cell - V = 10V/div. |
The yoke, charged to IP, now forces this current to |
I = 1A/div. - t = 1μs/div. |
flow partially through the Boucherot cell (I1) and |
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In Figures 14, 15 and 16 are represented the |
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cell and D1. |
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Figure 13 : Circuit involved during Flyback Starting |
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c) Flyback starting (t1 - t2)
When the voltage drop at pin A rises over VS, Q3 turns on and this causes Q4 and Q5 to saturate. Consequently Q6 turns off.
During this period the voltage at pin D is forced to :
VD = VS - VQ4SAT |
(5) |
Therefore the voltage at pin B becomes :
VB = VCB + VD |
(6) |
The yoke current flows in the Boucherot cell added to another current peak flowing from VS via Q4 and CB (Figures 14 and 15).
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Figure 15 : Voltage Drop on the Yoke and Current Flowing through D1
V = 10V/div. - I = 1A/div. t = 1μs/div.
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