Philips SSTL16857 Datasheet

INTEGRATED CIRCUITS

SSTL16857

14-bit SSTL_2 registered driver with differential clock inputs

Product specification Supersedes data of 1999 Apr 29

 

1999 Sep 30

Philips Semiconductors Product specification

14-bit SSTL_2 registered driver with differential clock inputs

FEA TURES

•Stub-series terminated logic for 2.5V VDDQ (SSTL_2)

•Optimized for DDR (Double Data Rate) SDRAM applications

•Supports SSTL_2 signal inputs and outputs

•Flow-through architecture optimizes PCB layout

•Meets SSTL_2 class I and class II specifications

•Latch-up protection exceeds 500mA per JEDEC Std 17

•ESD protection exceeds 2000 V per MIL STD 833 Method 3015

and 200 V per Machine Model

•Full DDR solution provided when used with PCK857 and CBT3857

DESCRIPTION

The SSTL16857 is a 14-bit SSTL_2 registered driver with differential clock inputs. Both V however. V V

REF

DDQ

normally at 0.5*V be used for standard stub-series applications or capacitive loads. Master reset (RESET

The SSTL16857 is intended to be incorporated into standard DIMM (Dual In-Line Memory Module) designs defined by JEDEC, such as DDR (Double Data Rate) SDRAM or SDRAM II Memory Modules. Different from traditional SDRAM, DDR SDRAM transfers data on both clock edges (rising and falling), thus doubling the peak bus bandwidth. A DDR DRAM rated at 100 MHz will have a burst rate of 200 MHz. The modules require between 23 and 27 registered control and address lines, so two 14-bit wide devices will be used on each module. The SSTL16857 is intended to be used for SSTL_2 input and output signals.

The device data inputs consist of differential receivers. One differential input is tied to the input pin while the other is tied to a reference input pad, which is shared by all inputs.

The clock input is fully differential to be compatible with DRAM devices that are installed on the DIMM. However, since the control inputs to the SDRAM change at only half the data rate, the device must only change state on the positive transition of the CLK signal. In order to be able to provide defined outputs from the device even before a stable clock has been supplied, the device must support an asynchronous input pin (reset), which when held to the LOW state will assume that all registers are reset to the LOW state and all outputs drive a LOW signal as well.

and V

must not exceed VCC. Inputs are SSTL_2 type with

DDQ

support 2.5V and 3.3V operation

DDQ

. The outputs support class I which can

) asynchronously resets all registers to zero.

PIN CONFIGURATION

GND

VDDQ

4 5

Q4 Q5

7 8

GND

VDDQ

10 11

VDDQ

GND

Q8 Q9

15 16

VDDQ

GND

Q10

18 19

Q11

Q12

VDDQ

GND

Q13

23 24

Q14

SSTL16857

GND

VCC

CLK–

CLK+

VCC

GND

VREF

RESET

D10

D11

D12

VCC

GND

D13

D14

SW00311

QUICK REFERENCE DA TA

GND = 0 V; T

SYMBOL

NOTES:

1. C

is used to determine the dynamic power dissipation (PD in µW) PD = CPD V

= input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V;

ȍ (C

= 25°C; tr =tf v2.5 ns

amb

PHL/tPLH

fo) = sum of the outputs.

PARAMETER CONDITIONS TYPICAL UNIT

Propagation delay; CLK to Qn CL = 30 pF; V

= 2.5 V 1.8 ns

DDQ

Input capacitance VCC = 2.5V 2.9 pF

x fi )ȍ (CL V

fo) where:

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE ORDER CODE DWG NUMBER

48-Pin Plastic TSSOP Type I 0°C to +70°C SSTL16857 DGG SOT362-1

1999 Sep 30 853-2155 22448

Philips Semiconductors Product specification

SYMBOL

PARAMETER

CONDITION

UNIT

14-bit SSTL_2 registered driver with differential clock inputs

PIN DESCRIPTION

PIN NUMBER SYMBOL NAME AND FUNCTION

LVCMOS asynchronous master

34 RESET

48, 47, 44, 43, 42, 41, 40, 33, 32, 31, 30, 29,

D1 – D14 SSTL_2 data inputs

26, 25

1, 2, 5, 6, 7, 10,

11, 14, 15, 18,

Q1 – Q14 SSTL_2 data outputs

19, 20, 23, 24

35 VREF SSTL_2 input reference level

3, 8, 13, 17, 22,

27, 36, 46

GND Ground (0 V)

28, 37, 45 V

4, 9, 12, 16, 21 V

38 39

DDQ

CLK+

CLK–

FUNCTION TABLE

INPUTS

RESET CLK CLK D

L X X X L H ↓ ↑ H H H ↓ ↑ L L H L or H L or H X Q

H = High voltage level L = High voltage level

↓ = High-to-Low transition ↑ = Low-to-High transition

X = Don’t care

reset (Active LOW)

Positive supply voltage

Output supply voltage Differential clock inputs

OUTPUT

SSTL16857

LOGIC DIAGRAM

RESET

VREF

D10

D11

D12

D13

D14

Q10

Q11

Q12

Q13

Q14

CLK+

ABSOLUTE MAXIMUM RA TINGS

CLK–

1, 2

SW00312

LIMITS

MIN MAX

I V

OK OUT

OUT

STG

DC supply voltage –0.5 +4.6 V

DC input diode current VI < 0 –50 mA

DC input voltage

–0.5 V

+ 0.5 V

DDQ

DC output diode current VO < 0 –50 mA

DC output voltage

DC output current VO = 0 to V

Continuous current

Note 3 –0.5 V

DDQ

VCC, V

, or GND ±100

DDQ

+ 0.5 V

DDQ

±50

Storage temperature range –65 +150 °C

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

, V

4. The continuous current at V

1999 Sep 30

, or GND should not exceed ±100 mA.

DDQ

+ 5 hidden pages