Philips SAA7240 Datasheet

INTEGRATED CIRCUITS

DATA SH EET

SAA7240

MPEG-2 Transport RISC processor

Product speciﬁcation File under Integrated Circuits, IC02

2001 Oct 22

Philips Semiconductors Product speciﬁcation

MPEG-2 Transport RISC processor SAA7240

CONTENTS

1 FEATURES

1.1 General

1.2 External interfaces

1.3 CPU-related features

1.4 MPEG-2 System Processor (MSP) features

1.5 Compatibility with other devices 2 GENERAL DESCRIPTION

2.1 Limitation notes

2.2 IntegratedConditionalAccessModule(ICAM®) licensing requirements

3 ORDERING INFORMATION 4 BLOCK DIAGRAMS 5 PINNING INFORMATION

5.1 Pinning

5.2 Pin description

5.3 Pin list in numerical order

6 LIMITING VALUES 7 HANDLING 8 THERMAL CHARACTERISTICS 9 DC CHARACTERISTICS

9.1 Power saving in Sleep and Coma modes

9.2 Maximum allowable load capacitance on output pins

10 APPLICATION INFORMATION

10.1 Application examples of the multi-master mode

10.2 Memory configurations

11 PACKAGE OUTLINE 12 SOLDERING

12.1 Introduction to soldering surface mount packages

12.2 Reflow soldering

12.3 Wave soldering

12.4 Manual soldering

12.5 Suitability of surface mount IC packages for wave and reflow soldering methods

13 DATA SHEET STATUS 14 DEFINITIONS 15 DISCLAIMERS 16 PURCHASE OF PHILIPS I2C COMPONENTS

2001 Oct 22 2

Philips Semiconductors Product speciﬁcation

MPEG-2 Transport RISC processor SAA7240

1 FEATURES

1.1 General

• Conditional access descrambling Digital Video

Broadcasting (DVB) compliant, MULTI2 compliant and

 (1)

ICAM

• Targeted to BSkyB 3.00 and Canal+basic box 3.02 and

web box 1.01 applications

• Stream demultiplexing: Transport Stream (TS),

Packetized Elementary Stream(PES), Program Stream (PS) and Proprietary data streams

• Internal 32-bit MIPS RISC-based CPU, supporting

MIPS16 instruction set and running at 81 MHz

• Low-power Sleep modes supported across the chip

• Support for external co-processor

• 0.25 µm technology

• Power supply of 2.5 V for the core and 3.3 V for the

peripherals, to be TTL level compatible

• Comprehensive driver software and development tool

support

• Package: SQFP208.

1.2 External interfaces

The SAA7240 supports the following external interfaces:

• Versatile transport streaminput/output at 13.5 Mbytes/s

configurable in parallel or serial mode. Interfaces to IEEE 1394 devices (such as Philips PDI 1394 chip-set) in full-duplex mode and to external descramblers through a Common Interface (CI) device. The following interfaces are supported:

– 3 parallel TS input/output ports – 2 parallel TS input/output ports and 3 serial TS ports – 1 parallel TS input/output port and 5 serial TS ports – 6 serial TS input/output ports.

• A microcontroller extension bus, supporting:

– 16-bit and 32-bit data buses – Up to 64 Mbytes addressing range – Synchronous Dynamic RAM (SDRAM) interface – Dynamic RAM interface – Read Only Memory (ROM) interface – Flash memory interface – Interface to various peripherals

compliant

– Synchronous interface to communicate with the

integrated MPEG Audio Video Graphics Decoder

(AVGD) SAA7215 at 40.5 MHz – Large endian and small endian byte addressing – A multi-master mode (master and slave modes).

• 2-channel Direct Memory Access (DMA) for fast block move to/from any memory location

• Up to 12 chipselects available, some can be configured as general purpose ports

• An IEEE 1284 interface (Centronics) with DMA engine supporting master and slave modes. Usable as a general purpose port

• TwoUART (RS232) dataports with DMAcapabilities (at

187.5 kbit/s), including hardware flow control signals RXD, TXD, RTS and CTS for modem support

• A Synchronous Serial Interface (SSI) to connect an off-chip modem analog front-end

• An elementary UART with DMA capabilities, dedicated to front panel devices for instance

• Two dedicated smart card reader interfaces (ISO 7816 compatible) with DMA capabilities. One interface is intended for the conditional access and is shared with the Integrated ConditionalAccess Module (ICAM) when ICAM is enabled; the second interface may be used for pay-per-view

• Two I2C-bus master/slave transceivers with DMA capabilities, supporting the standard (100 kbit/s) and fast (400 kbit/s) I2C-bus modes

• 32-bit general purpose port

• Eight interrupt inputs

• Parallel audio video interface to the MPEG AVGD

decoder SAA7215

• One Pulse Width Modulated (PWM) output with 8-bit resolution

• An Extended JTAG (EJTAG) interface for board test support.

(1) Integrated Conditional Access Module (ICAM



) is an intellectual property of News Data System Corporation.

2001 Oct 22 3

Philips Semiconductors Product speciﬁcation

MPEG-2 Transport RISC processor SAA7240

1.3 CPU-related features

The SAA7240 contains an embedded RISC CPU, which incorporates the following features:

• A 32-bit PR3930 core, running at 81 MHz

• Support for large and small byte addressing modes; is

ready for Windows

 (1)

CE and pSOS

 (2)

operating

systems

• 8-kbyte 2-way set of associative instruction cache

• 4-kbyte 4-way set of associative data cache

• A programmable low-power mode, including wake-up

on interrupt

• A Memory Management Unit (MMU) with 32 odd/even entries and variable page sizes

• Multiply/accumulate/divide unit with fast multiply/accumulate for 16-bit and 32-bit operands

• Twofully independent 24-bit timers andone24-bit timer, including watchdog facilities

• A real-time clock unit (active in Sleep mode)

• Built-in software debug support unit as part of extended

JTAG debug interface

• On-chip SRAM of 4 kbytes for storing code that needs fast execution.

1.4 MPEG-2 System Processor (MSP) features

• A flexible re-router to support many combinations of the transport stream input/output interfaces:

– Connection to serial or parallel Common Interface IC – Connection to serial or parallel 1394 IC in full-duplex

mode – Static dual front-end handling of channel decoders – A maximum frequency of up to 13.5 Mbytes/s in

parallel mode and up to 81 Mbits/s in serial mode.

• A demultiplexer scheme, which is fully compliant with Canal+ and BSkyB specifications:

– Hardware-based parsing of transport, program and

proprietary software data streams. The maximum input rate is 13.5 Mbytes/s in parallel mode and 81 Mbits/s in serial mode

– Up to 40, 13-bit Packet Identifier (PID) filters applied

on the PID value. 32 PID filters can be dedicated to filter packets containing sections; four PID filters to filter transport packets header; four PID filters to parse audio, video, teletext and subtitle data

(1) Windows is a registered trademark of Microsoft Corporation (2) pSOS is a registered trademark of Wind River Systems, Inc.

– 4 TS/PES packet header filters (filter condition of

3 bytes, including PID value for TS packet header and specific filter condition for PES packet header)

– 32 section filters based on a flexible number of filter

conditions to retrieve PSI, SI, Private data and EPG, etc. Each section filter supports 48 filters conditions of 12 bytes; each filter condition can be negated or masked on a bit level

– 7 ECM/EMM filters stored in on-chip RAM for ICAM

implementation (ECM/EMM packets are stored in on-chip RAM)

– Flexible 40 channel DMA-based storage of the

32 section sub-streams and four TS/PES data sub-streams and 4 TS/PES packet headers in external memory

– System time base management with a double

counter mechanism for clock control and discontinuity handling

– Two Presentation TimeStamp (PTS)/Decoding Time

Stamp (DTS) timers

– A General Purpose/High Speed (GP/HS)filter, which

can serve as an alternative input from IEEE 1394 devices, for example. The IEEE 1394 GP/HS mode supports packet insertion and has an internal SRAM for storing two packets. It can also output either scrambled or descrambled TS to IEEE 1394 devices.

• A real time descrambler, supporting different descrambler algorithms and consisting of four modules:

– A control word bank, containing 14 pairs (odd or

even) of control words and a default control word

– The DVB descrambler core, implementing the stream

decipher and block decipher algorithms

– The MULTI2 descrambler algorithm, implementing

the CBC and OFB mode descrambling functions. In this mode, the maximum frequency is 9 Mbytes/s (72 Mbits/s)

– The Integrated Conditional Access Module (ICAM),

including an ISO 7816 compliant UART to interface the conditional access smart card.

1.5 Compatibility with other devices

The SAA7240 seamlessly interfaces to the integrated MPEG AVGD decoder SAA7215HS. It is also backward compatible with the other devices of the family. The following modes/combinations are supported:

• SAA7240 with SAA7215HS seamless

• Pinning compatibility with the SAA7219HS.

2001 Oct 22 4

Philips Semiconductors Product speciﬁcation

MPEG-2 Transport RISC processor SAA7240

2 GENERAL DESCRIPTION

The SAA7240 is a transport MPEG-2 source decoder designed for application in set-top boxes in aDigital Video Broadcast (DVB)environment.Itistargeted to BSkyB 3.00 and Canal+ basic box and web box applications. The device is part of a comprehensive source decoding kit that contains all the hardware and software required to receive and decode MPEG-2 transport streams, including descrambling and demultiplexing.

In addition, it includes a PR3930 core, which is a 32-bit MIPS RISC-based CPU core supporting the MIPS16 instruction set (to reduce memory requirements) and several peripheral interfaces such as UARTs, I2C-bus units, an IEC 1883, and an IEEE 1284 (Centronics) interface.The SAA7240 is thereforecapableof performing all controller tasks in digital television applications. Furthermore, the SAA7240 complies with DVB, ICAM and MULTI2 descrambler standards.

The SAA7240 receives transport streams through a versatile stream input interface capable of handling both byte-parallel and bit-serial streams, in various formats, supportingdatastreams up to and including13.5 Mbytes/s in parallel mode and 81 Mbits/s in serial mode. The data stream is first applied to an on-chip descrambler with a DVB descrambling algorithm, on the basis of 14 control word pairs stored in an on-chip RAM.

Demultiplexingis subsequently applied tothedata stream, to separate up to 40 individual data streams. The demultiplexer section includes clock recovery and timebase management. Program Specific Information (PSI), Service Information (SI), Conditional Access (CA) messages and private data are selected and stored in external memory, for subsequent off-line processing by the internal PR3930 CPU core.

To support advanced board testing facilities,the SAA7240 includes Boundary Scan Test (BST) hardware, according to the JTAG standard. The device features flexible

low-power Sleep modes, which independently control the activity of each functional block and can sustain set-top box standby functionality, thus eliminating the need for a separate front-panel controller.

The SAA7240 requires a supply voltage of 3.3 V for the I/O pads and a supply voltage of 2.5 V for the core.

2.1 Limitation notes

Althoughthemostadvanced techniques and sophisticated tools are used during the design and validation phases, some design limitations giving some restrictions for specific applications might be discovered during the characterization of the SAA7240 and during its life time. If such an eventuality occurs, a limitation note will be issued, describing the deviation against the specification and the advised work-around if any. This limitation note, alsosometimescalled ‘anomaly sheet’ or ‘buglist’,isgiven to customers when they are in the initial design-in phase. Once the design-in is in production phase, customers are informed about any new limitation if the severity is estimated to be high.

Please contact your nearest Philips Semiconductor sales office for more information.

2.2 Integrated Conditional Access Module (ICAM

licensing requirements

Companies planning to use ICAMimplementation in any final product must obtain a license from News Data System Corporation before designing such products. Additionalper-chip royalties mayberequired and aretobe paid by the purchaser to News Data System Corporation. For information on the Integrated Conditional Access Module features, a non-disclosure agreement must be signed with Philips Semiconductors to get the ICAM specification.

Please contact your nearest Philips Semiconductor sales office for more information.



)

3 ORDERING INFORMATION

PACKAGE

TYPE NUMBER

NAME DESCRIPTION VERSION

SAA7240 SQFP208 plasticshrink quad ﬂat package, 208 leads (lead length 1.3 mm);

body 28 × 28 × 34 mm; high stand-off height

2001 Oct 22 5

SOT316-1

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2001 Oct 22 6

ll pagewidth

4 BLOCK DIAGRAMS

Philips Semiconductors Product speciﬁcation

MPEG-2 Transport RISC processor SAA7240

CPU section

MIPS

PR3930

CORE

DATA CACHE

INSTRUCTION CACHE

TIMER 1

TIMER 2

TIMER 3 (WATCHDOG)

DSU

EJTAG

SAA7240

PI-BUS

CTRL

EXTENSION BUS

CONTROLLER AND

GPDATA PKTDATA GPD

INPUT/OUTPUT ROUTER

MMU

PI-bus

SMM

CARD READER

DMA

UART

01 0 10

SSI

PWM

DEMUX AND

DESCRAMBLERS

BUFFER POOL CONTROLLER

PIO

INTERFACE

I2C-bus

IEEE 1284

MSP section

AUDIO AND

VIDEO

INTERFACE

SS S

RTC

32 kHz

INTERRUPT

CONTROLLER

(1)

AV PES interface

RESETN

CLK

4-KBYTE

SRAM

JTAG

EJTAG

interface

M = master peripheral with embedded DMA channel S = slave peripheral

(1) The MSP section is shown in more detail in Fig.2.

extension

bus

smart card

interface

UART

interface

SSI interface

PIO

interface

Fig.1 Block diagram.

I2C-bus

interface

IEEE 1284

interface

Peripheral section

FCE811

Philips Semiconductors Product speciﬁcation

MPEG-2 Transport RISC processor SAA7240

handbook, full pagewidth

smart

card

interface

INTERRUPT

HANDLER

BIST

CONTROLLERS

DVB

DESCRAMBLER

CA/UART MODULE

ECM/EMM

FILTER

RAM

TO / FROM SERIAL OR PARALLEL PORTS PKTDATA

INPUT / OUTPUT ROUTER

INPUT

INTERFACE

PID

FILTER

MULTI2

DESCRAMBLER

SECTION

FILTER

GP/HS

MPEG bus

TS-PES

PACKET

FILTER

GPD PWMGPDATA

PCR/SCR

TS-PES

HEADER

FILTER

4432

PWM

INTERFACE

CONTROL &

STATUS

REGISTERS

AV PES interface

BUFFER POOL CONTROLLER

WITH 40 DMA CHANNELS

PI-bus

Fig.2 MSP block diagram.

2001 Oct 22 7

INTERFACE

FCE824

Philips Semiconductors Product speciﬁcation

MPEG-2 Transport RISC processor SAA7240

5 PINNING INFORMATION

5.1 Pinning

handbook, halfpage

208

SAA7240HS

Fig.3 Pin configuration.

157

104

156

105

FCE812

2001 Oct 22 8

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2001 Oct 22 9

5.2 Pin description Table 1 Interface signal descriptions

Philips Semiconductors Product speciﬁcation

MPEG-2 Transport RISC processor SAA7240

SYMBOL PIN TYPE DESCRIPTION BUFFER TYPE

Programmable input/output port

PIO[0:7]/INT[0:7] 105 to 112 I/O I/O lines or interrupt inputs bidirectional; CMOS input; 2 mA

output drive

PIO8 113 I/O I/O line bidirectional; CMOS input; 2 mA

output drive

PIO9 114 I/O I/O line bidirectional; CMOS input; 2 mA

output drive

PIO10/BPN 116 I/O I/O line or bus pre-empt; this requires the bus owner to

release the bus after the current transfer

PIO11/VPP 117 I/O I/O line or VPP; control signal for the supply voltage

(ICAM)

PIO12/C8 118 I/O I/O line or IO data for conditional access (ICAM) bidirectional; CMOS input;

PIO13/C4 119 I/O I/O line or IO data for conditional access (ICAM) bidirectional; 8 mA output drive;

PIO14/BRN 120 I/O I/O line or bus request input bidirectional; CMOS input; 2 mA

PIO15/BGN 121 I/O I/O line or bus grant output bidirectional; CMOS input; 2 mA

PIO[16:31]/D[16:31] 20 to 11,

9 to 4, 2

Extension bus interface

D[0:15] 41 to 28,

25 to 21 A[0:21] 63 to 90 O address bus 3-state output; 2 mA output drive LOW A[22:25]

RAS0N 49 O row access strobe for DRAM and SDRAM bank 0 3-state output; 2 mA output drive HIGH RAS1N/DCS1N 48 O row access strobe for DRAM and SDRAM bank 1 or

LCASN/LBA#/SIZE0 46 O column access strobe lower byte 3-state output; 2 mA output drive HIGH

(1)

I/O I/O lines or upper data bus in 32-bit conﬁguration bidirectional; CMOS input;

I/O lower 16-bit data bus bidirectional; CMOS input;

n.a. address bus extension shared with the IEEE 1284

interface

SDRAM chip select bank 1

bidirectional; CMOS input; 2 mA output drive

8 mA output drive; open-drain;

open-drain

output drive

3-state output; 2 mA output drive

n.a. n.a.

3-state output; 2 mA output drive HIGH

RESET

STATE

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2001 Oct 22 10

SYMBOL PIN TYPE DESCRIPTION BUFFER TYPE

MLCASN/BAA#/SIZE1 45 O column access strobe mid lower byte 3-state output; 2 mA output drive HIGH MUCASN/SIZE2 44 O column access strobe mid upper byte 3-state output; 2 mA output drive HIGH UCASN 42 O column access strobe upper byte 3-state output; 2 mA output drive HIGH WEN 62 O write enable 3-state output; 2 mA output drive HIGH DCS0N 47 O chip select for SDRAM bank 0 3-state output; 2 mA output drive HIGH CS[0:8]N 56 to 50,

O chip select 3-state output; 2 mA output drive HIGH

60, 61 CS[10:9]N

(1)

n.a. chip select extension shared with the IEEE 1284

n.a. n.a.

interface OEN/TSN 58 O output enable or Transfer Start indication 3-state output; 2 mA output drive HIGH DTACK 59 I data termination acknowledge CMOS input Z CLK 91 O 40.5 MHz clock 2 mA output drive T

UART 0 interface

TXD0 142 O UART 0 transmit data line 2 mA output drive HIGH RXD0 141 I UART0 receive data line CMOS input Z RTSN0 143 O UART 0 request to send 2 mA output drive HIGH CTSN0 144 I UART 0 clear to send CMOS input Z

UART 1 and SSI interface

TXD1/V34_TXD RXD1/V34_RXD RTSN1/V34_FS

CTSN1/V34_CLK

(2)

138 O transmit data line or transmit serial data to the CODEC 2 mA output drive HIGH 137 I receive data line or receive serial data from CODEC CMOS input Z 139 I/O request to send (output) or Frame synchronization

reference from CODEC (input)

140 I clear to send or serial input clock from CODEC (up to

bidirectional; CMOS input; 2 mA output drive

CMOS input Z

3.375 MHz)

MCLK 146 O master clock to the CODEC (up to 36.864 MHz) 2 mA output drive T

UART 2 interface

TXD2 136 O UART 2 transmit data line 2 mA output drive HIGH RXD2 135 I UART2 receive data line CMOS input Z

RESET

STATE

HIGH

Philips Semiconductors Product speciﬁcation

MPEG-2 Transport RISC processor SAA7240

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