Philips saa7219 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

SAA7219

MPEG2 Transport RISC processor

Product speciﬁcation Supersedes data of 1999 Sep 20 File under Integrated Circuits, IC02

2000 Jun 14

Philips Semiconductors Product speciﬁcation

MPEG2 Transport RISC processor SAA7219

1 FEATURES

1.1 External interfaces

1.2 CPU related features

1.3 MPEG2 systems features

2.1 SAA7219 overview

2.2 SAA7219 in a DVB system 3 ORDERING INFORMATION 5 PINNING 6 APPLICATION INFORMATION

6.1 Memory configurations 7 PACKAGE OUTLINE

8.1 Introduction to soldering surface mount packages

8.2 Reflow soldering

8.3 Wave soldering

8.4 Manual soldering

8.5 Suitability of surface mount IC packages for wave and reflow soldering methods

9 DATA SHEET STATUS 10 DEFINITIONS 11 DISCLAIMERS

2000 Jun 14 2

Philips Semiconductors Product speciﬁcation

MPEG2 Transport RISC processor SAA7219

1 FEATURES

• Conditional access descrambling Digital Video

Broadcasting (DVB) compliant and MULTI2 compliant

• Stream demultiplexing: Transport Stream (TS),

Packetized Elementary Stream (PES), program and proprietary streams

• Internal 32-bit MIPS RISC based Central Processing

Unit (CPU) supporting MIPS16 instruction set and running at 81 MHz

• Low-power sleep modes supported across the chip

• Comprehensive driver software and development tool

support

• Package: SQFP208.

1.1 External interfaces

• Versatile compressed stream input at 108 Mbits/s

• A 32-bit microcontroller extension bus supporting

DRAM, SDRAM,Flash, (E)PROM andexternal memory mapped I/O devices. It also supports a synchronous interface to communicate with the integrated MPEG Audio Video Graphics Decoder (AVGD) SAA7215 at

40.5 Mbytes.

• An IEEE 1284 interface(Centronics) supporting master

and slave modes. Usable as a general purpose port.

• An interface to IEEE 1394 devices (such as Philips

PDI 1394 chip-set)

• Two UART (RS232) data ports with Direct Memory

Access (DMA) capabilities (187.5 kbits/s) including hardware flow control signals RXD, TXD, RTS and CTS for modem support

• A Synchronous Serial Interface (SSI) to connect an

off-chip modem analog front-end

• An elementary UART with DMA capabilities, dedicated

to front panel devices for instance

• Two dedicated smart-card reader interfaces (ISO 7816

compatible) with DMA capabilities

• Two I2C-bus master/slave transceivers with DMA

capabilities, supporting the standard (100 kbit/s) and fast (400 kbits/s) I2C-bus modes

• 32 general purpose, bidirectional I/O interface pins, 8 of

which may also be used as interrupt inputs

• One Pulse Width Modulated (PWM) output with 8-bit

resolution

• A General Purpose/High-Speed (GP/HS) interface supporting stream recording through IEEE 1394 interface IC

• An extended JTAG interface for board test support.

1.2 CPU related features

The SAA7219 contains an embedded RISC CPU, which incorporates the following features:

• A 32-bit PR3930 core running at 81 MHz

• 8-kbyte, 2-way set associative instruction cache

• 4-kbyte, 4-way set associative data cache

• A programmable low-power mode, including wake-up

on interrupt

• A memory management unit with 32 odd/even entries and variable page sizes

• Multiply/accumulate/divide unit with fast multiply/accumulate for 16-bit and 32-bit operands

• Two fully independent 24-bit timers and one 24-bit timer including watchdog facilities

• A real-time clock unit (active in Sleep mode)

• Built-in software debug support unit as part of Extended

Enhanced JTAG debug interface

• On-chip SRAM of 4 kbytesfor storing code whichneeds fast execution.

1.3 MPEG2 systems features

• Hardware based parsing of Transport Stream (TS), Philips Semiconductors program and proprietary software data streams. Maximum input rate is 108 Mbits/s.

• A real-time descrambler consisting of 3 modules: – A control word bank containing 14 pairs (odd, even)

of control words and a default control word

– The DVB descrambler core implementing the stream

decipher and block decipher algorithms

– The MULTI2 descrambler algorithm implementing

the CBC and OFB mode descrambling functions.

2000 Jun 14 3

Philips Semiconductors Product speciﬁcation

MPEG2 Transport RISC processor SAA7219

• Hardware section filtering based on 32 different Packet Identifiers (PIDs) with a flexible number of filter conditions (8 or 4-byte condition plus 8 or 4-byte mask) per PID and a total filter capacity of 40 (8-byte condition checks) or up to 80 (4-byte condition checks) filter conditions:

– 4 TS/PES filters for retrieval for data at TS or PES

level for applications such as subtitling, TXT or retrieval of private data

– Flexible DMA based storage of the 32 section

substreams and 4 TS/PES data substreams in the external memory.

• System time base management with a double counter mechanism for clock control and discontinuity handling, 2 Presentation Time Stamp (PTS)/Decoding Time Stamp (DTS) timers

• A GP/HS filter which can serve as an alternate input from for example IEEE 1394 devices. The IEEE 1394 GP/HS mode supports packet insertion and has an internal SRAM for storing 2 packets. It can also output either scrambled or descrambled TS to IEEE 1394 devices.

2 GENERAL DESCRIPTION

2.1 SAA7219 overview

The device is part of a comprehensive source decoding kit which contains all the hardware and software required to receive and decode MPEG2 transport streams, including descrambling, demultiplexing. In addition, it includes a PR3930 core which is a 32-bit MIPS RISC-based CPU core supporting the MIPS 16 instruction set to reduce memory requirements and several peripheral interfaces such as UARTs, I2C-bus units, an IEC 1883, and an IEEE 1284 (Centronics) interface. The SAA7219 is therefore capable of performing all controller tasks in digital television receiver applications such as set-top boxes. Furthermore, the SAA7219 is compliant to DVB and MULTI2 standards.

The SAA7219 receives transport streams through a versatile stream input interface capable of handling both byte-parallel and bit-serial streams in various formats, supporting data streams up to and including 13.5 Mbyte/s (108 Mbits/s).Thestreamdataisfirstappliedtoanon-chip descrambler incorporating a DVB descramblingalgorithm, on the basis of 14 control word pairs stored in on-chip RAM. Demultiplexing is subsequently applied to the stream, to separate up to 32 individual data streams.

The demultiplexer section includes clock recovery and timebase management. Program Specific Information (PSI), Service Information (SI), Conditional Access (CA) messages and private data are selected and stored in external memory, for subsequent off-line processing by the internal PR3930 CPU core.

To support advanced board testing facilities the SAA7219 includes boundary scan test hardware, according to the EJTAG standard. The device features a low-power sleep mode, which is capable of sustaining set-top box standby functionality, thus eliminating the need for a separate front panel controller. The SAA7219 requires a supply voltage of 3.3 V and most devices input and output interfaces are 5 V tolerant except the extension bus which is 3.3 V only. The SAA7219 is mounted in a SQFP208 package.

2.2 SAA7219 in a DVB system

The SAA7219 has been designed to offer optimum performance when used with the SAA7215 for MPEG2 AVG decoding.

• Synchronous bus interface transfer at 40.5 MHz on 16 bits

• SAA7215 has one dedicated SDRAM for MPEG2 audio video handling and one for graphics and CPU data. The second memory offers high bandwidth and low latency tothe SAA7219 when accessing it to downloadgraphics or executing some applications. This enables a high level of performance together with a low system cost by having one SDRAM for graphics and CPU data.

3 ORDERING INFORMATION

PACKAGE

TYPE NUMBER

NAME DESCRIPTION VERSION

SAA7219HS/C2 SQFP208 plastic shrink quad ﬂat package; 208 leads (lead length 1.3 mm); body

28 × 28 × 3.4 mm; high stand-off height

2000 Jun 14 4

SOT316-1

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2000 Jun 14 5

input

stream

output

stream

CPU section

MIPS

PR3930

CORE

DATA CACHE

INSTRUCTION CACHE

TIMER 1

INPUT

INTERFACE

GP/HS

INTERFACE

1394 GATEWAY

pagewidth

PWM

PID

FILTER

PCR

PROCESSING

DESCRAMBLER

DVB AND MULTI2 MPEG system-bus

TS/PES

FILTERS

demultiplexer descrambler section

FILTER

SECTION

FILTERS

AUDIO AND

VIDEO

INTERFACE

AVD

interface

4 BLOCK DIAGRAM

Philips Semiconductors Product speciﬁcation

MPEG2 Transport RISC processor SAA7219

TIMER 2

TIMER 3 (WATCHDOG)

DSU

EJTAG

SS MM

PI-BUS

CTRL

JTAG

JTAG interface

M = master peripheral with embedded DMA channel S = slave peripheral

EXTENSION BUS

MMU

CONTROLLER

bus interface

CARD READER UART

smart card

interface

PI-bus

UART and SSI

connections

MPEG SYSTEM

GATEWAY

SSI

PIO

INTERFACE

I2C

010

SCL and

SDA lines

FILTER DMA

CONTROLLER

1284

32 kHz

1284 bus32-bit PIOexternal

MPEG SYSTEM

INT.HANDLER

SS S

RTC

INTERRUPT

CONTROLLER

peripheral section

4-KBYTE

SRAM

FCE374

Reset

Clock

Fig.1 Block diagram.

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2000 Jun 14 6

5 PINNING Table 1 SQFP208 package: 179 functional pins and 29 power supply pins

SYMBOL PIN I/O BUFFER TYPE VOLT

PIO interface (32 pins)

PIO0 to PIO7 105 to 112 I/O bidirectional, 3 mA output drive 5 V usable as interrupt inputs and/or I/O lines PIO8/BOOTIS32 113 I/O bidirectional, 3 mA output drive 5 V PIO bit and PIO-strap. At power-on, it indicates the

PIO9/BOOTIS16 114 I/O bidirectional, 3 mA output drive 5 V PIO bit and PIO-strap. At power-on, if BOOTIS32 is

PIO10 to PIO15 116 to 121 I/O bidirectional, 3 mA output drive 5 V PIO bit and PIO-strap PIO(31:16)/D(31:16) 2, 4 to 9, 11 to 16,

18 to 20

Extension bus (58 pins)

D15 to D0 21, 22, 24, 25,

28 to 30, 33 to 36, 38 to 41

A0 to A21 63 to 65, 67 to 71,

73 to 77, 81 to 85,

87 to 90 RAS0N 49 O 8 mA output drive 3.3 V row access strobe for DRAM and SDRAM Bank 0 RAS1N/DCS1N 48 O 8 mA output drive 3.3 V row access strobe for DRAM and SDRAM Bank 1 LCASN 46 O 8 mA output drive 3.3 V column access strobe lower byte MLCASN 43 O 8mA output drive 3.3 V column access strobe mid lower byte MUCASN 44 O 8 mA output drive 3.3 V column access strobe mid upper byte UCASN 42 O 8 mA output drive 3.3 V column access strobe upper byte WEN 62 O 8 mA output drive 3.3 V write enable DCS0N 47 O 8mA output drive 3.3 V chip select for SDRAM Bank 0 CS6N to CS0N 50 to 56 O 8 mA output drive 3.3 V chip select OEN 58 O 8 mA output drive 3.3 V output enable DTACKN 59 I TTL input 5 V Data termination acknowledge. Asserted LOW by

CS_SDN 60 O 2 mA output drive 3.3 V selects the graphics SDRAM memory space of the

I/O bidirectional, 6 mA output drive 5 V I/O lines or upper 16-bit data bus. The data bus

I/O bidirectional, 8 mA output drive 3.3 V lower 16-bit data bus

O 8 mA output drive 3.3 V address bus

(1)

data bus size of the booting device.

LOW, it indicates if the system should reboot from a 16-bit or 8-bit device.

width of the booting device is automatically conﬁgured at power-on.

the peripheral when the data bus is valid.

SAA7215

DESCRIPTION

Philips Semiconductors Product speciﬁcation

MPEG2 Transport RISC processor SAA7219

+ 14 hidden pages

Philips saa7219 DATASHEETS

CONTENTS

1 FEATURES

1.1 External interfaces

1.2 CPU related features

1.3 MPEG2 systems features

2 GENERAL DESCRIPTION

2.1 SAA7219 overview

2.2 SAA7219 in a DVB system

3 ORDERING INFORMATION

4 BLOCK DIAGRAM

5 PINNING Table 1 SQFP208 package: 179 functional pins and 29 power supply pins