Philips SAA7199BWP Datasheet

INTEGRATED CIRCUITS

DATA SH EET

SAA7199B

Digital Video Encoder (DENC) GENLOCK-capable

Product speciﬁcation Supersedes data of April 1993 File under Integrated Circuits, IC22

1996 Sep 27

Philips Semiconductors Product speciﬁcation

Digital Video Encoder (DENC) GENLOCK-capable

FEATURES

• Monolithic integrated CMOS video encoder circuit

• Standard MPU (12 lines) and I2C-bus interfaces for

controls

• Three 8-bit signal inputs PD7 to PD0 for RGB respectively YUV or indexed colour signals (Tables 19 to 26)

• Square pixel and CCIR input data rates

• Band limited composite sync pulses

• Three 256 × 8 colour look-up tables (CLUTs)

for example for gamma correction

• External subcarrier from a digital decoder (SAA7151B or SAA7191B)

• Multi-purpose key for real time format switching

• Autonomous internal blanking

• Optional GENLOCK operation with adjustable horizontal

sync timing and adjustable subcarrier phase

• Stable GENLOCK operation in VCR standard playback mode

• Optional still video capture extension

• Three suitable video 9-bit digital-to-analog converters

• Composite analog output signals CVBS, Y and C for

PAL/NTSC

• Line 21 data insertion possible.

SAA7199B

GENERAL DESCRIPTION

The SAA7199B encodes digital baseband colour/video data into analog Y, C and CVBS signals (S-video included). Pixel clock and data are line-locked to the horizontal scanning frequency of the video signal. The circuit can be used in a square pixel or in a consumer TV application. Flexibility is provided by programming facilities via MPU-bus (parallel) or I2C-bus (serial).

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

DDD

DDA

P(tot)

digital supply voltage (pins 2, 21 and 41) 4.5 5.0 5.5 V analog supply voltage (pins 64, 66, 70 and 72) 4.75 5.0 5.25 V total supply current −−200 mA input signal levels TTL-compatible analog output voltage Y, C and CVBS without load (peak-to-peak value) − 2 − V

output load resistance 90 −−Ω ILE LF integral linearity error in output signal (9-bit DAC) −−±1 LSB DLE LF differential linearity error in output signal (9-bit DAC) −−±0.5 LSB T

amb

operating ambient temperature 0 − 70 °C

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

SAA7199BWP PLCC84

plastic leaded chip carrier; 84 leads

PACKAGE

SOT189-2

1996 Sep 27 2

Philips Semiconductors Product speciﬁcation

Digital Video Encoder (DENC) GENLOCK-capable

BLOCK DIAGRAM

outputs to

Y 



DACs

TRIPLE

ENCODER



OUTPUT

+5 V

to

DDA1

KEY

DDA4

CUR

refH

66, 70,

72, 64

C 

monitor/TV

CVBS

BUFFERS

SSA

SAA7199B

XTALI

refL

SAA7199B

XTALO

CLOCK INTERFACE

MEH416

52495051235556

CLKO CLKSEL

LLC

CREF

358846174753635

VSN/CSYN PIXCLK CLKIN

SLT

ook, full pagewidth

+5 V

to V

MPK

to V

SSD3

SSD1

DDD3

DDD1

1, 22, 42

2, 21, 41

(1)

3 × 8-bit input data

11 to 4

(1)

PD1(7 to 0)

(digital red)

RTCI

MATRIX

3 ¥

CLUTS

256 ¥ 8

INPUT

INTERFACE

19 to 12

(digital green)

PD2(7 to 0)

31 to 24

(1)

PD3(7 to 0)

(digital blue)

internal control bus

83 to 76



LDV

CVBS(7 to 0)

STATUS

SYNC PROCESSING

46 to 43,

40 to 37

34 33

CONTROL INTERFACE

5754

C-BUS

CONTROL

SCL

SDA

C-bus

LFCO

HCL

RTCI/

GPSW

RESET

HSY HSN

D(7 to 0)

R/W

to/from microcontroller

Fig.1 Block diagram.

1996 Sep 27 3

(1) RGB respectively input formats YUV and indexed colour (Tables 19 to 26).

Philips Semiconductors Product speciﬁcation

Digital Video Encoder (DENC)

SAA7199B

GENLOCK-capable

PINNING

SYMBOL PIN DESCRIPTION

SSD1

DDD1

VSN/CSYN 3 vertical sync output (3-state), conditionally composite sync output; active LOW or active HIGH PD1(0) 4 data 1 input: digital signal R (red) respectively V signal; bit 0 (formats in Tables 19 to 25) PD1(1) 5 data 1 input: digital signal R (red) respectively V signal; bit 1 (formats in Tables 19 to 25) PD1(2) 6 data 1 input: digital signal R (red) respectively V signal; bit 2 (formats in Tables 19 to 25) PD1(3) 7 data 1 input: digital signal R (red) respectively V signal; bit 3 (formats in Tables 19 to 25) PD1(4) 8 data 1 input: digital signal R (red) respectively V signal; bit 4 (formats in Tables 19 to 25) PD1(5) 9 data 1 input: digital signal R (red) respectively V signal; bit 5 (formats in Tables 19 to 25) PD1(6) 10 data 1 input: digital signal R (red) respectively V signal; bit 6 (formats in Tables 19 to 25) PD1(7) 11 data 1 input: digital signal R (red) respectively V signal; bit 7 (formats in Tables 19 to 25) PD2(0) 12 data 2 input: digital signal G (green) respectively Y signal or indexed colour data; bit 0

PD2(1) 13 data 2 input: digital signal G (green) respectively Y signal or indexed colour data; bit 1

PD2(2) 14 data 2 input: digital signal G (green) respectively Y signal or indexed colour data; bit 2

PD2(3) 15 data 2 input: digital signal G (green) respectively Y signal or indexed colour data; bit 3

PD2(4) 16 data 2 input: digital signal G (green) respectively Y signal or indexed colour data; bit 4

PD2(5) 17 data 2 input: digital signal G (green) respectively Y signal or indexed colour data; bit 5

PD2(6) 18 data 2 input: digital signal G (green) respectively Y signal or indexed colour data; bit 6

PD2(7) 19 data 2 input: digital signal G (green) respectively Y signal or indexed colour data; bit 7

LDV 20 load data clock input signal to input interface (samples PDn(7 to 0), V

DDD2

SSD2

CB 23 composite blanking input; active LOW PD3(0) 24 data 3 input: digital signal B (blue) respectively U signal; bit 0 (formats in Tables 19 to 25) PD3(1) 25 data 3 input: digital signal B (blue) respectively U signal; bit 1 (formats in Tables 19 to 25) PD3(2) 26 data 3 input: digital signal B (blue) respectively U signal; bit 2 (formats in Tables 19 to 25) PD3(3) 27 data 3 input: digital signal B (blue) respectively U signal; bit 3 (formats in Tables 19 to 25) PD3(4) 28 data 3 input: digital signal B (blue) respectively U signal; bit 4 (formats in Tables 19 to 25) PD3(5) 29 data 3 input: digital signal B (blue) respectively U signal; bit 5 (formats in Tables 19 to 25) PD3(6) 30 data 3 input: digital signal B (blue) respectively U signal; bit 6 (formats in Tables 19 to 25) PD3(7) 31 data 3 input: digital signal B (blue) respectively U signal; bit 7 (formats in Tables 19 to 25) MPK 32 multi-purpose key input; active HIGH A0 33 subaddress bit A0 input for microcontroller access (Table 3)

1 digital ground 1 (0 V) 2 digital supply 1 (5 V)

(formats in Tables 19 to 25)

CB, MPK, KEY and RTCI) 21 digital supply 2 (5 V) 22 digital ground 2 (0 V)

1996 Sep 27 4

Philips Semiconductors Product speciﬁcation

Digital Video Encoder (DENC)

SAA7199B

GENLOCK-capable

SYMBOL PIN DESCRIPTION

A1 34 subaddress bit A1 input for microcontroller access (Table 3)

W 35 read/write not input signal from microcontroller

R/ CS 36 chip select input for parallel interface; active LOW D0 37 bidirectional port from/to microcontroller; bit D0 D1 38 bidirectional port from/to microcontroller; bit D1 D2 39 bidirectional port from/to microcontroller; bit D2 D3 40 bidirectional port from/to microcontroller; bit D3 V

DDD3

SSD3

D4 43 bidirectional port from/to microcontroller; bit D4 D5 44 bidirectional port from/to microcontroller; bit D5 D6 45 bidirectional port from/to microcontroller; bit D6 D7 46 bidirectional port from/to microcontroller; bit D7 SDA 47 I SCL 48 I CLKIN 49 external clock signal input (maximum frequency 60 MHz) CLKSEL 50 clock source select input PIXCLK 51 CLKO/2 or conditionally CLKO output signal CLKO 52 selected clock output signal (LLC or CLKIN) TP 53 test pin; connected to ground RESET 54 reset input; active LOW LLC 55 line-locked clock input signal from external clock generation circuit (CGC) CREF 56 clock qualiﬁer input of external CGC GPSW/RTCI 57 general purpose switch output (set via I

SLT 58 GENLOCK output ﬂag (3-state): HIGH = sync lost in GENLOCK mode; LOW = otherwise XTALI 59 crystal oscillator input (26.8 or 24.576 MHz) XTALO 60 crystal oscillator output LFCO 61 line frequency control output signal for external CGC V

refL

refH

DDA4

C 65 chrominance analog output signal V

DDA1

Y 67 luminance analog output signal V

SSA

CVBS 69 CVBS analog output signal V

DDA2

CUR 71 current input for analog output buffers V

DDA3

KEY 73 key input signal to insert CVBS input signal into encoded CVBS output signal; active HIGH

41 digital supply 3 (5 V) 42 digital ground 3

C-bus data input/output

C-bus clock input

C-bus or MPU-bus); real time control input, deﬁned

by I2C or MPU programming

62 reference voltage LOW of DACs (resistor chains) 63 reference voltage HIGH of DACs (resistor chains) 64 analog supply 4 for resistor chains of the DACs (5 V)

66 analog supply 1 for output buffer ampliﬁer of DAC1 (5 V)

68 analog ground (0 V)

70 analog supply 2 for output buffer ampliﬁer of DAC2 (5 V)

72 analog supply 3 for output buffer ampliﬁer of DAC3 (5 V)

1996 Sep 27 5

Philips Semiconductors Product speciﬁcation

Digital Video Encoder (DENC) GENLOCK-capable

SYMBOL PIN DESCRIPTION

HSY 74 horizontal sync indicator output signal; active HIGH (3-state output to ADC) HCL 75 horizontal clamping output; active HIGH (3-state output) CVBS0 76 digital CVBS input signal; bit 0 CVBS1 77 digital CVBS input signal; bit 1 CVBS2 78 digital CVBS input signal; bit 2 CVBS3 79 digital CVBS input signal; bit 3 CVBS4 80 digital CVBS input signal; bit 4 CVBS5 81 digital CVBS input signal; bit 5 CVBS6 82 digital CVBS input signal; bit 6 CVBS7 83 digital CVBS input signal; bit 7 HSN 84 horizontal sync output; active LOW or active HIGH for 60/66/72 × PIXCLK at

12.27/13.5/14.75 MHz (3-state output)

SAA7199B

1996 Sep 27 6

Philips Semiconductors Product speciﬁcation

Digital Video Encoder (DENC) GENLOCK-capable

handbook, full pagewidth

PD1(7)

PD1(6)

PD1(5)

PD1(4)

PD1(3)

PD1(2)

PD2(0) PD2(1) PD2(2) PD2(3) PD2(4) PD2(5) PD2(6) PD2(7)

LDV

DDD2

SSD2

PD3(0) PD3(1) PD3(2) PD3(3) PD3(4) PD3(5) PD3(6) PD3(7)

MKP

12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

PD1(1) 5

PD1(0) 4

DDD1VSSD1

VSN/CSYN

SAA7199B

HSN

CVBS7

CVBS6

CVBS5

CVBS4

CVBS3

CVBS2

CVBS1

CVBS0

HCL

HSY

KEY

73 72

DDA3

CUR

71 70

DDA2

CVBS

69 68

SSA

67 66

DDA1

65 64

DDA4

refH

refL

LFCO

XTALO

XTALI

SLT

RTCI/

GPSW CREF

LLC

55 54

RESET

R/W

DDD3

SSD3

Fig.2 Pin configuration.

1996 Sep 27 7

43 D4

44 D5

45 D6

46 D7

SDA

SCL

CLKIN

PIXCLK

CLKSEL

CLKO

53 TP

MEH417

Philips Semiconductors Product speciﬁcation

Digital Video Encoder (DENC) GENLOCK-capable

FUNCTIONAL DESCRIPTION

The SAA7199B is a digital video encoder that translates digital RGB, YUV or 8-bit indexed colour signals into the analog PAL/NTSC output signals Y (luminance), C (4.43/3.58 MHz chrominance) and CVBS (composite signal including sync).

Four different modes are selectable (Table 18):

Stand-alone mode (horizontal and vertical timings are generated)

Slave mode (stand-alone unit that accepts external horizontal and vertical timing), and optional real time information for subcarrier/clock from a digital colour decoder

GENLOCK mode (GENLOCK capabilities are achieved in conjunction with determined ICs)

Test mode (only clock signal is required).

The input data rate (pixel sequence) has an integer relationship to the number of horizontal clock cycles (Table 1). A sufficient stable external clock signal ensures correct encoding. The generated clock frequency in the GENLOCK mode may deviate by ±7% depending on the reference signal which is corresponding to its input sync signal. The clock will be nominal in the GENLOCK mode when the reference signal is absent (nominal with crystal oscillator accuracy for TV time constants, and nominal ±1.4% for VCR time constants).

The on-chip colour conversion matrix provides “ code-compatible transcoding of RGB to YUV data.

RGB data out of bounds, with respect to specification, can be clipped to prevent over-loading of the colour modulator. RGB data input can be either in linear colour space or in gamma-corrected colour space.

YUV data must be gamma-corrected in accordance with “

CCIR 601”

colour space (3 × 8-bit) but can also accommodate different data formats (4 :1:1, 4:2:2 and 4:4:4) plus 8-bit indexed pseudo-colour space operations (FMT-bits in Table 8).

RGB CLUTs on-chip provide gamma-correction and/or other CLUT functions. They consist of programmable tables to be loaded independently, and they generate 24-bit gamma-corrected output signals from 24-bit data of one of the input formats or from 8-bit indexed pseudo-colour data.

. This circuit operates primarily in a 24-bit

CCIR 601”

“CCIR 601”

SAA7199B

Required modulation is performed. The digital YUV data is encoded in accordance with standards (composite NTSC) and PAL-B/G). S-video output signal is available (Y/C) also some sub-standard output signals (STD-bits in Table 12).

A 7.5 IRE set-up level is automatically selected in the 60 Hz mode, but not selected in the 50 Hz mode.

The analog signal outputs can drive directly into terminated 75 Ω coaxial lines, a passive external filter is recommended (Figs 3, 13 and 14). Analog post-filtering is required (LP in Fig.3).

GENLOCK to an external reference signal is achieved by addition of a video ADC and a clock generator combination. Thus, the system is enabled to lock on a stable video source or to a stable VCR source (normal playback). The SAA7199B, the ADC and the clock generator combination (Fig.3) form a control loop achieving a highly stable line-locked clock. The clock has to be generated by a crystal oscillator without this availability. The GENLOCK mode is not available in a single device set-up.

Control interface

The SAA7199B supports a standard parallel MPU interface and the serial I direct access to internal control registers and colour tables. Update is possible at any time, excluding coincident internal reading and external writing of the same cell (the current pixel value could be destroyed).

The two interfaces of Table 2 are selected automatically. However, the I2C-bus control is inactive when the MPU interface is selected by CS = LOW. No simultaneous access may occur. I2C-bus and MPU control complement each other and have access to common registers controlled via a common internal bus. The programmer can use virtually identical programs.

The internal memory space is devided into the look-up table and the control table, each with its own 8-bit address register used as a pointer for specific location. This address register is provided with auto-incrementation and can be written by only one addressing.

The look-up table contains three banks of 256 bytes. Therefore, each read or write cycle must access all three banks in a pre-determined order. The support logic is part of the control interface.

“CCIR 624-4

C-bus interface. The MPU has

“RS-170A

” (composite

”

1996 Sep 27 8

Philips Semiconductors Product speciﬁcation

Digital Video Encoder (DENC) GENLOCK-capable

Timing (see Fig.3) The reference to generate internal clocks from LLC in

GENLOCK operation with SAA7197 is CREF CREF = .

In this event input CLKSEL is HIGH and the SRC-bit = 1. In non-GENLOCK operation the signal from CLKIN is used

and LDV is clock reference (input CLKSEL = 0; SCR-bit = CPR-bit = 0).

Pins LLC and CLKIN are tied together when no switching between LLC and CLKIN is applied. In Fig.3 it is assumed that LLC and CLKIN are double the pixel clock frequency of CREF and LDV respectively.

CREF must be at the same frequency (or constant HIGH or LOW) when LLC is at pixel clock frequency. CPR-bit = 1 if CLKIN is at pixel clock frequency.

The buffered CLKO signal is always delayed. LLC or CLKIN signals are in accordance with CLKSEL.

Mapping

The method of mapping external control signals on to the internal bus is simple. The MPU-bus contains the signals as shown in Table 4 (names in chip-internal nomenclature).

LLC

----------2

SAA7199B

Bit allocation

The Bit Allocation Map (BAM) shows the individual control signals, used to control the different operational modes of the circuit. The I The SAA7199B also has an MPU-bus interface for direct microcontroller connection. The BAM shown in Table 6 resembles the I2C-bus type but can be also used for the parallel bus; the control registers are indexed from 00H to 0FH. Auto-incrementation is applied.

Digital-to-analog converters

The converters use a combination of resistor chains with low-impedance output buffers. The bottom output voltage is 200 mV to reduce integral non-linearity errors. The analog signal, without load on output pin, is between

0.2 and 2.2 V. Figure 16 shows the application for

1.23 V/75 Ω outputs, using the serial 25 + 22 Ω resistors. Each digital-to-analog converter has its own supply pin for

the purpose of decoupling. V the resistor chains of the three DACs. The accuracy of this supply voltage directly influences the output amplitudes. The current CUR into pin 71 is 0.3 mA (V R

=20kΩ); a larger current improves the bandwidth

64-71

but increases the integral non-linearity.

C-bus is normally used for control.

is the supply voltage for

DDA4

=5V;

DDA4

Table 1 Pixel relationships

ACTIVE PIXELS

PER LINE

640 (square) 60 780 12.27 26.8 720 60 858 13.5 24.576 768 50 944 14.75 26.8 720 50 864 13.5 24.576

Table 2 Access to the control interface

SYMBOL DESCRIPTION

SDA I SCL I A1, A0 MPU-bus address inputs

W read/write control input

R/ CS chip select input; I2C-bus disabled when LOW GPSW general purpose switch output (bit of control register) RESET reset input signal; active-LOW

FIELD RATE

(Hz)

C-bus serial data line (bidirectional)

C-bus clock line

MULTIPLES OF LINE

FREQUENCY

PIXCLK OUTPUT SIGNAL

(MHz)

CRYSTAL

(MHz)

1996 Sep 27 9

Philips Semiconductors Product speciﬁcation

Digital Video Encoder (DENC) GENLOCK-capable

Table 3 Address assignment

ADDRESS INPUTS

A1 A0

0 0 00 ADR-CLUT (address register of look-up tables) 0 1 01 DATA-CLUT 1 0 02 ADR-CTRL (index register of control table) 1 1 03 DATA-CTRL

Table 4 Signals on the internal bus

SYMBOL DESCRIPTION

W select read/write (read = 1; write = 0)

T control table/look-up table (control table = 1; look-up table = 0)

A select data/address (data = 1; address = 0)

D/ DI/DO (0 to 7) data bus on port inputs/outputs D7 to D0 EN enable from control interface to synchronize data transfer

I2C-BUS SUBADDRESS SELECTION

SAA7199B

Table 5 Signals on the internal bus

INTERNAL PARALLEL BUS PARALLEL INTERFACE I

WR/W (pin 35) LSB of slave address byte (read = HIGH; write = LOW) T A1 (pin 34) X 4 subaddresses after decoding

T A0 (pin 33) X 4 subaddresses after decoding

A/ DI/DO (0 to 7) D7 to D0 data bits D7 to D0 for each subaddress EN

CS and R/W enable by every 9th clock of sample of SCL

(control of serial-to-parallel conversion)

C-BUS INTERFACE

1996 Sep 27 10

Philips Semiconductors Product speciﬁcation

Digital Video Encoder (DENC) GENLOCK-capable

optional)

(passive filters 

analog outputs

LFCO

LLC

RESET CREF

(2)

RTCI



HSY GPSW

HCL

ook, full pagewidth

SAA7197 (CGC)

(1)

GPSW



LFCO

LLCA

CREF

RESET

SAA7199B

CVBS

MHA 418

CLKO CLKIN

XTALI

XTALO

CLKSEL

)

pix

or 2f

mode

pix

pixel frequency

in non-GENLOCK

CLK LLC2A

TDA8708A (ADC)

VIN0

(1)

CVBS1

RTCO (from SAA7151B or SAA7191B)

CVBS2

D(7 to 0)

VIN1

C-bus controls

CVBS(7 to 0)

SDA

SCL

HSN

PIXCLK

VSN

data

input

PD2(7 to 0)

PD1(7 to 0)

RAM

data

PD3(7 to 0)

LDV

INTERFACE

controls

1996 Sep 27 11

KEY

R/W

A0 A1 SLT

D(7 to 0)

MPK

Fig.3 System configuration.

MPU

INTERFACE

controls

(1) Not necessary in GENLOCK mode.

(2) RTCI optional (GPSW not possible).

Philips Semiconductors Product speciﬁcation

Digital Video Encoder (DENC)

SAA7199B

GENLOCK-capable

Table 6 Bit allocation map (I2C-bus access in Table 17)

INDEX DATA BYTE

BINARY HEX D7 D6 D5 D4 D3 D2 D1 D0

Input processing

0000 0000 00 VTBY FMT2 FMT1 FMT0 SCBW CCIR MOD1 MOD0 5C 0000 0001 01 TRER7 TRER6 TRER5 TRER4 TRER3 TRER2 TRER1 TRER0 XX 0000 0010 02 TREG7 TREG6 TREG5 TREG4 TREG3 TREG2 TREG1 TREG0 XX 0000 0011 03 TREB7 TREB6 TREB5 TREB4 TREB3 TREB2 TREB1 TREB0 XX

Sync processing

0000 0100 04 SYSEL1 SYSEL0 SCEN VTRC NINT HPLL HLCK

(2)

0000 0101 05 0 0 GDC5 GDC4 GDC3 GDC2 GDC1 GDC0 21 0000 0110 06 IDEL7 IDEL6 IDEL5 IDEL4 IDEL3 IDEL2 IDEL1 IDEL0 52 0000 0111 07 0 0 PSO5 PSO4 PSO3 PSO2 PSO1 PSO0 32

Control, clock and output formatter

0000 1000 08 DD KEYE SRC CPR COKI IM GPSW SRSN 64 0000 1001 09 0 BAME MPKC1 MPKC0 IEPI RTSC RTIN RTCE 02 0000 1010 0000 1011

(3) (3)

0A 0B

(3)

0000000000

(3)

0000000000

OEF

(2)

(1)

Encoder control

0000 1100 0C CHPS7 CHPS6 CHPS5 CHPS4 CHPS3 CHPS2 CHPS1 CHPS0 XX

(4)

0000 1101 0D FSCO7 FSCO6 FSCO5 FSCO4 FSCO3 FSCO2 FSCO1 FSCO0 00

(2)

0000 1110 0E 0 0 0 CLCK 0000 1111

(3)

00000000

STD3 STD2 STD1 STD0 0C

Notes

1. DF is the default value for a typical programming example: GENLOCK mode for a VCR; non-gamma-corrected RGB data (real time keying is possible). SLT will be set if there is no horizontal lock.NTSC-M standard with normal colour bandwidth and 12.2727 MHz pixel rate. CSYN signal will be provided, arriving 8 pixel clocks earlier, to compensate pipeline delay in the previous RAM interface. The encoded CVBS is 12 clocks earlier than the CVBS reference on the input of the previous ADC. The CLUTs are bypassed at MPK = HIGH in real time.

2. Read only bits.

3. Reserved.

4. Adjust as required.

1996 Sep 27 12

+ 28 hidden pages