Philips saa7197 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

SAA7197

Clock Generator Circuit for desktop
video systems (CGC)

Product specification
File under Integrated Circuits, IC22

August 1996

Philips Semiconductors Product specification

Clock Generator Circuit for desktop video systems (CGC) SAA7197

FEATURES

• Suitable for Desktop Video systems

• Two different sync sources selectable

• PLL frequency multiplier to generate 4 times of input

frequency

GENERAL DESCRIPTION

The SAA7197 generates all clock signals required for a
digital TV system suitable for the SAA719x family. The
circuit operates in either the phase-locked loop mode
(PLL) or voltage controlled oscillator mode (VCO).

• Dividers to generate clocks LLCA, LLCB, LLC2A and
LLC2B (2nd and 4th multiples of input frequency)

• PLL mode or VCO mode selectable

• Reset control and power fail detection

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V

DDA

V

DDD

I

DDA

I

DDD

V

LFCO

f

i

V

I

V

O

T

amb

analog supply voltage (pin 5) 4.5 5.0 5.5 V
digital supply voltage (pins 8, 17) 4.5 5.0 5.5 V
analog supply current 3 − 9mA
digital supply current 10 − 60 mA
LFCO input voltage (peak-to-peak value) 1 − V

DDA

input frequency range 5.5 − 8.0 MHz
input voltage LOW 0 − 0.8 V
input voltage HIGH 2.0 − V

DDD

output voltage LOW 0 − 0.6 V
output voltage HIGH 2.6 − V

DDD

operating ambient temperature range 0 − 70 °C

V

V

V

ORDERING INFORMATION

EXTENDED TYPE

NUMBER

PINS PIN POSITION MATERIAL CODE

SAA7197P 20 DIP plastic SOT146-1
SAA7197T 20 SO plastic SOT163-1

August 1996 2

PACKAGE

Philips Semiconductors Product specification

Clock Generator Circuit for desktop video systems (CGC) SAA7197

BLOCK DIAGRAM

handbook, full pagewidth

MS 1

LFCO

CE

11

19LFCO2
2

LFCOSEL

LOOP

FILTER

PHASE

DETECTOR

PRE-FILTER

AND

PULSE

SHAPER

MS = LOW

V

V

VCO

FREQUENCY

DIVIDER

16

DDD1

DDA

5178

1 : 2

POWER-ON

RESET

PORD

V

DDD2

FREQUENCY

DIVIDER

1 : 2

DELAY

4

V

SSA

SAA7197

6, 9, 13, 183

V

SSD

7

LLCA

10

LLCB

14

LLC2A

20

LLC2B

15

CREF

12

RESN

MEH461

Fig.1 Block diagram.

FUNCTION DESCRIPTION

The SAA7197 generates all clock signals required for a
digital TV system suitable for the SAA719x family
consisting of an 8-bit analog-to-digital converter (ADC8),
digital video multistandard decoder, square pixel
(DMSD-SQP), digital video colour space converter
(DCSC) and optional extensions. The SAA7197 completes
a system for Desktop Video applications in conjunction
with memory controllers.

The input signal LFCO is a digital-to-analog converted
signal provided by the DMDS-SQPs horizontal PLL. It is
the multiple of the line frequency:

7.38 MHz = 472 × f

in 50 Hz systems

H

6.14 MHz = 360 × fHin 60 Hz systems

LFCO2 (TTL-compatible signal from an external reference
source) can be applied to pin 19 (LFCOSEL = HIGH).

August 1996 3

The input signal LFCO or LFCO2 is multiplied by factors 2
or 4 in the PLL (including phase detector, loop filter, VCO
and frequency divider) and output on LLCA (pin7), LLCB
(pin 10), LLC2A (pin 14) and LLC2B (pin 20). The
rectangular output signals have 50% duty factor. Outputs
with equal frequency may be connected together
externally. The clock outputs go HIGH during power-on
reset (and chip enable) to ensure that no output clock
signals are available the PLL has locked-on.

Mode select MS

The LFCO input signal is directly connected to the VCO at
MS = HIGH. The circuit operates as an oscillator and
frequency divider. This function is not tested.

Philips Semiconductors Product specification

Clock Generator Circuit for desktop video systems (CGC) SAA7197

Source select LFCOSEL

Line frequency control signal LFCO (pin 11) is selected by
LFCOSEL = LOW. LFCOSEL = HIGH selects LFCO2
input signal (pin 19). This function is not tested.

Power-on reset

Power-on reset is activated at power-on, when the supply
voltage decreases below 3.5 V (Fig.4) or when chip enable
is done. The indicator output RESN is LOW for a time
determined by capacitor on pin 3. The RESN signal can be

Chip enable CE

The buffer outputs are enabled and RESN set HIGH by
CE = HIGH (Fig.4). CE = LOW sets the clock outputs

applied to reset other circuits of this digital TV system.
The LFCO or LFCO2 input signals have to be applied
before RESN becomes HIGH.

HIGH and RESN output LOW.

CREF output

2 f

output to control the clock dividers of the

LFCO

DMSD-SQP chip family.

PINNING

SYMBOL PIN DESCRIPTION

MS 1 mode select input (LOW = PLL mode)

(1)

CE 2 chip enable /reset (HIGH = outputs enabled)
PORD 3 power-on reset delay, dependent on external

capacitor

V

SSA

V

DDA

V

SSD1

LLCA 7 line-locked clock output signal (4 times f
V

DDD1

V

SSD2

LLCB 10 line-locked clock output signal (4 times f

4 analog ground (0 V)
5 analog supply voltage (+5 V)
6 digital ground 1 (0 V)

LFCO

8 digital supply voltage 1 (+5 V)
9 digital ground 2 (0 V)

LFCO

LFCO 11 line-locked frequency control input signal 1
RESN 12 reset output (active-LOW, Fig.4)
V

SSD3

13 digital ground 3 (0 V)
LLC2A 14 line-locked clock output signal 2A (2 times f
CREF 15 clock reference output, qualifier signal

(2 times f

LFCO

)
LFCOSEL 16 LFCO source select (LOW = LFCO selected)
V
V

DDD2
SSD4

17 digital supply voltage 2 (+5 V)

18 digital ground 4 (0 V)
LFCO2 19 line-locked frequency control input signal 2
LLC2B 20 line-locked clock output signal 2B (2 times f

)

)

LFCO

(1)

LFCO

(1)

PIN CONFIGURATION

halfpage

PORD

V

SSA

V

DDA

V

SSD1

LLCA

V

DDD1

V

SSD2

)

LLCB

)

MS

CE

1
2
3
4
5
6
7
8
9

10

SAA7197

20
19
18
17
16
15
14
13
12
11

MGL505

Fig.2 Pin configuration.

LLC2B
LFCO2

V

SSD4

V

DDD2

LFCOSEL
CREF
LLC2A

V

SSD3
RESIN
LFCO

Note

1. MS and LFCO2 functions are not tested. LFCO2 is a multiple of
horizontal frequency.

August 1996 4

Philips Semiconductors Product specification

Clock Generator Circuit for desktop video systems (CGC) SAA7197

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134);
ground pins as well as supply pins together connected.

SYMBOL PARAMETER MIN. MAX. UNIT

V

DDA

V

DDD

V

diff GND

V

O

P

tot

T

stg

T

amb

V

ESD

Note

1. Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
recommended to take normal handling precautions appropriate to

analog supply voltage (pin 5) −0.5 7.0 V
digital supply voltage (pins 8 and 17) −0.5 7.0 V
difference voltage V
output voltage (IOM= 20 mA) −0.5 V

DDA

− V

DDD

−±100 mV

DDD

V
total power dissipation (DIL20) 0 1.1 W
storage temperature range −65 150 °C
operating ambient temperature range 0 70 °C
electrostatic handling

(1)

for all pins − tbf V

“Handling MOS devices”

.

CHARACTERISTICS

V

DDA=VDDD

= 4.5 to 5.5 V; f

= 5.5 to 8.0 MHz and T

LFCO

= 0 to 70 °C unless otherwise specified.

amb

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DDA

V

DDD

I

DDA

I

DDD

V

reset

analog supply voltage (pin 5) 4.5 5.0 5.5 V
digital supply voltage (pins 8 and 17) 4.5 5.0 5.5 V
analog supply current (pin 5) 3 − 9mA
digital supply current (I8+ I17) note 1 10 − 60 mA

power-on reset threshold voltage Fig.4 − 3.5 - V
Input LFCO (pin 11)
V

11

V

i

f

LFCO

C

11

DC input voltage 0 − V

input signal (peak-to-peak value) 1 − V

DDA
DDA

input frequency range 5.5 − 8.0 MHz

input capacitance −−10 pF
Inputs MS, CE, LFCOSEL and LFCO2 (pins 1, 2, 16 and 19); note 3
V

IL

V

IH

f

LFCO2

I

LI

input voltage LOW 0 − 0.8 V

input voltage HIGH 2.0 − V

DDD

input frequency range for LFCO2 5.5 − 8.0 MHz

input leakage current LFCOSEL 50 − 150 µA

others −− 10 µA

C

I

input capacitance −−5pF
Output RESN (pin 12)
V

OL

V

OH

t

d

output voltage LOW IOL= 2 mA 0 − 0.4 V

output voltage HIGH IOH= −0.5 mA 2.4 − V

DDD

RESN delay time C3= 0.1 µF; Fig.4 20 − 200 ms

V
V

V

V

August 1996 5