Philips SAA7191B Datasheet
INTEGRATED CIRCUITS
DATA SH EET
SAA7191B
Digital Multistandard Colour
Decoder, Square Pixel
(DMSD-SQP)
Product specification
File under Integrated Circuits, IC22
August 1996
Philips Semiconductors Product specification
Digital Multistandard Colour Decoder,
Square Pixel (DMSD-SQP)
CONTENTS
1 FEATURES
2 GENERAL DESCRIPTION
3 QUICK REFERENCE DATA
4 ORDERING INFORMATION
5 BLOCK DIAGRAM
6 PINNING
7 FUNCTIONAL DESCRIPTION
8 LIMITING VALUES
9 CHARACTERISTICS
10 I2C-BUS FORMAT
11 PROGRAMMING EXAMPLE
12 PACKAGE OUTLINE
13 SOLDERING
14 DEFINITIONS
15 LIFE SUPPORT APPLICATIONS
16 PURCHASE OF PHILIPS I2C COMPONENTS
SAA7191B
August 1996 2
Philips Semiconductors Product specification
Digital Multistandard Colour Decoder,
Square Pixel (DMSD-SQP)
1 FEATURES
• Separate 8-bit luminance (Y or CVBS) and 8-bit
chrominance inputs (CVBS or C) from CVBS, Y/C,
S-Video (S-VHS or Hi8) sources
• Luminance and chrominance signal processing for
standards PAL-B/G, NTSC-M, SECAM
• Horizontal and vertical sync detection for all standards
• Real-time control output RTCO to be used for
frequency-locked digital video encoder (SAA7199B).
RTCO contains serialized information about actual clock
frequency, subcarrier frequency and PAL/SECAM
sequence.
2
• Controls via the I
• User programmable aperture correction (horizontal
peaking)
• Compatible with memory-based features (line-locked
clock)
• Cross-colour reduction by chrominance comb-filtering
(NTSC) or by special cross colour cancellation
(SECAM)
• 8-bit quantization of input signals
• 768/640 active samples per line equals 50/60 Hz (SQP)
• The YUV bus supports data rates of 780 × fH equal to
12.2727 MHz for 60 Hz (NTSC-M) and 944 × fH equal to
14.75 MHz for 50 Hz (PAL-B/G, SECAM) in 4 : 1 : 1 or
4:2:2 formats (via the I2C-bus)
• One crystal oscillator of 26.8 MHz
C-bus
SAA7191B
2 GENERAL DESCRIPTION
The SAA7191B is a digital multistandard colour decoder
suitable for 8-bit CVBS input signals or for 8-bit luminance
and 8-bit chrominance input signals (Y/C).
The SAA7191B is down-compatible with SAA7191. The
SAA7191B has additional outputs RTCO, GPSW0 and
ODD. These new outputs are in high-impedance state
when NFEN-bit = 0.
3 QUICK REFERENCE DATA
SYMBOL PARAMETER MIN. TYP. MAX. UNIT
V
DD
I
DD
V
IL
V
OL
T
amb
positive supply voltage (pins 5, 18, 28, 37 and 52) 4.5 5 5.5 V
total supply current (pins 5, 18, 28, 37 and 52) 100 250 mA
input levels TTL-compatible
output levels TTL-compatible
operating ambient temperature 0 - 70 °C
4 ORDERING INFORMATION
EXTENDED TYPE
NUMBER
PINS PIN POSITION MATERIAL CODE
PACKAGE
SAA7191B 68 PLCC plastic SOT188-2
August 1996 3
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August 1996 4
handbook, full pagewidth
+5 V
V to V
DD1 DD4
5, 18. 28, 52 19, 38, 51, 67
V to V
SS1 SS4
PLIN
66
RTCO
68
internally
connected
44 1, 2
test pins
SAA7191B
5 BLOCK DIAGRAM
Digital Multistandard Colour Decoder,
Square Pixel (DMSD-SQP)
Philips Semiconductors Product specification
CVBS7 to
CVBS0
CHR7 to
CHR0
GPSW0
GPSW1
GPSW2
SDA
IICSA
RESN
14 to 17
20 to 23
6 to 13
65
24
25
40
41
INPUT
INTERFACE
LUMINANCE
PROCESSOR
PORT AND
STATUS
REGISTER
2
I C-BUS
CONTROL
43 29
3
clock
status
26 39
HCL HSY VS
CHROMINANCE PROCESSOR
SYNCHRONIZATION
30 31 32
HS
Fig.1 Block diagram.
Fig.1 Block diagram.
HL
36
LFCO
ODD
OUTPUT
INTERFACE
CLOCK
4
CREF27LLC
45 to 50, 53, 54
55 to 62
Y output
(Y7 to Y0)
UV output
(UV7 to UV0)
42
63
64
37
35
33
34
+5 V
HREF
FEON
FEIN
V
DDA
V
SSA
XTAL
XTALI
SAA7191B
MEH435
Philips Semiconductors Product specification
Digital Multistandard Colour Decoder,
SAA7191B
Square Pixel (DMSD-SQP)
6 PINNING
SYMBOL PIN DESCRIPTION
SP 1 connected to ground (shift pin for testing)
AP 2 connected to ground (action pin for testing)
RESN 3 reset, active LOW
CREF 4 clock reference, sync from external to ensure in-phase signals on the YUV-bus
V
DD1
CHR0 6
CHR1 7
CHR2 8
CHR3 9
CHR4 10
CHR5 11
CHR6 12
CHR7 13
CVBS0 14
CVBS1 15
CVBS2 16
CVBS3 17
V
DD2
V
SS1
CVBS4 20
CVBS5 21
CVBS6 22
CVBS7 23
GPSW1 24 Port 1 output for general purpose (programmable)
GPSW2 25 Port 2 output for general purpose (programmable)
HCL 26 black level clamp pulse (programmable), e.g. for TDA8708 (ADC)
LLC 27 line-locked clock input signal (29.5 MHz for 50 Hz system; 24.5454 MHz for 60 Hz system)
V
DD3
HSY 29 horizontal sync indicator output signal (programmable), e.g. for TDA8708 (ADC)
VS 30 vertical sync output signal
HS 31 horizontal sync output signal (programmable)
HL 32 horizontal lock flag, HIGH = PLL locked
XTAL 33 26.8 MHz clock output
XTALI 34 26.8 MHz connection for crystal or external oscillator (TTL compatible squarewave)
V
SSA
LFCO 36 line frequency control output signal, multiple of horizontal frequency (7.375 MHz/6.136363 MHz)
V
DDA
V
SS2
ODD 39 odd/even field identification output (odd = HIGH); active only at NFEN-bit = 1
SDA 40 I
5 +5 V supply input 1
chrominance input data bits CHR7 to CHR0
from a Y/C (VHS, Hi8) source in two’s complement format
luminance respectively CVBS lower input data bits CVBS3 to CVBS0
(CVBS with luminance, chrominance and all sync information in two’s complement format)
18 +5 V supply input 2
19 ground 1 (0 V)
luminance respectively CVBS upper input data bits CVBS7 to CVBS4
(CVBS with luminance, chrominance and all sync information in two’s complement format)
28 +5 V supply input 3
35 analog ground
37 +5 V supply input for analog part
38 ground 2 (0 V)
2
C-bus data line
August 1996 5
Philips Semiconductors Product specification
Digital Multistandard Colour Decoder,
SAA7191B
Square Pixel (DMSD-SQP)
SYMBOL PIN DESCRIPTION
SCL 41 I2C-bus clock line
HREF 42 horizontal reference output for valid YUV data (for active line 768Y or 640Y samples long)
IICSA 43 set module address input (LOW = 1000 101X; HIGH = 1000 111X)
i.c. 44 internally connected
Y7 45
Y6 46
Y5 47
Y4 48
Y3 49
Y2 50
V
SS3
V
DD4
Y1 53
Y0 54
UV7 55
UV6 56
UV5 57
UV4 58
UV3 59
UV2 60
UV1 61
UV0 62
FEON 63 output active flag (active LOW when Y and UV data in high-impedance state)
FEIN 64 fast enable input (active LOW to control fast switching due to YUV data)
GPSW0 65 Port 0 output for general purpose (programmable); active only at NFEN-bit = 1
PLIN 66 PAL flag (active LOW at inverted line); SECAM flag (LOW equals DR, HIGH equals DB line)
V
SS4
RTCO 68 real-time control output active at NFEN-bit = 1; Fig.8
Y signal output bits Y7 to Y2 (luminance), part of the digital YUV-bus
51 ground 3 (0 V)
52 +5 V supply input 4
Y signal output bits Y1 to Y0 (luminance), part of the digital YUV-bus
UV signal output bits UV7 to UV0 (colour-difference), part of the digital YUV-bus
67 ground 4 (0 V)
August 1996 6
Philips Semiconductors Product specification
Digital Multistandard Colour Decoder,
Square Pixel (DMSD-SQP)
6.1 Pin configuration
handbook, full pagewidth
UV6
UV1
UV0
FEON
FEIN
GPSW0
PLIN
V
SS4
RTCO
SP
AP
RESN
UV4
UV5
UV3
UV2
60
61
62
63
64
65
66
67
68
1
2
3
Y0
UV7
54 4950515253
5556575859
DD4VSS3
V
Y1
SAA7191B
Y2
Y3
Y4
Y5
Y6
Y7
SAA7191B
i.c.
4445464748
IICSA
43
HREF
42
41
SCL
SDA
40
39
ODD
V
38
SS2
V
37
DDA
36
LFCO
V
35
SSA
XTALI
34
XTAL
33
CREF
V
DD1
CHR0
CHR1
CHR2
CHR3
4
5
6
7
8
9
11
10 141312
CHR4
CHR5
CHR6
CHR7
15
16 2120191817 25242322
DD2
CVBS0
CVBS1
CVBS2
CVBS3
V
Fig.2 Pin configuration.
V
SS1
CVBS4
CVBS5
CVBS6
CVBS7
GPSW1
26
HCL
GPSW2
32
HL
HS
31
VS
30
HSY
29
V
28
DD3
LLC
27
MEH436
August 1996 7
Philips Semiconductors Product specification
Digital Multistandard Colour Decoder,
Square Pixel (DMSD-SQP)
7 FUNCTIONAL DESCRIPTION
7.1 Chrominance processor
The 8-bit chrominance input signal (CVBS or chrominance
format) passes a bandpass filter to eliminate DC
components and to decimate the sample rate before it is
fed to the two multipliers (quadrature demodulator), Fig.3.
Two subcarrier signals from a local oscillator (0 to 90
degree) are fed to the multiplicator inputs of the multipliers.
The multipliers operate as a quadrature demodulator for all
PAL and NTSC signals; it operates as a frequency
down-mixer for SECAM signals.
The two multiplier output signals are converted to a serial
data stream and applied to three low-pass filter stages,
then to a gain controlled amplifier. A final multiplexed
low-pass filter achieves, together with the preceding
stages, the required bandwidth performance. The signals,
originated from PAL and NTSC, are applied to a
comb-filter. The signals, originated from SECAM, are fed
through a Cloche filter (0 Hz centre frequency), a phase
demodulator and a differentiator to obtain
frequency-demodulated colour-difference signals.The
SECAM signals are fed after de-emphasis to a cross-over
switch, to provide the both serial-transmitted
colour-difference signals. These signals are fed finally to
the output formatter stages and to the output interface.
SAA7191B
August 1996 8
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August 1996 9
handbook, full pagewidth
CVBS (7-0)
CHR (7-0)
RTCO
68
INPUT
INTERFACE
CHROMINANCE
BANDPASS
HUEC
FISE
SECS
NFEN
QUADRATURE
DEMODULATOR
DISCRETE TIME
OSCILLATOR (DTO1)
AND DIVIDER
LOOP
FILTER
PI1
LOWPASS
FILTER
FISECHRSBYPS
CKTS (4-0)
CHCV (7-0)
CKTO (4-0)
LFIS (1-0)
SECS
GAIN
CONTROLLED
AMPLIFIER
LOOP
FILTER
PI2
BURST GATE
ACCUMULATOR
CODE
LOWPASS
FILTER
CLOCHE
FILTER
PHASE
DEMODULATOR
AND
AMPLITUDE
DETECTOR
QUAM COMB
FILTERS AND
SECAM
RECOMBINATION
SECS
HRMV
OUTPUT
FORMATTER
AND OUTPUT
INTERFACE
OFTS
COLO
OEDY
OEDC
OEHS
42
63
64
UV (7-0)
HREF
FEON
FEIN
Y (7-0)
Philips Semiconductors Product specification
Digital Multistandard Colour Decoder,
Square Pixel (DMSD-SQP)
PLIN
66
SAA7191B
PROCESSOR
PLSE(7-0)
SESE(7-0)
FISE
SECS
SEQUENCE
SEQA
DIFFERENTIATOR
SXCR
CHROMINANCE
DE-EMPHASIS
to luminance from luminance
Fig.3 Detailed block diagram; continued in Fig.4.
Fig.3(a) Detailed block diagram; continued in Fig.3(b).
SAA7191B
MEH437
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August 1996 10
from input interface
handbook, full pagewidth
to output interface
Philips Semiconductors Product specification
Digital Multistandard Colour Decoder,
Square Pixel (DMSD-SQP)
RESN
SCL
SDA
IICSA
SAMPLE RATE
CONVERTER
PREFILTER
SYNC
3
41
40
43
SAA7191B
2
I C-BUS
CONTROL
65,24,25
PREFILTER
PREF
SYNC SLICER
NFEN
LUMINANCE
PHASE DETECTOR
SYNC
CHROMINANCE
TRAP
BYPS
FISE
FINE
HRMV
HCLB (7-0)
SCEN
HCLS (7-0)
OEVS
HSYB (7-0)
OEHS
HSYS (7-0)
FISE
HPHI (7-0)
IDEL (7-0)
COUNTER
26 29 30 31 32
PHASE DETECTOR
VTRC
FISE
VARIABLE
BANDPASS
BPSS
(1-0)
COARSE
FILTER
PREF
BYPS
HLCK
STTC
VERTICAL
PROCESSOR
39
CORING
CORI (1-0)
MATCHING
AMPLIFIER
LOOP FILTER
HLCK
VTRC
HPLL
FISE
FISE
FIDT
VNOI (1-0)
HLCK
VTRC
FSEL
AUFD
NFEN
FISE
PROGRAMMABLE
DISCRETE TIME
OSCILLATOR
FISE
WEIGHTING
AND
ADDING STAGE
APER
(0-1)
DELAY
(DTO2)
DAC
36
internal clocks
VARIABLE DELAY
COMPENSATION
YDEL
(2-0)
LINE-LOCKED
CLOCK
GENERATOR
CRYSTAL
CLOCK
GENERATOR
4
CREF
27
LLC
33
XTAL
34
XTAL I
SAA7191B
GPSW(2-0)
HS
HCL
Fig.4 Detailed block diagram; continued from Fig.3.
Fig.3(b) Detailed block diagram; continued from Fig.3(a).
VSHSY
HL
ODD
LFCO
MEH438-1
Philips Semiconductors Product specification
Digital Multistandard Colour Decoder,
Square Pixel (DMSD-SQP)
7.2 Luminance processor
The luminance input signal, a digital CVBS format or an
8-bit luminance format (S-VHS, Hi8), is fed through a
sample rate converter to reduce the data rate to
14.75 MHz for PAL and SECAM (12.2727 MHz for NTSC),
Fig.4.
Sample rate is converted by means of a switchable
pre-filter. High frequency components are emphasized to
compensate for loss in the following chrominance trap
filter. This chrominance trap filter (fo= 4.43 MHz or
= 3.58 MHz centre frequency selectable) eliminates
f
o
most of the colour carrier signal, therefore, it must be
by-passed for S-Video (S-VHS and Hi8) signals.
The high frequency components of the luminance signal
can be “peaked” (control for sharpness improvement via
the I2C-bus) in two bandpass filters with selectable transfer
characteristic.
A coring circuit with selectable characteristic improves the
signal once more, this signal is then added to the original
(“unpeaked”) signal. A switchable amplifier achieves a
common DC amplification, because the DC gains are
different in both chrominance trap modes. The improved
luminance signal is fed to the variable delay
compensation.
7.3 Processing delay
The delay from input to output is 220 LLC cycles if YDEL
is set to 0. The processing delay will be influenced in future
enhancements.
7.4 Synchronization
SAA7191B
Table 1 Clock frequencies in MHz for 50/60 Hz systems
CLOCK 50 Hz 60 Hz
LLC 29.5 24.545454
LLC2 14.75 12.272727
LLC4 7.375 6.136136
LLC8 3.6875 3.068181
7.5 Line locked clock frequency
LFCO is required in an external PLL (SAA7197) to
generate the line locked clock frequency.
7.6 YUV-bus, digital outputs
The 16-bit YUV-bus transfers digital data from the output
interfaces to a feature box, or to the digital-to-analog
converter (DAC). Outputs are controlled via the I2C-bus in
normal selections, or they are controlled by output enable
chain (FEIN on pin 64, Fig.5). The YUV-bus data rate
equals LLC2 in Table 1. Timing is achieved by marking
each second positive rising edge of the clock LLC in
conjunction with CREF (clock reference).
YUV-bus formats 4:2:2 and 4:1:1
The output signals Y7 to Y0 are the bits of the digital
luminance signal. The output signals UV7 to UV0 are the
bits of the multiplexed colour-difference signals (B−Y) and
(R−Y). The frame in the following tables is the time,
required to transfer a full set of samples. In case of 4 :2:2
format two luminance samples are transmitted in
comparison to one U and one V sample within one frame.
The luminance output signal is fed to the synchronization
stage. Its bandwidth is reduced to 1 MHz in a low-pass
filter. The sync pulses are sliced and fed to the phase
detectors to be compared with the sub-divided clock
frequency.
The resulting output signal is applied to the loop filter to
accumulate all phase deviations. Adjustable output signals
(e. g. HCL and HSY) are generated according to peripheral
requirements (TDA8708A, TDA8709A). The output signals
HS, VS and PLIN are locked to the timing reference signal
HREF (Figures 7 and 8). There is no absolute timing
reference guaranteed between the input signal and the
HREF signal as further improvements to the circuit may
change the total processing delay. It is therefore not
recommended to use them for applications, which ask for
absolute timing accuracy to the input signals.
The loop filter signal drives an oscillator to generate the
line frequency control output signal LFCO.
August 1996 11
Philips Semiconductors Product specification
Digital Multistandard Colour Decoder,
Square Pixel (DMSD-SQP)
Table 2 4 : 2 : 2 format
(768 pixels per line for 50 Hz system; 640 pixels
per line for 60 Hz system)
OUTPUT PIXEL BYTE SEQUENCE
Y0 (LSB)
Y1
Y2
Y3
Y4
Y5
Y6
Y7 (MSB)
UV0 (LSB)
UV1
UV2
UV3
UV4
UV5
UV6
UV7(MSB)
Y frame 0 1 2 3 4 5
UV frame 0 2 4
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
U0
U1
U2
U3
U4
U5
U6
U7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
V0
V1
V2
V3
V4
V5
V6
V7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
U0
U1
U2
U3
U4
U5
U6
U7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
V0
V1
V2
V3
V4
V5
V6
V7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
U0
U1
U2
U3
U4
U5
U6
U7
SAA7191B
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
V0
V1
V2
V3
V4
V5
V6
V7
Notes
1. Data rate: LLC2
2. Sample frequency:
Y LLC2
U LLC4
V LLC4
The quoted frequencies are valid on the YUV-bus.
The time frames are controlled by the HREF signal.
August 1996 12
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