Philips SAA7186 Datasheet
INTEGRATED CIRCUITS
DATA SH EET
SAA7186
Digital video scaler
Preliminary specification
File under Integrated Circuits, IC22
May 1993
Philips Semiconductors Preliminary specification
Digital video scaler SAA7186
CONTENTS
1 FEATURES
2 GENERAL DESCRIPTION
3 QUICK REFERENCE DATA
4 ORDERING INFORMATION
5 BLOCK DIAGRAM
6 PINNING
7 FUNCTIONAL DESCRIPTION
8 OPERATION CYCLE
9I
10 LIMITING VALUES
11 DC CHARACTERISTICS
12 AC CHARACTERISTICS
13 PROCESSING DELAYS
14 PROGRAMMING EXAMPLE
15 PACKAGE OUTLINE
16 SOLDERING
17 DEFINITIONS
18 LIFE SUPPORT APPLICATIONS
19 PURCHASE OF PHILIPS I2C COMPONENTS
2
C-BUS FORMAT
May 1993 2
Philips Semiconductors Preliminary specification
Digital video scaler SAA7186
1 FEATURES
• Scaling of video picture windows down to randomly
sized windows
• Processes maximum 1023 pixels per line and 1023 lines
per field
• Two-dimensional data processing for improved signal
quality of scaled video data and for compression of
video data
• 16-bit YUV input data buffer
• Interlace/non-interlace video data processing and field
control
• Line memories in Y path and UV path to store two lines,
each with 2 × 768 × 8 bit capacity
• Vertical sync processing by scale control
• Non-scaled mode to get full picture or to gate videotext
lines
• UV input and output data binary/two’s complement
• Switchable RGB matrix and anti-gamma ROMs
• 16-word FIFO register for 32-bit output data
• Output formats: 5-bit and 8-bit RGB, 8-bit YUV or 8-bit
monochrome
2 GENERAL DESCRIPTION
The CMOS circuit SAA7186 scales and filters digital video
data to randomly sized picture windows. YUV input data in
4:2:2 format are required (SAA7191B source).
3 QUICK REFERENCE DATA
SYMBOL PARAMETER MIN. TYP. MAX. UNIT
V
DD
I
DD tot
V
I
V
O
supply voltage 4.5 5 5.5 V
total supply current (inputs LOW, without output load) - - 180 mA
data input level TTL-compatible
data output level TTL-compatible
LLC input clock frequency - - 32 MHz
T
amb
operating ambient temperature range 0 - 70 °C
4 ORDERING INFORMATION
EXTENDED TYPE
NUMBER
PINS PIN POSITION MATERIAL CODE
PACKAGE
SAA7186 100 QFP plastic SOT317-2
May 1993 3
Philips Semiconductors Preliminary specification
Digital video scaler SAA7186
5 BLOCK DIAGRAM
HFL
port output
RGB or YUV
48
REGISTER
15
CHROMA
U
INCADR
49
56 to 64
68 to 75, 77
output pins (1):
KEYER
V
INTERPOLATOR
1
80 to 88
92 to 100
LNQ
HREFD
2
n.c.
4, 6,
i.c.
54, 60, 66, 72, 79, 84, 90, 96
9, 15, 21, 27, 29, 39, 34, 41, 52,
3, 16, 28, 42,
SS8
to V
SS1
V
53, 65, 78, 89
SAA7186
8
AP
MEH422-1
DD8
V
to
DD1
5, 14, 26,40,
V
handbook, full pagewidth
+5 V
BTST
VOEN
VLCK
50
47
51
8
RGB
MATRIX
Y
55, 67, 76, 91
VRO (31 to 0);
OUTPUT
OUTPUT
FORMATTER
8
8
BY
FOLLOWED
ANTI-GAMMA
V
U
32-bit VRAM
FIFO
ROMs
ARITHMETIC
LINE
VERTICAL FILTER
(2x8x768)
MEMORY
FILTER
LUMINANCE
DECIMATION
Y
33
25
to 22
to 30
YIN
(7-0)
VERTICAL FILTER
DATA
INPUT
BUFFER
20
LINE
MEMORY
CHROMA
DECIMATION
UV
13
to 10
to 17
UVIN
(7-0)
ARITHMETIC
(2x8x768)
FILTER
SCALE CONTROL
37
38
HREF
VS
43
RESN
controls
2
I C
45
SCL
CLOCK
7
363546
GENERATION
status
CONTROL
44
SDA
SP
IICSA
CREF
LLC
(1) without pins 60, 72, 84 and 96,
these pins are not connected
Fig.1 Block diagram.
Fig.1 Block diagram.
May 1993 4
Philips Semiconductors Preliminary specification
Digital video scaler SAA7186
6 PINNING
SYMBOL PIN STATUS DESCRIPTION
LNQ 1 O line qualifier signal; active polarity defined by QPL-bit in “10” (VCLK strobed)
HREFD 2 O delay-compensated HREF output signal (VCLK strobed)
V
SS1
i.c. 4 − internally connected
V
DD1
i.c. 6 − internally connected
SP 7 I connected to ground (shift pin for testing)
AP 8 I connected to ground (action pin for testing)
n.c. 9 − not connected
UVIN0 10 I
UVIN1 11 I
UVIN2 12 I
UVIN3 13 I
V
DD2
n.c. 15 − not connected
V
SS2
UVIN4 17 I
UVIN5 18 I
UVIN6 19 I
UVIN7 20 I
n.c. 21 − not connected
YIN0 22 I
YIN1 23 I
YIN2 24 I
YIN3 25 I
V
DD3
n.c. 27 − not connected
V
SS3
n.c. 29 − not connected
YIN4 30 I
YIN5 31 I
YIN6 32 I
YIN7 33 I
n.c. 34 − not connected
CREF 35 I clock reference, external sync signal
LLC 36 I line-locked system clock input signal (twice of pixel rate)
HREF 37 I horizontal reference, pixel data clock signal (also present during vertical blanking)
VS 38 I vertical sync input signal (approximately 6 lines long)
n.c. 39 − not connected
V
DD4
3 − GND1 (0 V)
5 − +5 V supply voltage 1
time-multiplexed colour-difference input data (bits 0 to 3)
14 − +5 V supply voltage 2
16 − GND2 (0 V)
time-multiplexed colour-difference input data (bits 4 to 7)
luminance input data (bits 0 to 3)
26 − +5 V supply voltage 3
28 − GND3 (0 V)
luminance input data (bits 4 to 7)
40 − +5 V supply voltage 4
May 1993 5
Philips Semiconductors Preliminary specification
Digital video scaler SAA7186
SYMBOL PIN STATUS DESCRIPTION
n.c. 41 − not connected
V
SS4
RESN 43 I reset input (active-LOW for at least 30LLC periods)
SDA 44 I/O IIC-bus data line
SCL 45 I IIC-bus clock line
IICSA 46 I set module address input of IIC-bus (LOW = B8, HIGH = BC)
BTST 47 I output disable input; HIGH sets all data outputs to high-impedance state
INCADR 48 O line increment / vertical reset control output line
HFL 49 O FIFO register half-full flag output
VOEN 50 I VRAM port output enable input (active-LOW)
VCLK 51 I FIFO register clock input signal
n.c. 52 − not connected
V
SS5
n.c. 54 − not connected
V
DD5
VRO31 56 O
VRO30 57 O
VRO29 58 O
VRO28 59 O
n.c. 60 − not connected
VRO27 61 O
VRO26 62 O
VRO25 63 O
VRO24 64 O
V
SS6
n.c. 66 − not connected
V
DD6
VRO23 68 O
VRO22 69 O
VRO21 70 O
VRO20 71 O
n.c. 72 − not connected
VRO19 73 O
VRO17 75 O
V
DD7
VRO16 77 O video output; 32-bit VRAM output port (bit16)
V
SS7
n.c. 79 − not connected
42 − GND4 (0 V)
53 − GND5 (0 V)
55 − +5 V supply voltage 5
video output; 32-bit VRAM output port (bits 31 to 28)
video output; 32-bit VRAM output port (bits 27 to 24)
65 − GND6 (0 V)
67 − +5 V supply voltage 6
video output; 32-bit VRAM output port (bits 23 to 22)
video output; 32-bit VRAM output port (bits 21 to 20)
video output; 32-bit VRAM output port (bits 19 to 17)VRO18 74 O
76 − +5 V supply voltage 7
78 − GND7 (0 V)
May 1993 6
Philips Semiconductors Preliminary specification
Digital video scaler SAA7186
SYMBOL PIN STATUS DESCRIPTION
VRO15 80 O
VRO14 81 O
VRO13 82 O
VRO12 83 O
n.c. 84 − not connected
VRO11 85 O
VRO10 86 O
VRO9 87 O
VRO8 88 O
V
SS8
n.c. 90 − not connected
V
DD8
VRO7 92 O
VRO6 93 O
VRO5 94 O
VRO4 95 O
n.c. 96 − not connected
VRO3 97 O
VRO2 98 O
VRO1 99 O
VRO0 100 O
89 O GND8 (0 V)
91 − +5 V supply voltage 8
video output; 32-bit VRAM output port (bits 15 to 12)
video output; 32-bit VRAM output port (bits 11 to 8)
video output; 32-bit VRAM output port (bits 7 to 4)
video output; 32-bit VRAM output port (bits 3 to 0)
May 1993 7
Philips Semiconductors Preliminary specification
Digital video scaler SAA7186
6.1 Pin configuration
handbook, full pagewidth
SS8
DD8
VRO7
92
n.c.
V
VRO9
V
91
VRO8
88
90
87
89
VRO10
VRO11
85
86
n.c.
84
VRO12
83
VRO13
VRO14
81
82
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VRO15
n.c.
V
SS7
VRO16
V
DD7
VRO17
VRO18
VRO19
n.c.
VRO20
VRO21
VRO22
VRO23
V
DD6
n.c.
V
SS6
VRO24
VRO25
VRO26
VRO27
n.c.
VRO28
VRO29
VRO30
VRO31
V
DD5
n.c.
V
SS5
n.c.
VCLK
LNQ
HREFD.
V
SS1
i.c.
V
DD1
i.c.
SP.
AP
n.c.
UVIN0
UVIN1
UVIN2
UVIN3
V
DD2
n.c.
V
SS2
UVIN4
UVIN5
UVIN6
UVIN7
n.c.
YIN0
YIN1
YIN2
YIN3
V
DD3
n.c.
V
SS3
n.c.
YIN4
VRO0
99
100
VRO1
VRO2
98
VRO3
97
n.c.
96
VRO4
95
VRO5
94
VRO6
93
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SAA7186
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
YIN5
32
YIN6
33
YIN7
34
n.c.
35
CREF
36
LLC
37
HREF
40
39
38
DD4VSS4
n.c.
V
VS
Fig.2 Pin configuration.
May 1993 8
41
n.c.
47
BTST
49
48
HFL
INCADR
VOEN
MEH421
45
46
44
43
42
RESN
SDA
SCL
IICSA
50
Philips Semiconductors Preliminary specification
Digital video scaler SAA7186
7 FUNCTIONAL DESCRIPTION
The input port is output of Philips digital video
multistandard decoders (SAA7151B, SAA7191B) or other
similar sources.
The SAA7186 input supports the 16-bit YUV 4:2:2 format.
The video data from the input port are converted into a
unique internal two’s complement data stream and are
processed in horizontal direction in two separate
decimation filters. Then they are processed in vertical
direction by the vertical processing unit (VPU).
Chrominance data are interpolated to a 4:4:4 format; a
chroma keying bit is generated.
The 4:4:4 YUV data are then converted from the YUV to
the RGB domain in a digital matrix. ROM tables in the RGB
data path can be used for anti-gamma correction of
gamma-corrected input signals.
Uncorrected RGB and YUV signals can be bypassed.
A scale control unit generates reference and gate signals
for scaling of the processed video data. After data
formatting to the various VRAM port formats, the scaled
video data are buffered in the 16 word× 32-bit output FIFO
register. The FIFO output is directly connected to the
VRAM output bus VRO(31-0). Specific reference signals
support an easy memory interfacing.
All functions of the SAA7186 are controlled via I2C-bus
using 17 subaddresses. The external microcontroller can
get information by reading the status register.
7.1 Video input port
The 16-bit YUV input data in 4:2:2 format (Table 1) consist
of 8-bit luminance data Y (pins YIN(7-0)) and 8-bit
time-multiplexed colour-difference data UV (pins
UVIN(7-0)).
The input data are clocked in by the signals LLC and
CREF (Fig.3). HREF and VS inputs define the video scan
pattern (window).
Sequential input data
• are limited to maximum 768 active pixels per line if the
vertical filter is active
• UV can be processed in straight binary and two’s
complement representation (controlled by TCC)
7.2 Decimation filters
The decimation filters perform accurate horizontal filtering
of the input data stream.
Signal characteristics are matched in front of the pixel
decimation stage, thus disturbing artifacts, caused by the
pixel dropping, are reduced. The signal bandwidth can be
reduced in steps of:
2-tap filter = −6 dB at 0.325 pixel rate
3-tap filter = −6 dB at 0.25 pixel rate
4-tap filter = −6 dB at 0.21 pixel rate
5-tap filter = −6 dB at 0.125 pixel rate
9-tap filter = −6 dB at 0.075 pixel rate
The different characteristics are chosen dependent on the
defined scaling parameters in an adaptive filter mode
(AFS-bit = 1).
The filter characteristics can also be selected
independently by control bits HF2 to HF0 at AFS-bit = 0.
7.3 Vertical filters
Y and UV data are handled in separate filters (Fig.1). Each
of the two line memories has a capacity of 2 × 768 × 8-bit.
Thus two complete video lines of 4:2:2 YUV data can be
stored. The VPU is split into two memory banks and one
arithmetic unit. The available processing modes,
respectively transfer functions, are selectable by the bits
VP1 and VP0 if AFS = 0.
An adaptive mode is selected by AFS = 1. Disturbing
artifacts, generated by line dropping, are reduced.
Adaptive filter selection (AFS = 1):
SCALING RATIO
XD/XS horizontal
≤1
≤14/15
≤11/15
≤7/15
≤3/15
YD/YS vertical
≤1
≤13/15
≤4/15
bypassed
filter 1
filter 6
filter 3
filter 4
bypassed
filter 1
filter 2
FILTER FUNCTION
(REFER TO I
2
C SECTION)
May 1993 9
Philips Semiconductors Preliminary specification
Digital video scaler SAA7186
7.4 RGB matrix
Y data and UV data are converted after interpolation into
RGB data according to CCIR601 recommendation. Data
are bypassed in YUV or monochrome modes.
Table 1 4 : 2 : 2 format (pixels per line). The time frames
are controlled by the HREF signal.
INPUT PIXEL BYTE SEQUENCE
YIN7
YIN6
YIN5
YIN4
YIN3
YIN2
YIN1
YIN0
UVIN7
UVIN6
UVIN5
UVIN4
UVIN3
UVIN2
UVIN1
UVIN0
Y frame 0 1 2 3 4
UV frame 0 2 4
Note
1. e = even pixel; o = odd pixel
The matrix equations are these considering the digital
quantization:
R=Y+1.375 V
G=Y− 0.703125 V − 0.34375 U
B=Y+1.734375 U.
Anti-gamma ROM tables:
ROM tables are implemented at the matrix output to
provide anti-gamma correction of the RGB data. A curve
for a gamma of 1.4 is implemented
The tables can be used (RTB-bit = 0) to compensate
gamma correction for linear data representation of RGB
output data.
Ye7
Ye6
Ye5
Ye4
Ye3
Ye2
Ye1
Ye0
Ue7
Ue6
Ue5
Ue4
Ue3
Ue2
Ue1
Ue0
Yo7
Yo6
Yo5
Yo4
Yo3
Yo2
Yo1
Yo0
Ve7
Ve6
Ve5
Ve4
Ve3
Ve2
Ve1
Ve0
Ye7
Ye6
Ye5
Ye4
Ye3
Ye2
Ye1
Ye0
Ue7
Ue6
Ue5
Ue4
Ue3
Ue2
Ue1
Ue0
Yo7
Yo6
Yo5
Yo4
Yo3
Yo2
Yo1
Yo0
Ve7
Ve6
Ve5
Ve4
Ve3
Ve2
Ve1
Ve0
Ye7
Ye6
Ye5
Ye4
Ye3
Ye2
Ye1
Ye0
Ue7
Ue6
Ue5
Ue4
Ue3
Ue2
Ue1
Ue0
7.5 Chrominance signal keyer
The keyer generates an alpha signal to achieve a 5-5-5 +α
RGB alpha output signal. Therefore, the processed UV
data amplitudes are compared with thresholds set via
I2C-bus (subaddresses ”0C to 0F”). A logical “1” signal is
generated if the amplitude is inside the specified amplitude
range, otherwise a logical “0” is generated.
Keying can be switched off by setting the lower limit higher
than the upper limit (“0C or 0E” and “0D or 0F”).
7.6 Scale control and vertical regions
The scale control block SC includes vertical
address/sequence counters to define the current position
in the input field and to address the internal VPU
memories.
To perform scaling, XD of XS pixel selection in horizontal
direction and YD of YS line selection in vertical direction
are applied. The pixel and line dropping are controlled at
the input of the FIFO register. To control the decimation
filter function and the vertical data processing in the
adaptive mode (AFS = 1), the scaling ratio in horizontal
and vertical direction is estimated in the SC block.
The input field can be divided into two vertical regions
− the bypass region and the scaling region, which are
defined via I
YS.
Vertical bypass region:
Data are not scaled and independent of I2C-bits FS1, FS0
the output format is always 8-bit greyscale (monochrome).
The SAA7186 outputs all active pixels of a line, defined by
the HREF input signal if the vertical bypass region is
active. This can be used, for example, to store videotext
information in the field memory.
The start line of the bypass region is defined by VS; the
number of lines to be bypassed is defined by VC.
Vertical scaling region:
Data is scaled with start at line YO and the output format
is selected when FS1, FS0 are valid.
This is the “normal operation” area.
The input/output screen dimensions in horizontal and
vertical direction are defined by the parameters
XO, XS and XD for horizontal
2
C-bus by the parameters VS, VC, YO and
May 1993 10
YO, YS and YD for vertical.
The circuit processes XS samples of a line. Remaining
pixels are ignored if a line is longer than XS. If a line is
Philips Semiconductors Preliminary specification
Digital video scaler SAA7186
shorter than XS, processing is aborted when the falling
edge of HREF is detected.
Vertical regions in Fig.4:
• the two regions can be programmed via I2C-bus,
whereby regions should not overlap (active region
overrides the bypass region).
• the start of a normal active picture depends on video
standard and has to be programmed to the correct
value.
handbook, full pagewidth
Byte numbers for pixles:
Y signal
LLC
CREF
HREF
0
start of
active line
1
• the offsets XO and YO have to be set according to the
internal processing delays to ensure the complete
number of destination pixels and lines (Table 6).
• the scaling parameters can be used to perform a
panning function over the video frame/field.
2
3
4
5
6
7
U and V signal
handbook, full pagewidth
Byte number for pixels:
LLC
CREF
HREF
Y signal
U and V signal
n – 5
Un-5
U0
n – 4
Vn-5
V0
n – 3
Un-3
U2
n – 2
Vn-3
V2
n – 1
Un-1
end of
active line
Fig.3 Horizontal and data multiplex timing.
U4
n
Vn-1
V4
U6
V6
MEH411
MEH410
May 1993 11
Philips Semiconductors Preliminary specification
Digital video scaler SAA7186
7.7 Output data representation and levels
Output data representation of the YUV data can be
modified by bit MCT (subaddress 10).
The DC gain is 1 for YUV input data. The corresponding
RGB levels are defined by the matrix equations. The
luminance levels are limited according to CCIR 601
16 (239) = black
235 (20) = white
(..) = greyscale luminance levels
if the YUV or monochrome luminance output formats are
selected.
handbook, full pagewidth
vertical sync
vertical bypass start
VS
bypass region
The signal levels of the RGB formats are limited in 8-bit to
“0” or “255”. For the 5-bit RGB formats a truncation from
8-bit to 5-bit is implemented.
Fill values are inserted dependent on longword position
and destination size:
• “0” in RGB formats and for Y two’s complement U, V
• “128” for U, V (straight binary)
• “255” in 8-bit greyscale format
The unused output values of the YUV and greyscale
formats can be used for other purposes.
vertical
blanking
YO
first valid line
vertical bypass count
equals VS
scaling region start
scaling region
Fig.4 Vertical regions.
scaling region count
equals YS Y-size source
MEH357-1
May 1993 12
Philips Semiconductors Preliminary specification
Digital video scaler SAA7186
Table 2 VRAM port output data formats at EFE-bit = 0 dependent on FS1 and FS0 bits (set via I2C-bus)
PIXEL
OUTPUT
BITS
PIXEL
ORDER n n+2n+4n n+2n+4n n+1n+2
VRO31
VRO30
VRO29
VRO28
VRO27
VRO26
VRO25
VRO24
VRO23
VRO22
VRO21
VRO20
VRO19
VRO18
VRO17
VRO16
PIXEL
ORDER n+1n+3n+5n+1n+3n+5 OUTPUTS NOT USED
VRO15
VRO14
VRO13
VRO12
VRO11
VRO10
VRO9
VRO8
VRO7
VRO6
VRO5
VRO4
VRO3
VRO2
VRO1
VRO0
FS1 = 0; FS0 = 0
RGB 5-5-5 + 1
32-BIT WORDS
α
R4
R3
R2
R1
R0
G4
G3
G2
G1
G0
B4
B3
B2
B1
B0
α
R4
R3
R2
R1
R0
G4
G3
G2
G1
G0
B4
B3
B2
B1
B0
α
R4
R3
R2
R1
R0
G4
G3
G2
G1
G0
B4
B3
B2
B1
B0
α
R4
R3
R2
R1
R0
G4
G3
G2
G1
G0
B4
B3
B2
B1
B0
α
R4
R3
R2
R1
R0
G4
G3
G2
G1
G0
B4
B3
B2
B1
B0
α
R4
R3
R2
R1
R0
G4
G3
G2
G1
G0
B4
B3
B2
B1
B0
FS1 = 0; FS0 = 1
YUV 4:2:2
32-BIT WORDS
Ye7
Ye6
Ye5
Ye4
Ye3
Ye2
Ye1
Ye0
Ue7
Ue6
Ue5
Ue4
Ue3
Ue2
Ue1
Ue0
Yo7
Yo6
Yo5
Yo4
Yo3
Yo2
Yo1
Yo0
Ve7
Ve6
Ve5
Ve4
Ve3
Ve2
Ve1
Ve0
Ye7
Ye6
Ye5
Ye4
Ye3
Ye2
Ye1
Ye0
Ue7
Ue6
Ue5
Ue4
Ue3
Ue2
Ue1
Ue0
Yo7
Yo6
Yo5
Yo4
Yo3
Yo2
Yo1
Yo0
Ve7
Ve6
Ve5
Ve4
Ve3
Ve2
Ve1
Ve0
Ye7
Ye6
Ye5
Ye4
Ye3
Ye2
Ye1
Ye0
Ue7
Ue6
Ue5
Ue4
Ue3
Ue2
Ue1
Ue0
Yo7
Yo6
Yo5
Yo4
Yo3
Yo2
Yo1
Yo0
Ve7
Ve6
Ve5
Ve4
Ve3
Ve2
Ve1
Ve0
FS1 = 1; FS0 = 0
YUV 4:2:2 TEST
16-BIT WORDS
Ye7
Ye6
Ye5
Ye4
Ye3
Ye2
Ye1
Ye0
Ue7
Ue6
Ue5
Ue4
Ue3
Ue2
Ue1
Ue0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Yo7
Yo6
Yo5
Yo4
Yo3
Yo2
Yo1
Yo0
Ve7
Ve6
Ve5
Ve4
Ve3
Ve2
Ve1
Ve0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Ye7
Ye6
Ye5
Ye4
Ye3
Ye2
Ye1
Ye0
Ue7
Ue6
Ue5
Ue4
Ue3
Ue2
Ue1
Ue0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
FS1 = 1; FS0 = 1
8-BIT MONOCHROME
32-BIT WORDS
n
n+1
Ya7
Ya6
Ya5
Ya4
Ya3
Ya2
Ya1
Ya0
Yb7
Yb6
Yb5
Yb4
Yb3
Yb2
Yb1
Yb0
n+2
n+3
Yc7
Yc6
Yc5
Yc4
Yc3
Yc2
Yc1
Yc0
Yd7
Yd6
Yd5
Yd4
Yd3
Yd2
Yd1
Yd0
n+4
n+5
Ya7
Ya6
Ya5
Ya4
Ya3
Ya2
Ya1
Ya0
Yb7
Yb6
Yb5
Yb4
Yb3
Yb2
Yb1
Yb0
n+6
n+7
Yc7
Yc6
Yc5
Yc4
Yc3
Yc2
Yc1
Yc0
Yd7
Yd6
Yd5
Yd4
Yd3
Yd2
Yd1
Yd0
n+8
n+9
Ya7
Ya6
Ya5
Ya4
Ya3
Ya2
Ya1
Ya0
Yb7
Yb6
Yb5
Yb4
Yb3
Yb2
Yb1
Yb0
n+10
n+11
Yc7
Yc6
Yc5
Yc4
Yc3
Yc2
Yc1
Yc0
Yd7
Yd6
Yd5
Yd4
Yd3
Yd2
Yd1
Yd0
Note
1. α = keying bit; R, G, B, Y, U and V = digital signals; e = even pixel number; o = odd pixel number;
a b c d = consecutive pixels
May 1993 13
Philips Semiconductors Preliminary specification
Digital video scaler SAA7186
Table 3 VRAM port output data formats at EFE-bit = 1 dependent on FS1 and FS0 bits (set via I2C-bus)
PIXEL
OUTPUT
BITS
PIXEL
ORDER n n+1n+2n n+1n+2n n+1n+2
VRO31
VRO30
VRO29
VRO28
VRO27
VRO26
VRO25
VRO24
VRO23
VRO22
VRO21
VRO20
VRO19
VRO18
VRO17
VRO16
PIXEL
ORDER n n+1n+2n n+1n+2n n+1n+2
VRO15
VRO14
VRO13
VRO12
VRO11
VRO10
VRO9
VRO8
VRO7 (2, 3)
VRO6 (3)
VRO5 (3)
VRO4 (3)
VRO3
VRO2 (3)
VRO1 (3)
VRO0 (3)
FS1 = 0; FS0 = 0
RGB 5-5-5 + 1
16-BIT WORDS
α
R4
R3
R2
R1
R0
G4
G3
G2
G1
G0
B4
B3
B2
B1
B0
X
X
X
X
X
X
X
X
α
O/E
VGT
HGT
X
HRF
LNQ
PXQ
α
R4
R3
R2
R1
R0
G4
G3
G2
G1
G0
B4
B3
B2
B1
B0
X
X
X
X
X
X
X
X
α
O/E
VGT
HGT
X
HRF
LNQ
PXQ
α
R4
R3
R2
R1
R0
G4
G3
G2
G1
G0
B4
B3
B2
B1
B0
X
X
X
X
X
X
X
X
α
O/E
VGT
HGT
X
HRF
LNQ
PXQ
FS1 = 0; FS0 = 1
YUV 4:2:2
16-BIT WORDS
Ye7
Ye6
Ye5
Ye4
Ye3
Ye2
Ye1
Ye0
Ue7
Ue6
Ue5
Ue4
Ue3
Ue2
Ue1
Ue0
X
X
X
X
X
X
X
X
α
O/E
VGT
HGT
X
HRF
LNQ
PXQ
Yo7
Yo6
Yo5
Yo4
Yo3
Yo2
Yo1
Yo0
Ve7
Ve6
Ve5
Ve4
Ve3
Ve2
Ve1
Ve0
X
X
X
X
X
X
X
X
X
O/E
VGT
HGT
X
HRF
LNQ
PXQ
Ye7
Ye6
Ye5
Ye4
Ye3
Ye2
Ye1
Ye0
Ue7
Ue6
Ue5
Ue4
Ue3
Ue2
Ue1
Ue0
X
X
X
X
X
X
X
X
α
O/E
VGT
HGT
X
HRF
LNQ
PXQ
FS1 = 1; FS0 = 0
RGB 8-8-8
24-BIT WORDS
R7
R6
R5
R4
R3
R2
R1
R0
G7
G6
G5
G4
G3
G2
G1
G0
B7
B6
B5
B4
B3
B2
B1
B0
α
O/E
VGT
HGT
X
HRF
LNQ
PXQ
R7
R6
R5
R4
R3
R2
R1
R0
G7
G6
G5
G4
G3
G2
G1
G0
B7
B6
B5
B4
B3
B2
B1
B0
α
O/E
VGT
HGT
X
HRF
LNQ
PXQ
R7
R6
R5
R4
R3
R2
R1
R0
G7
G6
G5
G4
G3
G2
G1
G0
B7
B6
B5
B4
B3
B2
B1
B0
α
O/E
VGT
HGT
X
HRF
LNQ
PXQ
FS1 = 1; FS0 = 1
8-BIT MONOCHROME
16-BIT WORDS
n
n+1
Ya7
Ya6
Ya5
Ya4
Ya3
Ya2
Ya1
Ya0
Yb7
Yb6
Yb5
Yb4
Yb3
Yb2
Yb1
Yb0
n
n+1
X
X
X
X
X
X
X
X
α
O/E
VGT
HGT
X
HRF
LNQ
PXQ
n+2
n+3
Ya7
Ya6
Ya5
Ya4
Ya3
Ya2
Ya1
Ya0
Yb7
Yb6
Yb5
Yb4
Yb3
Yb2
Yb1
Yb0
n+2
n+3
X
X
X
X
X
X
X
X
α
O/E
VGT
HGT
X
HRF
LNQ
PXQ
n+4
n+5
Ya7
Ya6
Ya5
Ya4
Ya3
Ya2
Ya1
Ya0
Yb7
Yb6
Yb5
Yb4
Yb3
Yb2
Yb1
Yb0
n+4
n+5
X
X
X
X
X
X
X
X
α
O/E
VGT
HGT
X
HRF
LNQ
PXQ
Notes
1. α = keying bit; R, G, B, Y, U and V = digital signals; e = even pixel number; o = odd pixel number;
a b c d = consecutive pixels; O/E = odd/even flag
2. YUV 16-bit format: the keying signal α is defined only for YU time steps. The corresponding YV sample has also to
be keyed. The α signal in monochrome mode can be used only in the transparent mode (TTR = 1), in this case
Ya = Yb.
3. Data valid only when transparent mode active (TTR-bit = 1) and VCLK pin connected to LLC/2 clock rate.
May 1993 14
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