INTEGRATED CIRCUITS
SAA7182; SAA7183
Digital Video Encoder (EURO-DENC)
Preliminary specification |
1996 Jul 08 |
Supersedes data of 1995 Sep 19
File under Integrated Circuits, IC22
Philips Semiconductors |
Preliminary specification |
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Digital Video Encoder (EURO-DENC) |
SAA7182; SAA7183 |
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FEATURES
∙CMOS 5 V device
∙Digital PAL/NTSC/SECAM encoder
∙System pixel frequency 13.5 MHz
∙Accepts MPEG decoded data on 8-bit wide input port. Input data format Cb, Y, Cr etc. or Y and Cb, Cr on 16 lines (“CCIR 656”)
∙Three DACs for CVBS, Y and C operating at 27 MHz with 10-bit resolution
∙Three DACs for RGB operating at 27 MHz with 9-bit resolution, RGB sync on CVBS and Y
∙CVBS, Y, C and RGB output simultaneously
∙Closed captioning and teletext encoding including sequencer and filter
∙On-chip YUV to RGB matrix
∙Fast I2C-bus control port (400 kHz)
∙Encoder can be master or slave
∙Programmable horizontal and vertical input synchronization phase
∙Programmable horizontal sync output phase
∙Internal Colour Bar Generator (CBG)
∙Overlay with Look-Up Tables (LUTs) 8 × 3 bytes
∙Macrovision Pay-per-View protection system as option, also used for RGB output
This applies to SAA7183 only. The device is protected by USA patent numbers 461603, 4577216 and 4819098 and other intellectual property rights.
QUICK REFERENCE DATA
Use of the Macrovision anti-copy process in the device is licensed for non-commercial home use only. Reverse engineering or disassembly is prohibited. Please contact your nearest Philips Semiconductor sales office for more information
∙Controlled rise/fall times of output syncs and blanking
∙Down-mode of DACs
∙PLCC84 package.
GENERAL DESCRIPTION
The SAA7182; SAA7183 encodes digital YUV video data to an NTSC, PAL, SECAM CVBS or S-Video signal and also RGB.
The circuit accepts CCIR compatible YUV data with 720 active pixels per line in 4 : 2 : 2 multiplexed formats,
for example MPEG decoded data. It includes a sync/clock generator and on-chip Digital-to-Analog Converters (DACs).
The circuit is compatible to the DIG-TV2 chip family.
SYMBOL |
PARAMETER |
MIN. |
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TYP. |
MAX. |
UNIT |
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VDDA |
analog supply voltage |
4.75 |
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5.0 |
5.25 |
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VDDD |
digital supply voltage |
4.75 |
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5.0 |
5.25 |
V |
IDDA |
analog supply current |
− |
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90 |
110 |
mA |
IDDD |
digital supply current |
− |
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220 |
250 |
mA |
Vi |
input signal voltage levels |
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TTL compatible |
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Vo(p-p) |
analog output signal voltages Y, C, CVBS and RGB |
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2 |
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V |
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without load (peak-to-peak value) |
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RL |
load resistance |
80 |
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Ω |
ILE |
LF integral linearity error |
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±2 |
LSB |
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DLE |
LF differential linearity error |
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±1 |
LSB |
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Tamb |
operating ambient temperature |
0 |
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− |
+70 |
°C |
1996 Jul 08 |
2 |
Philips Semiconductors |
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Preliminary specification |
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Digital Video Encoder (EURO-DENC) |
SAA7182; SAA7183 |
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ORDERING INFORMATION |
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TYPE NUMBER |
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PACKAGE |
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NAME |
DESCRIPTION |
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VERSION |
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SAA7182WP |
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PLCC84 |
plastic leaded chip carrier; 84 leads |
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SOT189-2 |
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SAA7183WP |
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PLCC84 |
plastic leaded chip carrier; 84 leads |
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SOT189-2 |
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BLOCK DIAGRAM
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RTCI |
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RCV1 |
TTXRQ |
XTALO |
LLC |
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Y/C/CVBS |
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RESET SDA SCL SA |
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RCV2 |
CREF |
XTALI |
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VrefH2 |
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VDDA4 |
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CDIR |
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VDDA7 |
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1 |
84 |
83 |
4 |
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37 |
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50 |
35 |
36 |
20 |
47 |
45 |
44 |
48 |
75 |
68 |
64, 70, |
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I2C-bus |
8 |
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72, 74 |
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control |
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I2C-BUS |
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SECAM |
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SYNC |
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INTERFACE |
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PROCESSOR |
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CLOCK |
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10 to 13 |
8 |
I2C-bus |
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clock |
8 |
I2C-bus |
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control |
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DbDr |
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control |
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DP0 |
16 to 19 |
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and timing |
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8 |
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to DP7 |
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Y |
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Y |
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73 |
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25 to 28 |
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CVBS |
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MP7 |
31 to 34 |
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OUTPUT |
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D |
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71 |
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8 |
DATA |
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ENCODER |
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Y |
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to MP0 |
CbCr |
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INTERFACE |
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MANAGER |
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C |
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A |
69 |
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OVL2 |
6 to 8 |
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CHROMA |
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to OVL0 |
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9 |
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KEY |
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8 |
I2C-bus |
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internal |
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8 |
I2C-bus |
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67 |
VSSA |
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I2C-bus |
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control |
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control |
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control bus |
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76 |
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control |
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VrefL2 |
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52 |
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2 |
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VrefL1 |
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21 |
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8 |
C-bus |
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TTX |
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SAA7182 |
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I |
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control |
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3 |
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SAA7183 |
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D |
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61 |
RED |
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Y |
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RGB |
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58 |
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GREEN |
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CbCr |
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PROCESSOR |
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A |
55 |
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BLUE |
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3, 15, 24, |
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5, 14, 22, |
2, 23, 40, 43, |
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54, |
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30, 39, 42, |
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29, 38, 41, |
46, 56, 59, |
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77 |
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51, 79, 81 |
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49, 80, 82 |
62, 65, 66 |
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53 |
63 |
57, 60 |
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VSSD1 |
VDDD1 |
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n.c. |
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SP |
AP |
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V |
refH1 |
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VDDA1 |
MGB696 |
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IRGB |
to |
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VSSD9 |
VDDD9 |
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VDDA3 |
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Fig.1 |
Block diagram. |
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1996 Jul 08 |
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3 |
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Philips Semiconductors |
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Preliminary specification |
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Digital Video Encoder (EURO-DENC) |
SAA7182; SAA7183 |
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PINNING |
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SYMBOL |
PIN |
DESCRIPTION |
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1 |
Reset input, active LOW. After reset is applied, all digital I/Os are in input mode. |
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RESET |
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The I2C-bus receiver waits for the START condition. |
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n.c. |
2 |
not connected |
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VSSD1 |
3 |
digital ground 1 |
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SA |
4 |
The I2C-bus slave address select pin. LOW: slave address = 88H, HIGH = 8CH. |
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VDDD1 |
5 |
digital supply voltage 1 |
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OVL2 |
6 |
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OVL1 |
7 |
3-bit overlay data input. This is the index for the internal look-up table. |
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OVL0 |
8 |
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KEY |
9 |
Key input for OVL. When HIGH it selects OVL input. |
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DP0 |
10 |
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DP1 |
11 |
Lower 4 bits of the data port. Input for multiplexed Cb, Cr data if 16 line input mode is used. |
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DP2 |
12 |
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DP3 |
13 |
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VDDD2 |
14 |
digital supply voltage 2 |
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VSSD2 |
15 |
digital ground 2 |
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DP4 |
16 |
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DP5 |
17 |
Upper 4 bits of the data port. Input for multiplexed Cb, Cr data if 16 line input mode is used. |
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DP6 |
18 |
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DP7 |
19 |
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TTXRQ |
20 |
Teletext request output, indicating when the bitstream is valid. |
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TTX |
21 |
Teletext bitstream input. |
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VDDD3 |
22 |
digital supply voltage 3 |
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n.c. |
23 |
not connected |
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VSSD3 |
24 |
digital ground 3 |
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MP7 |
25 |
Upper 4 bits of MPEG port. It is an input for “CCIR 656” style multiplexed Cb, Y, Cr data, or |
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input for Y data only, if 16 line input mode is used. |
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MP6 |
26 |
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MP5 |
27 |
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MP4 |
28 |
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VDDD4 |
29 |
digital supply voltage 4 |
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VSSD4 |
30 |
digital ground 4 |
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MP3 |
31 |
Lower 4 bits of MPEG port. It is an input for “CCIR 656” style multiplexed Cb, Y, Cr data, or |
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input for Y data only, if 16 line input mode is used. |
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MP2 |
32 |
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MP1 |
33 |
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MP0 |
34 |
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RCV1 |
35 |
Raster Control 1 for video port. This pin receives/provides a VS/FS/FSEQ signal. |
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RCV2 |
36 |
Raster Control 2 for video port. This pin provides an HS pulse of programmable length or |
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receives an HS pulse. |
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RTCI |
37 |
Real Time Control Input. If the LLC clock is provided by an SAA7111 or SAA7151B, RTCI |
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should be connected to the RTCO pin of the respective decoder to improve the signal quality. |
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1996 Jul 08 |
4 |
Philips Semiconductors |
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Preliminary specification |
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Digital Video Encoder (EURO-DENC) |
SAA7182; SAA7183 |
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SYMBOL |
PIN |
DESCRIPTION |
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VDDD5 |
38 |
digital supply voltage 5 |
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VSSD5 |
39 |
digital ground 5 |
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n.c. |
40 |
not connected |
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VDDD6 |
41 |
digital supply voltage 6 |
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VSSD6 |
42 |
digital ground 6 |
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n.c. |
43 |
not connected |
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XTALI |
44 |
Crystal oscillator input (from crystal). If the oscillator is not used, this pin should be connected |
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to ground. |
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XTALO |
45 |
Crystal oscillator output (to crystal). |
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n.c. |
46 |
not connected |
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CREF |
47 |
Clock Reference signal. This is the clock qualifier for DIG-TV2 compatible signals. |
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LLC |
48 |
Line-Locked Clock. This is the 27 MHz master clock for the encoder. The I/O direction is set |
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by the CDIR pin. |
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VDDD7 |
49 |
digital supply voltage 7 |
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CDIR |
50 |
Clock direction. If the CDIR input is HIGH, the circuit receives a clock and optional CREF |
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signal, otherwise if CDIR is LOW CREF and LLC are generated by the internal crystal |
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oscillator. |
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VSSD7 |
51 |
digital ground 7 |
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VrefL1 |
52 |
Lower reference voltage 1 input for the RGB DACs, connect to VSSA. |
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VrefH1 |
53 |
Upper reference voltage 1 input for the RGB DACs, connect via 100 nF capacitor to VSSA. |
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VDDA1 |
54 |
Analog supply voltage 1 for the RGB DACs. |
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BLUE |
55 |
Analog output of the BLUE component. |
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n.c. |
56 |
not connected |
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VDDA2 |
57 |
Analog supply voltage 2 for the RGB DACs. |
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GREEN |
58 |
Analog output of the GREEN component. |
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n.c. |
59 |
not connected |
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VDDA3 |
60 |
Analog supply voltage 3 for the RGB DACs. |
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RED |
61 |
Analog output of the RED component. |
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n.c. |
62 |
not connected |
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IRGB |
63 |
Current input for RGB amplifiers, connected via 15 kΩ resistor to VDDA. |
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VDDA4 |
64 |
Analog supply voltage 4 for the Y/C/CVBS DACs. |
|
n.c. |
65 |
not connected |
|
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|
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n.c. |
66 |
not connected |
|
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|
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VSSA |
67 |
Analog ground for the DACs. |
|
IY/C/CVBS |
68 |
Current input for the Y/C/CVBS amplifiers, connected via 15 kΩ resistor to VDDA. |
|
CHROMA |
69 |
Analog output of the chrominance signal. |
|
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|
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VDDA5 |
70 |
Analog supply voltage 5 for the Y/C/CVBS DACs. |
|
Y |
71 |
Analog output of the luminance signal. |
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VDDA6 |
72 |
Analog supply voltage 6 for the Y/C/CVBS DACs. |
|
CVBS |
73 |
Analog output of the CVBS signal. |
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1996 Jul 08 |
5 |
Philips Semiconductors |
|
Preliminary specification |
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Digital Video Encoder (EURO-DENC) |
SAA7182; SAA7183 |
||
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SYMBOL |
PIN |
DESCRIPTION |
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VDDA7 |
74 |
Analog supply voltage 6 for the Y/C/CVBS DACs. |
|
VrefH2 |
75 |
Upper reference voltage 2 input for the Y/C/CVBS DACs, connected via 100 nF capacitor to |
|
|
|
VSSA. |
|
VrefL2 |
76 |
Lower reference voltage 2 input for the Y/C/CVBS DACs, connect to VSSA. |
|
AP |
77 |
Test pin. Connected to digital ground for normal operation. |
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SP |
78 |
Test pin. Connected to digital ground for normal operation. |
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VSSD8 |
79 |
digital ground 8 |
|
VDDD8 |
80 |
digital supply voltage 8 |
|
VSSD9 |
81 |
digital ground 9 |
|
VDDD9 |
82 |
digital supply voltage 9 |
|
SCL |
83 |
I2C-bus serial clock input. |
|
SDA |
84 |
I2C-bus serial data input/output. |
|
1996 Jul 08 |
6 |
Philips Semiconductors |
Preliminary specification |
|
|
Digital Video Encoder (EURO-DENC) |
SAA7182; SAA7183 |
|
|
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DP1 |
DP0 |
KEY |
OVL0 |
OVL1 |
OVL2 |
DDD1 |
SA |
SSD1 |
n.c. |
RESET |
SDA |
SCL |
DDD9 |
SSD9 |
DDD8 |
SSD8 |
SP |
AP |
refL2 |
refH2 |
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V |
V |
V |
V |
V |
V |
V |
V |
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|||||||||||||
|
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
84 |
83 |
82 |
81 |
80 |
79 |
78 |
77 |
76 |
75 |
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DP2 |
12 |
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74 |
VDDA7 |
DP3 |
13 |
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73 |
CVBS |
VDDD2 |
14 |
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72 |
VDDA6 |
VSSD2 |
15 |
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71 |
Y |
DP4 |
16 |
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70 |
VDDA5 |
DP5 |
17 |
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69 |
CHROMA |
DP6 |
18 |
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68 |
IY/C/CVBS |
DP7 |
19 |
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67 |
VSSA |
TTXRQ |
20 |
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66 |
n.c. |
TTX |
21 |
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SAA7182 |
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65 |
n.c. |
||
VDDD3 |
22 |
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64 |
VDDA4 |
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SAA7183 |
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n.c. |
23 |
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63 |
IRGB |
VSSD3 |
24 |
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62 |
n.c. |
MP7 |
25 |
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61 |
RED |
MP6 |
26 |
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60 |
VDDA3 |
MP5 |
27 |
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59 |
n.c. |
MP4 |
28 |
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58 |
GREEN |
VDDD4 |
29 |
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57 |
VDDA2 |
VSSD4 |
30 |
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56 |
n.c. |
MP3 |
31 |
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55 |
BLUE |
MP2 |
32 |
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54 |
VDDA1 |
|
33 |
34 |
35 |
36 |
37 |
38 |
39 |
40 |
41 |
42 |
43 |
44 |
45 |
46 |
47 |
48 |
49 |
50 |
51 |
52 |
53 |
|
|
MP1 |
MP0 |
RCV1 |
RCV2 |
RTCI |
DDD5 |
SSD5 |
n.c. |
DDD6 |
SSD6 |
n.c. |
XTALI |
XTALO |
n.c. |
CREF |
LLC |
DDD7 |
CDIR |
SSD7 |
refL1 |
refH1 |
MGB697 |
|
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|||||||||||||||||||||
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V |
V |
V |
V |
V |
V |
V |
V |
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Fig.2 |
Pin configuration. |
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||||
1996 Jul 08 |
|
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|
7 |
|
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|
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|
|
|
|
|
|
|
Philips Semiconductors |
Preliminary specification |
|
|
Digital Video Encoder (EURO-DENC) |
SAA7182; SAA7183 |
|
|
FUNCTIONAL DESCRIPTION
The digital video encoder (EURO-DENC) encodes digital luminance and colour difference signals into analog CVBS and simultaneously S-Video signals. NTSC-M, PAL B/G and SECAM standards and sub-standards are supported.
Both interlaced and non-interlaced operation is possible for all standards.
In addition to RED, GREEN and BLUE converted components, the dematrixed YUV input is available on three separate analog outputs.
The basic encoder function consists of subcarrier generation and colour modulation also insertion of synchronization signals. Luminance and chrominance signals are filtered in accordance with the standard requirements of RS-170-A and “CCIR 624”.
For ease of analog post filtering the signals are twice oversampled with respect to the pixel clock before digital-to-analog conversion.
For total filter transfer characteristics see
Figs 3, 4, 5, 6, 7 and 8. The DACs for Y, C and CVBS are realized with full 10-bit resolution, DACs for RGB are with 9-bit resolution.
The MPEG port (MP) accept 8 lines multiplexed Cb-Y-Cr data.
The 8-bit multiplexed Cb-Y-Cr formats are “CCIR 656” (D1 format) compatible, but the SAV, EAV etc. codes are not decoded.
Alternatively, 8-bits Y on MP port and 8-bit multiplexed Cb, Cr on DP port can be chosen as input.
A crystal-stable master clock (LLC) of 27 MHz, which is twice the CCIR line-locked pixel clock of 13.5 MHz, needs to be supplied externally. Optionally, a crystal oscillator input/output pair of pins and an on-chip clock driver is provided.
It is also possible to connect a Philips Digital Video Decoder (SAA7111 or SAA7151B) in conjunction with a CREF clock qualifier to EURO-DENC. Via RTCI pin connected to RTCO of a decoder, information concerning actual subcarrier, PAL-ID (see “data sheet SAA7111” ) definite subcarrier phase can be inserted.
The EURO-DENC synthesizes all necessary internal signals, colour subcarrier frequency, and synchronization signals, from that clock. The encoder is always timing master for the MPEG port (MP), but it can additionally be configured as slave with respect to the RCV trigger inputs.
European teletext encoding is supported if an appropriate teletext bitstream is applied to the TTX pin.
The IC also contains Closed Caption and Extended Data Services Encoding (Line 21), and supports anti-taping signal generation in accordance with Macrovision; it also supports overlay via KEY and three control bits by a 24 × 8 LUT.
A number of possibilities are provided for setting of different video parameters such as:
Black and blanking level control
Colour subcarrier frequency
Variable burst amplitude etc.
During reset (RESET = LOW) and after reset is released, all digital I/O stages are set to input mode. A reset forces the I2C-bus interface to abort any running bus transfer and sets register 3A to 03H, register 61 to 06H and
registers 6BH and 6EH to 00H. All other control registers are not influenced by a reset.
Data manager
In the data manager, real time arbitration on the data stream to be encoded is performed.
Depending on the polarity of pin KEY, the MP input
(or MP/DP input) or OVL input are selected to be encoded to CVBS and Y/C signals, and output as RGB.
KEY controls OVL entries of a programmable LUT for encoded signals and for RGB output. The common KEY switching signal can be disabled by software for the signals to be encoded (Y, C and CVBS), such that OVL will appear on RGB outputs, but not on Y, C and CVBS.
OVL input under control of KEY can be also used to insert decoded teletext information or other on-screen data.
Optionally, the OVL colour LUTs located in this block, can be read out in a pre-defined sequence (8 steps per active video line), achieving, for example, a colour bar test pattern generator without need for an external data source. The colour bar function is only under software control.
1996 Jul 08 |
8 |
Philips Semiconductors |
Preliminary specification |
|
|
Digital Video Encoder (EURO-DENC) |
SAA7182; SAA7183 |
|
|
Encoder
VIDEO PATH
The encoder generates out of Y, U and V baseband signals luminance and colour subcarrier output signals, suitable for use as CVBS or separate Y and C signals.
Luminance is modified in gain and in offset (latter programmable in a certain range to enable different black level set-ups). After having been inserted a fixed synchronization level, in accordance with standard composite synchronization schemes, and blanking level, programmable also in a certain range to allow for manipulations with Macrovision anti-taping, additional insertion of AGC super-white pulses, programmable in height, is supported.
In order to enable easy analog post filtering, luminance is interpolated from 13.5 MHz data rate to 27 MHz data rate, providing luminance in 10-bit resolution. This filter is also used to define smoothed transients for synchronization pulses and blanking period. For transfer characteristic of the luminance interpolation filter see Figs 5 and 6.
Chrominance is modified in gain (programmable separately for U and V), standard dependent burst is inserted, before baseband colour signals are interpolated from 6.75 MHz data rate to 27 MHz data rate. One of the interpolation stages can be bypassed, thus providing a higher colour bandwidth, which can be made use of for Y/C output. For transfer characteristics of the chrominance interpolation filter see Figs 3 and 4.
The amplitude of inserted burst is programmable in a certain range, suitable for standard signals and for special effects. Behind the succeeding quadrature modulator, colour in 10-bit resolution is provided on subcarrier.
The numeric ratio between Y and C outputs is in accordance with set standards.
TELETEXT INSERTION AND ENCODING
Pin TTX receives a teletext bitstream sampled at the LLC clock, each teletext bit is carried by four or three LLC samples.
Phase variant interpolation is achieved on this bitstream in the internal teletext encoder, providing sufficient small phase jitter on the output text lines.
TTXRQ provides a fully programmable request signal to the teletext source, indicating the insertion period of bitstream at lines selectable independently for both fields. The internal insertion window for text is set to 360 teletext bits including clock run-in bits. For protocol and timing see Fig.17.
CLOSED CAPTION ENCODER
Using this circuit, data in accordance with the specification of Closed Caption or Extended Data Service, delivered by the control interface, can be encoded (Line 21). Two dedicated pairs of bytes (two bytes per field), each pair preceded by run-in clocks and framing code, are possible.
The actual line number where data is to be encoded in, can be modified in a certain range.
Data clock frequency is in accordance with definition for NTSC-M standard 32 times horizontal line frequency.
Data LOW at the output of the DACs corresponds to 0 IRE, data HIGH at the output of the DACs corresponds to approximately 50 IRE.
It is also possible to encode Closed Caption Data for 50 Hz field frequencies at 32 times horizontal line frequency.
ANTI-TAPING (SAA7183 ONLY)
For more information contact your nearest Philips Semiconductors sales office.
RGB processor
This block contains a dematrix in order to produce RED, GREEN and BLUE signals to be fed to a SCART plug.
Before Y, Cb, Cr signals are dematrixed, 2 times oversampling for luminance and 4 times oversampling for colour difference signals is performed. For transfer curves of luminance and colour difference components of RGB see Figs 7 and 8.
SECAM processor
SECAM specific pre-processing is achieved in this block by a pre-emphasis of colour difference signals (for gain and phase see Figs 9 and 10.
A baseband frequency modulator with a reference frequency shifted from 4.286 MHz to DC carries out SECAM modulation in accordance with appropriate standard or optionally wide clipping limits.
After the HF pre-emphasis, also applied on a DC reference carrier (anti-Cloche filter; see Figs 11 and 12), line-by-line sequential carriers with black reference of 4.25 MHz (Db) and 4.40625 MHz (Dr) are generated using specified values for FSC programming bytes.
Alternating phase reset in accordance with SECAM standard is carried out automatically. During vertical blanking the so-called bottle pulses are not provided.
1996 Jul 08 |
9 |
Philips Semiconductors |
Preliminary specification |
|
|
Digital Video Encoder (EURO-DENC) |
SAA7182; SAA7183 |
|
|
Output interface/DACs
In the output interface encoded both Y and C signals are converted from digital-to-analog in 10-bit resolution. Y and C signals are also combined to a 10-bit CVBS signal.
The CVBS output occurs with the same processing delay as the Y and C outputs. Absolute amplitudes at the input of the DAC for CVBS is reduced by 15¤16 with respect to Y and C DACs to make maximum use of conversion ranges.
RED, GREEN and BLUE signals are also converted from digital-to-analog, each providing a 9-bit resolution.
Outputs of the DACs can be set together in two groups via software control to minimum output voltage for either purpose.
Synchronization
Synchronization of the EURO-DENC is able to operate in two modes; slave mode and master mode.
In the slave mode, the circuit accepts synchronization pulses at the bidirectional RCV1 port. The timing and trigger behaviour related to RCV1 can be influenced by programming the polarity and on-chip delay of RCV1. Active slope of RCV1 defines the vertical phase and optionally the odd/even and colour frame phase to be initialized, it can be also used to set the horizontal phase.
If the horizontal phase is not be influenced by RCV1, a horizontal pulse needs to be supplied at the RCV2 pin. Timing and trigger behaviour can also be influenced for RCV2.
If there are missing pulses at RCV1 and/or RCV2, the time base of EURO-DENC runs free, thus an arbitrary number of synchronization slopes may miss, but no additional pulses (such with wrong phase) must occur.
If the vertical and horizontal phase is derived from RCV1, RCV2 can be used for horizontal or composite blanking input or output.
In the master mode, the time base of the circuit continuously runs free. On the RCV1 port, the IC can output:
·A Vertical Sync signal (VS) with 3 or 2.5 lines duration, or
·An ODD/EVEN signal which is LOW in odd fields, or
·A field sequence signal (FSEQ) which is HIGH in the first of 4 respectively 8 respectively 12 fields.
On the RCV2 port, the IC can provide a horizontal pulse with programmable start and stop phase; this pulse can be inhibited in the vertical blanking period to build up, for example, a composite blanking signal.
The polarity of both RCV1 and RCV2 is selectable by software control.
Field length is in accordance with 50 Hz or 60 Hz standards, including non-interlaced options; start and end of its active part can be programmed. The active part of a field always starts at the beginning of a line, if the standard blanking option SBLBN is not set.
I2C-bus interface
The I2C-bus interface is a standard slave transceiver, supporting 7-bit slave addresses and 400 kbits/s guaranteed transfer rate. It uses 8-bit subaddressing with an auto-increment function. All registers are write only, except one readable status byte.
Two I2C-bus slave addresses are selected:
88H: LOW at pin 4
8CH: HIGH at pin 4.
Input levels and formats
EURO-DENC expects digital Y, Cb, Cr data with levels (digital codes) in accordance with “CCIR 601”.
For C and CVBS outputs, deviating amplitudes of the colour difference signals can be compensated by independent gain control setting, while gain for luminance is set to predefined values, distinguishable for 7.5 IRE set-up or without set-up.
For RGB outputs fixed amplification in accordance with “CCIR 601” is provided.
Reference levels are measured with a colour bar, 100% white, 100% amplitude and 100% saturation.
1996 Jul 08 |
10 |
Philips Semiconductors |
|
|
|
|
|
Preliminary specification |
||
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|
|
Digital Video Encoder (EURO-DENC) |
|
|
SAA7182; SAA7183 |
|||||
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Table 1 “CCIR 601” signal component levels |
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COLOUR |
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SIGNALS(1) |
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Y |
Cb |
Cr |
|
R(2) |
G(2) |
B(2) |
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||||||
White |
|
235 |
128 |
128 |
|
235 |
235 |
235 |
|
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Yellow |
|
210 |
16 |
146 |
|
235 |
235 |
16 |
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Cyan |
|
170 |
166 |
16 |
|
16 |
235 |
235 |
|
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Green |
|
145 |
54 |
34 |
|
16 |
235 |
16 |
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Magenta |
|
106 |
202 |
222 |
|
235 |
16 |
235 |
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Red |
|
81 |
90 |
240 |
|
235 |
16 |
16 |
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Blue |
|
41 |
240 |
110 |
|
16 |
16 |
235 |
|
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Black |
|
16 |
128 |
128 |
|
16 |
16 |
16 |
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Notes
1.Transformation:
a)R = Y + 1.3707 × (Cr − 128)
b)G = Y − 0.3365 × (Cb − 128) − 0.6982 × (Cb − 128)
c)B = Y + 1.7324 × (Cb − 128).
2.Representation of R, G and B at the output is 9 bits at 27 MHz.
Table 2 8-bit multiplexed format (similar to “CCIR 601”)
TIME |
0 |
|
1 |
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2 |
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2 |
4 |
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5 |
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6 |
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7 |
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Sample |
Cb0 |
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Y0 |
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Cr0 |
|
Y1 |
Cb2 |
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Y2 |
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Cr2 |
|
Y3 |
Luminance pixel number |
0 |
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1 |
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2 |
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3 |
||||
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Colour pixel number |
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0 |
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2 |
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Table 3 16-bit multiplexed format (DTV2 format) |
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TIME |
0 |
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1 |
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2 |
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3 |
4 |
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5 |
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6 |
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7 |
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Sample Y line |
Y0 |
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Y1 |
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Y2 |
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Y3 |
||||
Sample UV line |
Cb0 |
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Cr0 |
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Cb2 |
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Cr2 |
||||
Luminance pixel number |
0 |
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1 |
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2 |
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3 |
||||
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Colour pixel number |
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0 |
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2 |
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1996 Jul 08 |
11 |
08 Jul 1996
12
Bit allocation map
Table 4 Slave Receiver (Slave Address 88H or 8CH)
REGISTER FUNCTION |
SUB |
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DATA BYTE |
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ADDRESS |
D7 |
D6 |
D5 |
D4 |
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D3 |
D2 |
D1 |
D0 |
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Null |
00 |
0 |
0 |
0 |
0 |
|
0 |
0 |
0 |
0 |
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↓ |
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↓ |
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|
|
|
|
|
|
|
|
|
|
|
|
|
Null |
39 |
0 |
0 |
0 |
0 |
|
0 |
0 |
0 |
0 |
|
|
|
|
|
|
|
|
|
|
|
Input port control |
3A |
CBENB |
DISKEY |
0 |
0 |
|
0 |
FMT16 |
Y2C |
UV2C |
|
|
|
|
|
|
|
|
|
|
|
OVL LUT Y0 |
42 |
OVLY07 |
OVLY06 |
OVLY05 |
OVLY04 |
|
OVLY03 |
OVLY02 |
OVLY01 |
OVLY00 |
|
|
|
|
|
|
|
|
|
|
|
OVL LUT U0 |
43 |
OVLU07 |
OVLU06 |
OVLU05 |
OVLU04 |
|
OVLU03 |
OVLU02 |
OVLU01 |
OVLU00 |
|
|
|
|
|
|
|
|
|
|
|
OVL LUT V0 |
44 |
OVLV07 |
OVLV06 |
OVLV05 |
OVLV04 |
|
OVLV03 |
OVLV02 |
OVLV01 |
OVLV00 |
|
|
|
|
|
|
|
|
|
|
|
|
↓ |
|
|
|
|
↓ |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
OVL LUT Y7 |
57 |
OVLY77 |
OVLY76 |
OVLY75 |
OVLY74 |
|
OVLY73 |
OVLY72 |
OVLY71 |
OVLY70 |
|
|
|
|
|
|
|
|
|
|
|
OVL LUT U7 |
58 |
OVLU77 |
OVLU76 |
OVLU75 |
OVLU74 |
|
OVLU73 |
OVLU72 |
OVLU71 |
OVLU70 |
|
|
|
|
|
|
|
|
|
|
|
OVL LUT V7 |
59 |
OVLV77 |
OVLV76 |
OVLV75 |
OVLV74 |
|
OVLV73 |
OVLV72 |
OVLV71 |
OVLV70 |
|
|
|
|
|
|
|
|
|
|
|
Chrominance phase |
5A |
CHPS7 |
CHPS6 |
CHPS5 |
CHPS4 |
|
CHPS3 |
CHPS2 |
CHPS1 |
CHPS0 |
|
|
|
|
|
|
|
|
|
|
|
Gain U |
5B |
GAINU7 |
GAINU6 |
GAINU5 |
GAINU4 |
|
GAINU3 |
GAINU2 |
GAINU1 |
GAINU0 |
|
|
|
|
|
|
|
|
|
|
|
Gain V |
5C |
GAINV7 |
GAINV6 |
GAINV5 |
GAINV4 |
|
GAINV3 |
GAINV2 |
GAINV1 |
GAINV0 |
|
|
|
|
|
|
|
|
|
|
|
Gain U MSB, black level |
5D |
GAINU8 |
0 |
BLCKL5 |
BLCKL4 |
|
BLCKL3 |
BLCKL2 |
BLCKL1 |
BLCKL0 |
|
|
|
|
|
|
|
|
|
|
|
Gain V MSB, blanking level, |
5E |
GAINV8 |
DECTYP |
BLNNL5 |
BLNNL4 |
|
BLNNL3 |
BLNNL2 |
BLNNL1 |
BLNNL0 |
decoder type |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Blanking level VBI |
5F |
0 |
0 |
BLNVB5 |
BLNVB4 |
|
BLNVB3 |
BLNVB2 |
BLNVB1 |
BLNVB0 |
|
|
|
|
|
|
|
|
|
|
|
Null |
60 |
0 |
0 |
0 |
0 |
|
0 |
0 |
0 |
0 |
|
|
|
|
|
|
|
|
|
|
|
Standard control |
61 |
DOWNB |
DOWNA |
INPI |
YGS |
|
SECAM |
SCBW |
PAL |
FISE |
|
|
|
|
|
|
|
|
|
|
|
Burst amplitude |
62 |
RTCE |
BSTA6 |
BSTA5 |
BSTA4 |
|
BSTA3 |
BSTA2 |
BSTA1 |
BSTA0 |
|
|
|
|
|
|
|
|
|
|
|
Subcarrier 0 |
63 |
FSC07 |
FSC06 |
FSC05 |
FSC04 |
|
FSC03 |
FSC02 |
FSC01 |
FSC00 |
|
|
|
|
|
|
|
|
|
|
|
Subcarrier 1 |
64 |
FSC15 |
FSC14 |
FSC13 |
FSC12 |
|
FSC11 |
FSC10 |
FSC09 |
FSC08 |
|
|
|
|
|
|
|
|
|
|
|
Subcarrier 2 |
65 |
FSC23 |
FSC22 |
FSC21 |
FSC20 |
|
FSC19 |
FSC18 |
FSC17 |
FSC16 |
|
|
|
|
|
|
|
|
|
|
|
Subcarrier 3 |
66 |
FSC31 |
FSC30 |
FSC29 |
FSC28 |
|
FSC27 |
FSC26 |
FSC25 |
FSC24 |
|
|
|
|
|
|
|
|
|
|
|
Line 21 odd 0 |
67 |
L21O07 |
L21O06 |
L21O05 |
L21O04 |
|
L21O03 |
L21O02 |
L21O01 |
L21O00 |
|
|
|
|
|
|
|
|
|
|
|
Line 21 odd 1 |
68 |
L21O17 |
L21O16 |
L21O15 |
L21O14 |
|
L21O13 |
L21O12 |
L21O11 |
L21O10 |
|
|
|
|
|
|
|
|
|
|
|
Line 21 even 0 |
69 |
L21E07 |
L21E06 |
L21E05 |
L21E04 |
|
L21E03 |
L21E02 |
L21E01 |
L21E00 |
|
|
|
|
|
|
|
|
|
|
|
Line 21 even 1 |
6A |
L21E17 |
L21E16 |
L21E15 |
L21E14 |
|
L21E13 |
L21E12 |
L21E11 |
L21E10 |
|
|
|
|
|
|
|
|
|
|
|
DENC)-(EURO Encoder Video Digital
SAA7183 SAA7182;
Semiconductors Philips
specification Preliminary