Philips saa7182a, saa7183a DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

SAA7182A; SAA7183A

Digital Video Encoder
(EURO-DENC2)

Preliminary specification
Supersedes data of 1996 Sep 11
File under Integrated Circuits, IC22

1996 Oct 02

Philips Semiconductors Preliminary specification

Digital Video Encoder (EURO-DENC2) SAA7182A; SAA7183A

FEATURES

• Monolithic CMOS 3.3 V device with 5 V input stages

• Digital PAL/NTSC/SECAM encoder

• System pixel frequency 13.5 MHz

• Accepts MPEG decoded data on 8-bit wide input port.

Input data format Cb, Y, Cr etc. “
Y and Cb, Cr on 16 lines

• Three DACs for CVBS, Y and C operating at 27 MHz
with 10 bit resolution

• Three DACs for RGB operating at 27 MHz with 9 bit
resolution, RGB sync on CVBS and Y

• Analog multiplexing between internal RGB and external
RGB on-chip

• CVBS, Y, C and RGB output simultaneously

• Closed captioning and teletext encoding including

sequencer and filter

• Line 23 wide screen signalling encoding

• On-chip Cr, Y, Cb to RGB dematrix, including gain

adjustment for Y and Cr, Cb, optionally to be by-passed
for Cr, Y, Cb output on RGB DACs

2

• Fast I

• Encoder can be master or slave

• Programmable horizontal and vertical input

• Programmable horizontal sync output phase

• Internal Colour Bar Generator (CBG)

• Overlay with Look-Up Tables (LUTs) 8 × 3 bytes

• Macrovision Pay-per-View copy protection system as

C-bus control port (400 kHz)

synchronization phase

option, also used for RGB output.

(CCIR 656)

” or

This applies to SAA7183A only. The device is protected
by USA patent numbers 4631603, 4577216 and
4819098 and other intellectual property rights. Use of
the Macrovision anti-copy process in the device is
licensed for non-commercial home use only.
Reverse engineering or disassembly is prohibited.
Please contact your nearest Philips Semiconductor
sales office for more information

• Controlled rise/fall times of output syncs and blanking

• Down-mode of DACs

• PQFP80 or PLCC84 package.

GENERAL DESCRIPTION

The SAA7182A; SAA7183A encodes digital YUV video
data to an NTSC, PAL, SECAM CVBS or S-Video signal
and also RGB.

Optionally, the YUV to RGB dematrix can be by-passed
providing the digital-to-analog converted Cb, Y, Cr signals
instead of RGB.

The circuit accepts CCIR compatible YUV data with
720 active pixels per line in 4:2:2multiplexed formats,
for example MPEG decoded data. It includes a sync/clock
generator and on-chip Digital-to-Analog Converters
(DACs).

The circuit is compatible to the DIG-TV2 chip family.

ORDERING INFORMATION

TYPE

NUMBER

SAA7182AWP;
SAA7183AWP

1996 Oct 02 2

NAME DESCRIPTION VERSION

PLCC84 plastic leaded chip carrier; 84 leads SOT189-2

QFP80 plastic quad flat package; 80 leads (lead length 1.95 mm);

body 14 × 20 × 2.8 mm

PACKAGE

SOT318-2

Philips Semiconductors Preliminary specification

Digital Video Encoder (EURO-DENC2) SAA7182A; SAA7183A

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V

DDA3

V

DDD3

V

DDD5

I

DDA

I

DDD3

I

DDD5

V

i

V

o(p-p)

R

L

ILE LF integral linearity error −−±2 LSB
DLE LF differential linearity error −−±1 LSB
T

amb

3.3 V analog supply voltage 3.1 3.3 3.5 V

3.3 V digital supply voltage 3.0 3.3 3.6 V
5 V digital supply voltage 4.75 5.0 5.25 V
analog supply current −−110 mA

3.3 V digital supply current −−80 mA
5 V digital supply current −−10 mA
input signal voltage levels TTL compatible
analog output signal voltages Y, C, CVBS and RGB without load

− 1.4 − V

(peak-to-peak value)
load resistance 75 − 300 Ω

operating ambient temperature 0 − +70 °C

1996 Oct 02 3

Philips Semiconductors Preliminary specification

Digital Video Encoder (EURO-DENC2) SAA7182A; SAA7183A

BLOCK DIAGRAM

RTCI

RCV1

TTXRQ

handbook, full pagewidth

RESET SDA SCL

SA

CDIR

RCV2

XTALO

CREF

XTALI

LLC

V

TESTB

DDA4

to V

DDA9

DP0

to

DP7

MP7

to

MP0

OVL2

to

OVL0

KEY

TTX

10 to 13
16 to 19

8

25 to 28
31 to 34

8

6 to 8

3

9

21

3, 15, 24,
30, 39, 42,
51, 79, 81

184834

I2C-BUS

INTERFACE

8

DATA

MANAGER

2

I

C-bus

control

3

V
V

SSD1
SSD9

V



to

DDD1

V

DDD9

2

I

C-bus

control

5, 14, 22, 
29, 38, 46,
49, 80, 82



to

CbCr

I2C-bus

control

SECAM

PROCESSOR

DbDr

Y

ENCODER

2, 23, 40, 41,
43, 66

n.c.

8

8

SAA7182A
SAA7183A

I2C-bus

control

CbCr

SP AP

50 35 36 20 47 45

37

CLOCK

clock

and timing

Y

OUTPUT

C

control bus

Y

78 77

INTERFACE

internal 

PROCESSOR

SYNC

8

8

8

RGB

2

C-bus

I

control

2

C-bus

I

control

2

C-bus

I

control

44 48

75

59 56

GI

D

D

63, 64,
68, 70,
72, 74

A

A

BI

52, 67, 76

54,
57, 60

V

DDA1

to

V

DDA3

73
71
69

53
65
62

61
58
55



MGD668

CVBS
Y
CHROMA

V

SSA1

to

V

SSA3

TESTC
SELI

RI

RED
GREEN
BLUE

Fig.1 Block diagram; PLCC84.

1996 Oct 02 4

Philips Semiconductors Preliminary specification

Digital Video Encoder (EURO-DENC2) SAA7182A; SAA7183A

RTCI

RCV1

TTXRQ

andbook, full pagewidth

RESET SDA SCL

SA

CDIR

RCV2

XTALO

CREF

XTALI

LLC

V

TESTB

DDA4

to V

DDA9

DP0

to

DP7

MP7

to

MP0

OVL2

to

OVL0

KEY

TTX

1 to 4
7 to 10

8

15 to 18
21 to 24

8

77 to 79

3

80

12

6, 14, 20,
29, 31, 39,
67, 69, 74

73 72 71 75

I2C-BUS

INTERFACE

DATA

MANAGER

2

I

C-bus

control

3

V



SSD1

to

V

SSD9

2

I

C-bus

8

control

CbCr

5, 13, 19, 
28, 34, 37,
68, 70, 76 30, 40

V



DDD1

to

V

DDD9

I2C-bus

control

SECAM

PROCESSOR

DbDr

Y

n.c.

8

ENCODER

I2C-bus

8

SAA7182A
SAA7183A

control

CbCr

SP AP

38 25 26 11 35 33

27

CLOCK

clock

and timing

Y

OUTPUT

C

control bus

Y

66 65

INTERFACE

internal 

PROCESSOR

SYNC

8

8

8

RGB

2

C-bus

I

control

2

C-bus

I

control

2

C-bus

I

control

32 36

63

48 45

GI

D

D

52, 53,
56, 58,
60, 62

A

A

BI

41, 55, 64

43,
46, 49

V

DDA1

to

V

DDA3

61
59
57

42
54
51

50
47
44



MGD670

CVBS
Y

CHROMA

V

SSA1

to

V

SSA3

TESTC
SELI

RI

RED
GREEN
BLUE

Fig.2 Block diagram; QFP80.

1996 Oct 02 5

Philips Semiconductors Preliminary specification

Digital Video Encoder (EURO-DENC2) SAA7182A; SAA7183A

PINNING

SYMBOL

DESCRIPTION

PLCC84 QFP80

RESET 1 73 Reset input, active LOW. After reset is applied, all digital I/Os are in input mode.

The I2C-bus receiver waits for the START condition.

n.c. 2 − not connected

PIN

V

SSD1

SA 4 75 The I

3 6 digital ground 1

2

C-bus slave address select input pin. LOW: slave address = 88H,

HIGH = 8CH.

V

DDD1

5 13 digital supply voltage 1 (3.3 V)

OVL2 6 77

3-bit overlay data input. This is the index for the internal look-up table.OVL1 7 78
OVL0 8 79
KEY 9 80 Key input for OVL. When HIGH it selects OVL input.
DP0 10 1
DP1 11 2
DP2 12 3

Lower 4 bits of the data port. Input for multiplexed Cb, Cr data if 16 line input mode

is used.
DP3 13 4

V
V

DDD2
SSD2

14 5 digital supply voltage 2 (5 V)

15 14 digital ground 2
DP4 16 7
DP5 17 8
DP6 18 9

Upper 4 bits of the data port. Input for multiplexed Cb, Cr data if 16 line input mode
is used.

DP7 19 10
TTXRQ 20 11 Teletext request output, indicating when bit stream is valid.
TTX 21 12 Teletext bit stream input.
V

DDD3

22 28 digital supply voltage 3 (3.3 V)
n.c. 23 − not connected
V

SSD3

24 20 digital ground 1
MP7 25 15
MP6 26 16
MP5 27 17

Upper 4 bits of MPEG port. It is an input for “
data, or for Y data only, if 16 line input mode is used.

CCIR 656

” style multiplexed Cb, Y, Cr

MP4 28 18
V
V

DDD4
SSD4

29 19 digital supply voltage 4 (5 V)

30 29 digital ground 4
MP3 31 21
MP2 32 22
MP1 33 23

Lower 4 bits of MPEG port. It is an input for “
data, or for Y data only, if 16 line input mode is used.

CCIR 656

” style multiplexed Cb, Y, Cr

MP0 34 24
RCV1 35 25 Raster Control 1 for video port. This pin receives/provides a VS/FS/FSEQ signal.
RCV2 36 26 Raster Control 2 for video port. This pin provides an HS pulse of programmable

length or receives an HS pulse.

1996 Oct 02 6

Philips Semiconductors Preliminary specification

Digital Video Encoder (EURO-DENC2) SAA7182A; SAA7183A

SYMBOL

DESCRIPTION

PLCC84 QFP80

RTCI 37 27 Real Time Control input. If the LLC clock is provided by an SAA7111 or SAA7151B,

RTCI should be connected to the RTCO pin of the respective decoder to improve
the signal quality.

PIN

V
V

DDD5
SSD5

38 68 digital supply voltage 5 (3.3 V)

39 39 digital ground 5
n.c. 40 40 not connected
n.c. 41 − not connected
V

SSD6

42 31 digital ground 6 for oscillator
n.c. 43 30 not connected
XTALI 44 32 Crystal oscillator input (from crystal). If the oscillator is not used, this pin should be

connected to ground.
XTALO 45 33 Crystal oscillator output (to crystal).
V

DDD6

46 34 digital supply voltage 6 for oscillator (3.3 V)
CREF 47 35 Clock Reference signal. This is the clock qualifier for DIG-TV2 compatible signals.
LLC 48 36 Line-Locked Clock. This is the 27 MHz master clock for the encoder. The I/O

direction is set by the CDIR pin.

V

DDD7

49 37 digital supply voltage 7 (5 V)
CDIR 50 38 Clock direction. If CDIR input is HIGH, the circuit receives a clock and optional

CREF signal, otherwise if CDIR is LOW, CREF and LLC are generated by the

internal crystal oscillator.
V
V

SSD7
SSA1

51 67 digital ground 7

52 41 Analog ground 1 for the DACs.
TESTC 53 42 Analog test pin. Leave open-circuit for normal operation.
V

DDA1

54 43 Analog supply voltage 1 for the RGB DACs (3.3 V).
BLUE 55 44 Analog output of the BLUE component.
BI 56 45 Analog input that can be switched to BLUE when SELI = HIGH.
V

DDA2

57 46 Analog supply voltage 2 for RGB DACs (3.3 V).
GREEN 58 47 Analog output of GREEN component.
GI 59 48 Analog input that can be switched to GREEN when SELI = HIGH.
V

DDA3

60 49 Analog supply voltage 3 for RGB DACs (3.3 V).
RED 61 50 Analog output of RED component.
RI 62 51 Analog input that can be switched to RED when SELI = HIGH.
V
V

DDA4
DDA5

63 52 Analog supply voltage 4 for DACs (3.3 V).

64 53 Analog supply voltage 5 for DACs (3.3 V).
SELI 65 54 Select analog input. Digital-to-analog converted RGB output when SELI = LOW;

RI, GI and BI output when SELI = HIGH.
n.c. 66 − not connected
V
V

SSA2
DDA6

67 55 Analog ground 2 for the DACs.

68 56 Analog supply voltage 6 for DACs (3.3 V).
CHROMA 69 57 Analog output of the chrominance signal.
V

DDA7

70 58 Analog supply voltage 7 for the Y/C/CVBS DACs (3.3 V).

1996 Oct 02 7

Philips Semiconductors Preliminary specification

Digital Video Encoder (EURO-DENC2) SAA7182A; SAA7183A

SYMBOL

DESCRIPTION

PLCC84 QFP80

Y 71 59 Analog output of VBS signal.

PIN

V

DDA8

72 60 Analog supply voltage 8 for the Y/C/CVBS DACs.
CVBS 73 61 Analog output of the CVBS signal.
V

DDA9

74 62 Analog supply voltage 9 for the Y/C/CVBS DACs.
TESTB 75 63 Analog test pin. Leave open-circuit for normal operation.
V

SSA3

76 64 Analog ground 3 for the DACs.
AP 77 65 Test pin. Connected to digital ground for normal operation.
SP 78 66 Test pin. Connected to digital ground for normal operation.
V

SSD8

V

DDD8

V

SSD9

V

DDD9

SCL 83 71 I
SDA 84 72 I

79 69 digital ground 8

80 76 digital supply voltage 8 (3.3 V)

81 74 digital ground 9

82 70 digital supply voltage 9 (5 V)

2

C-bus serial clock input.

2

C-bus serial data input/output.

1996 Oct 02 8

Philips Semiconductors Preliminary specification

Digital Video Encoder (EURO-DENC2) SAA7182A; SAA7183A

handbook, full pagewidth

DP1
11

DP0
10

KEY
9

OVL0
8

OVL1
7

OVL2
6

DDD1

V
5

SA
4

SSD1

V
3

n.c.
2

RESET
1

SDA
84

DDD9VSSD9VDDD8VSSD8

SCL

V

83

82

81

AP
77

SSA3

V
76

TESTB
75

SP

80

79

78

DP3

V

DDD2

V

SSD2

DP4
DP5
DP6
DP7

TTXRQ

TTX

V

DDD3

n.c.

V

SSD3

MP7
MP6
MP5
MP4

V

DDD4

V

SSD4

MP3
MP2

12DP2
13
14
15
16
17
18
19
20
21

74
73
72
71
70
69
68
67
66
65

V

DDA9

CVBS
V

DDA8

Y
V

DDA7

CHROMA
V

DDA6

V

SSA2

n.c.
SELI

SAA7182A

22
23
24
25
26
27
28
29
30
31
32

SAA7183A

64
63
62
61
60
59
58
57
56
55
54

V

DDA5

V

DDA4

RI
RED
V

DDA3

GI
GREEN
V

DDA2

BI
BLUE
V

DDA1

33

34

35

36

37

38

39

40

41

42

n.c.

MP1

MP0

RCV1

RCV2

RTCI

DDD5

V

SSD5

V

n.c.

SSD6

V

Fig.3 Pin configuration; PLCC84.

1996 Oct 02 9

43

n.c.

44

XTALI

45

XTALO

46

DDD6

V

47

CREF

48

LLC

49

DDD7

V

50

CDIR

51

SSD7

V

52

SSA1

V

53

TESTC

MGD669

Philips Semiconductors Preliminary specification

Digital Video Encoder (EURO-DENC2) SAA7182A; SAA7183A

handbook, full pagewidth

DP0
DP1
DP2
DP3

V

DDD2

V

SSD1

DP4
DP5
DP6
DP7

TTXRQ

TTX

V

DDD1

V

SSD2

MP7
MP6
MP5
MP4

V

DDD4

V

SSD3

MP3
MP2
MP1
MP0

KEY

OVL0

OVL1

80

79

78
1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

25

26

27

RCV2

RTCI

RCV1

OVL2
77

28

DDD3

V

DDD8

V
76

29

SSD4

V

SA
75

30
n.c.

SSD9

V

RESET

74

73

SAA7182A
SAA7183A

31

32

SSD6

XTALI

V

SDA
72

33

XTALO

DDD9VSSD8VDDD5VSSD7

SCL

V

71

70

69

34

35

36

CREF

LLC

DDD6

V

68

37

DDD7

V

67

38

CDIR

SP
66

39

SSD5

V

AP
65

40
n.c.

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

MGD671

V

SSA3

TESTB
V

DDA9

CVBS
V

DDA8

Y
V

DDA7

CHROMA
V

DDA6

V

SSA2

SELI
V

DDA5

V

DDA4

RI
RED
V

DDA3

GI
GREEN
V

DDA2

BI
BLUE
V

DDA1

TESTC
V

SSA1

Fig.4 Pin configuration; QFP80.

1996 Oct 02 10

Philips Semiconductors Preliminary specification

Digital Video Encoder (EURO-DENC2) SAA7182A; SAA7183A

FUNCTIONAL DESCRIPTION

The digital video encoder (EURO-DENC2) encodes digital
luminance and colour difference signals into analog CVBS
and simultaneously S-Video signals. NTSC-M, PAL B/G,
SECAM standards and sub-standards are supported.

Both interlaced and non-interlaced operation is possible
for all standards.

In addition, the de-matrixed Y, Cb, and Cr input is
available on three separate analog outputs as RED,
GREEN and BLUE. Under software control the dematrix
can be by-passed to output digital-to-analog converted Cr,
Y, and Cb signals on RGB outputs. Separate digital gain
adjustment for luminance and colour difference signals is
available.

Analog on-chip multiplexing between internal
digital-to-analog converted RGB and external RI, GI and
BI signals is also supported.

The basic encoder function consists of subcarrier
generation, colour modulation and insertion of
synchronization signals. Luminance and chrominance
signals are filtered in accordance with the standard
requirements of “

For ease of analog post filtering the signals are twice
oversampled with respect to the pixel clock before
digital-to-analog conversion.

For total filter transfer characteristics see
Figs 5, 6, 7, 8, 9 and 10. The DACs for Y, C, and CVBS
are realized with full 10-bit resolution, DACs for RGB are
with 9-bit resolution.

The MPEG port (MP) accept 8 line multiplexed Cb, Y, Cr
data.

The 8-bit multiplexed Cb-Y-Cr formats are “
(D1 format) compatible, but the SAV and EAV codes can
be decoded optionally, when the device is to operate in
slave mode.

Alternatively, 8-bits Y on MP port and 8-bit multiplexed Cb,
Cr on DP port can be chosen as input.

A crystal-stable master clock (LLC) of 27 MHz, which is
twice the CCIR line-locked pixel clock of 13.5 MHz, needs
to be supplied externally. Optionally, a crystal oscillator
input/output pair of pins and an on-chip clock driver is
provided.

It is also possible to connect a Philips Digital Video
Decoder (SAA7111 or SAA7151B) in conjunction with a
CREF clock qualifier to EURO-DENC2. Via the RTCI pin,
connected to RTCO of a decoder, information concerning

RS-170-A

” and “

CCIR 624

”.

CCIR 656

”

actual subcarrier, PAL-ID, and if connected to SAA7111,
definite subcarrier phase can be inserted.

The EURO-DENC2 synthesizes all necessary internal
signals, colour subcarrier frequency, and synchronization
signals, from that clock.

European teletext encoding is supported if an appropriate
teletext bitstream is applied to the TTX pin.

2

Wide screen signalling data can be loaded via the I
and is inserted into line 23 for standards using 50 Hz field
rate.

The IC also contains Closed Caption and Extended Data
Services Encoding (Line 21), and supports anti-taping
signal generation in accordance with Macrovision; it also
supports overlay via KEY and three control bits by a
24 × 8 LUT.

A number of possibilities are provided for setting different
video parameters such as:

Black and blanking level control
Colour subcarrier frequency
Variable burst amplitude etc.

During reset (RESET = LOW) and after reset is released,
all digital I/O stages are set to input mode. A reset forces
the I2C-bus interface to abort any running bus transfer and
sets register 3A to 03H, register 61 to 06H and
registers 6BH and 6EH to 00H. All other control registers
are not influenced by a reset.

Data manager

In the data manager, real time arbitration on the data
stream to be encoded is performed.

Depending on the polarity of pin KEY, the MP input
(or MP/DP input) or OVL input are selected to be encoded
to CVBS and Y/C signals, and output as RGB.

KEY controls OVL entries of a programmable LUT for
encoded signals and for RGB output. The common KEY
switching signal can be disabled by software for the
signals to be encoded (Y, C and CVBS), such that OVL will
appear on RGB outputs, but not on Y, C and CVBS.

OVL input under control of KEY can be also used to insert
decoded teletext information or other on-screen data.

Optionally, the OVL colour LUTs located in this block, can
be read out in a pre-defined sequence (8 steps per active
video line), achieving, for example, a colour bar test
pattern generator without need for an external data
source. The colour bar function is only under software
control.

C-bus,

1996 Oct 02 11

Philips Semiconductors Preliminary specification

Digital Video Encoder (EURO-DENC2) SAA7182A; SAA7183A

Encoder

V

IDEO PATH

The encoder generates out of Y, U and V baseband
signals luminance and colour subcarrier output signals,
suitable for use as CVBS or separate Y and C signals.

Luminance is modified in gain and in offset (latter
programmable in a certain range to enable different black
level set-ups). After having been inserted a fixed
synchronization level, in accordance with standard
composite synchronization schemes, and blanking level,
programmable also in a certain range to allow for
manipulations with Macrovision anti-taping, additional
insertion of AGC super-white pulses, programmable in
height, is supported.

In order to enable easy analog post filtering, luminance is
interpolated from 13.5 MHz data rate to 27 MHz data rate,
providing luminance in 10-bit resolution. This filter is also
used to define smoothed transients for synchronization
pulses and blanking period. For transfer characteristic of
the luminance interpolation filter see Figs 7 and 8.

Chrominance is modified in gain (programmable
separately for U and V), standard dependent burst is
inserted, before baseband colour signals are interpolated
from 6.75 MHz data rate to 27 MHz data rate. One of the
interpolation stages can be bypassed, thus providing a
higher colour bandwidth, which can be made use of for
Y and C output. For transfer characteristics of the
chrominance interpolation filter see Figs 5 and 6.

The amplitude of inserted burst is programmable in a
certain range, suitable for standard signals and for special
effects. Behind the succeeding quadrature modulator,
colour in 10-bit resolution is provided on subcarrier.

The numeric ratio between Y and C outputs is in
accordance with set standards.

ELETEXT INSERTION AND ENCODING

T

C

LOSED CAPTION ENCODER

Using this circuit, data in accordance with the specification
of Closed Caption or Extended Data Service, delivered by
the control interface, can be encoded (Line 21).
Two dedicated pairs of bytes (two bytes per field), each
pair preceded by run-in clocks and framing code, are
possible.

The actual line number where data is to be encoded in, can
be modified in a certain range.

Data clock frequency is in accordance with definition for
NTSC-M standard 32 times horizontal line frequency.

Data LOW at the output of the DACs corresponds to 0 IRE,
data HIGH at the output of the DACs corresponds to
approximately 50 IRE.

It is also possible to encode Closed Caption Data for 50 Hz
field frequencies at 32 times horizontal line frequency.

NTI-TAPING (SAA7183A ONLY)

A
For more information contact your nearest Philips

Semiconductors sales office.

RGB processor

This block contains a dematrix in order to produce RED,
GREEN and BLUE signals to be fed to a SCART plug.

Before Y, Cb and Cr signals are de-matrixed, individual
gain adjustment for Y and colour difference signals and
2 times oversampling for luminance and 4 times
oversampling for colour difference signals is performed.
For transfer curves of luminance and colour difference
components of RGB see Figs 9 and 10.

SECAM processor

SECAM specific pre-processing is achieved in this block
by a pre-emphasis of colour difference signals (for gain
and phase see Figs 11 and 12).

Pin TTX receives a teletext bitstream sampled at the LLC
clock, each teletext bit is carried by four or three LLC
samples.

Phase variant interpolation is achieved on this bitstream in
the internal teletext encoder, providing sufficient small
phase jitter on the output text lines.

TTXRQ provides a fully programmable request signal to
the teletext source, indicating the insertion period of
bitstream at lines selectable independently for both fields.
The internal insertion window for text is set to 360 teletext
bits including clock run-in bits. For protocol and timing
see Fig.19.

1996 Oct 02 12

A baseband frequency modulator with a reference
frequency shifted from 4.286 MHz to DC carries out
SECAM modulation in accordance with appropriate
standard or optionally wide clipping limits.

After the HF pre-emphasis, also applied on a DC reference
carrier (anti-Cloche filter; see Figs 13 and 14), line-by-line
sequential carriers with black reference of 4.25 MHz (Db)
and 4.40625 MHz (Dr) are generated using specified
values for FSC programming bytes.

Alternating phase reset in accordance with SECAM
standard is carried out automatically. During vertical
blanking the so-called bottle pulses are not provided.

Philips Semiconductors Preliminary specification

Digital Video Encoder (EURO-DENC2) SAA7182A; SAA7183A

Output interface/DACs

In the output interface encoded both Y and C signals are
converted from digital-to-analog in 10-bit resolution.
Y and C signals are also combined to a 10-bit CVBS
signal.

The CVBS output occurs with the same processing delay
as the Y and C outputs. Absolute amplitudes at the input
of the DAC for CVBS is reduced by15⁄16 with respect to
Y and C DACs to make maximum use of conversion
ranges.

RED, GREEN and BLUE signals are also converted from
digital-to-analog, each providing a 9-bit resolution. It is
also possible to feed through three external analog RGB
signals at pins RI, BI and GI when pin SELI = HIGH

Outputs of the DACs can be set together in two groups via
software control to minimum output voltage for either
purpose.

Synchronization

Synchronization of the EURO-DENC2 is able to operate in
two modes; slave mode and master mode.

In the slave mode, the circuit accepts synchronization
pulses at the bidirectional RCV1 port. The timing and
trigger behaviour related to RCV1 can be influenced by
programming the polarity and on-chip delay of RCV1.
Active slope of RCV1 defines the vertical phase and
optionally the odd/even and colour frame phase to be
initialized, it can be also used to set the horizontal phase.

If the horizontal phase is not to be influenced by RCV1, a
horizontal pulse needs to be supplied at the RCV2 pin.
Timing and trigger behaviour can also be influenced for
RCV2.

If there are missing pulses at RCV1 and/or RCV2, the time
base of EURO-DENC2 runs free, thus an arbitrary number
of synchronization slopes may miss, but no additional
pulses (with the incorrect phase) must occur.

If the vertical and horizontal phase is derived from RCV1,
RCV2 can be used for horizontal or composite blanking
input or output.

Alternatively, the device can be triggered by auxiliary
codes in a

CCIR 656

data stream at the MP port

• A Vertical Sync signal (VS) with 3 or 2.5 lines duration,
or;

• An ODD/EVEN signal which is LOW in odd fields, or;

• A field sequence signal (FSEQ) which is HIGH in the first

of 4, 8, 12 fields respectively.

On the RCV2 port, the IC can provide a horizontal pulse
with programmable start and stop phase; this pulse can be
inhibited in the vertical blanking period to build up, for
example, a composite blanking signal.

The polarity of both RCV1 and RCV2 is selectable by
software control.

The length of a field and the start and end of its active part
can be programmed. The active part of a field always
starts at the beginning of a line.

2

I

C-bus interface

The I2C-bus interface is a standard slave transceiver,
supporting 7-bit slave addresses and 400 kbits/s
guaranteed transfer rate. It uses 8-bit subaddressing with
an auto-increment function. All registers are write only,
except one readable status byte.

Two I2C-bus slave addresses are selected:

88H: LOW at pin SA
8CH: HIGH at pin SA.

Input levels and formats

EURO-DENC2 expects digital Y, Cb, Cr data with levels
(digital codes) in accordance with

For C and CVBS outputs, deviating amplitudes of the
colour difference signals can be compensated by
independent gain control setting, while gain for luminance
is set to predefined values, distinguishable for 7.5 IRE
set-up or without set-up.

For RGB outputs variable amplification of the Y, Cb and Cr
components is provided, enabling adjustment of contrast
and colour saturation in certain range.

Reference levels are measured with a colour bar,
100% white, 100% amplitude and 100% saturation.

“CCIR 601”

.

In the master mode, the time base of the circuit
continuously runs free. On the RCV1 port, the IC can
output:

1996 Oct 02 13

Philips Semiconductors Preliminary specification

Digital Video Encoder (EURO-DENC2) SAA7182A; SAA7183A

Table 1

“CCIR 601”

COLOUR

signal component levels

SIGNALS

YCbCrR

(1)

(2)

(2)

G

B

White 235 128 128 235 235 235
Yellow 210 16 146 235 235 16
Cyan 170 166 16 16 235 235
Green 145 54 34 16 235 16
Magenta 106 202 222 235 16 235
Red 81 90 240 235 16 16
Blue 41 240 110 16 16 235
Black 16 128 128 16 16 16

Notes

1. Transformation:
a) R = Y + 1.3707 × (Cr − 128)
b) G = Y − 0.3365 × (Cb − 128) − 0.6982 × (Cr − 128)
c) B = Y + 1.7324 × (Cb − 128).

2. Representation of R, G and B (or Cr, Y and Cb) at the output is 9 bits at 27 MHz.

Table 2 8-bit multiplexed format (similar to

“CCIR 601”

)

(2)

TIME

BITS

01224567

Sample Cb

0

Y

0

Cr

0

Y

1

Cb

2

Y

2

Cr

2

Y

3

Luminance pixel number 0123
Colour pixel number 0 2

Table 3 16-bit multiplexed format (DTV2 format)

BITS

TIME

01234567

Sample Y line Y
Sample UV line Cb

0

0

Y

Cr

1

0

Y

Cb

Cr

Y

3

2

2

2

Luminance pixel number 0123
Colour pixel number 0 2

1996 Oct 02 14